TWI359214B - Electroplating method - Google Patents

Electroplating method Download PDF

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Publication number
TWI359214B
TWI359214B TW093132441A TW93132441A TWI359214B TW I359214 B TWI359214 B TW I359214B TW 093132441 A TW093132441 A TW 093132441A TW 93132441 A TW93132441 A TW 93132441A TW I359214 B TWI359214 B TW I359214B
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TW
Taiwan
Prior art keywords
metal
solid
plating
tin
anode
Prior art date
Application number
TW093132441A
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English (en)
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TW200533792A (en
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Renesas Electronics Corp
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Publication of TW200533792A publication Critical patent/TW200533792A/zh
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Publication of TWI359214B publication Critical patent/TWI359214B/zh

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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/56—Electroplating: Baths therefor from solutions of alloys
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1359214 九、發明說明： 【發明所屬之技術領域】 本發明係關於電氣鍍敷（電解鍍敷）技術，特別是關於適用 於半導體裝置之製造製程中之鍍敷步驟之有效技術者。 【先前技術】 於使用引線框而製造半導體裝置中，為確保於基板焊接 安裝時之焊錫可濕性，於引線之外部連接用端子部形成有 合金鍍敷層。作為該合金鍍敷層，主要使用pb(鉛）_Sn(鋅） 組成之合金鍍敷層，近年來因環境保護之關係限制使用 Pb，於合金鍍敷層中亦進展為無鉛化。 作為無鉛組成之合金鍍敷層，提出有各種組成者並得以 實用化，其中之一、眾所周知有SnBi組成之合金鍍敷層 (Sn-Bi合金鍍敷層）。關於該Sn_Bi合金鍍敷層，例如揭示於 曰本專利特公平7-65206號公報（專利文獻丨）。又，於該專利 文獻1中，亦揭示有以電氣鍍敷法形成Sn_Bi合金鍍敷層之 技術。 【專利文獻1】日本專利特公平7_652〇6號公報 [發明所欲解決之問題] 本發明者對於半導體裝置製造製程中之鍍敷步驟研究之 結果，發現以下問題點。 鍍敷步驟中，以電氣鍍敷法形成Sn_Bi合金層。電氣鍍敷 法係藉由電場反應自鍍敷液（金屬鹽溶液）電解析出金屬至 被鍍敷處理物（導電體表面）並形成合金鍍敷層之方法。將引 線框（被鍍敷處理物）浸入包含錫及鉍之鍍敷液中，將配置於 96953.doc -6 - 1359214 鑛敷液中之固體錫金屬連接於陽極，將引線框連接於陰極 進行Sn-Bi合金層之形成。 以此方式形成Sn-Bi合金鐘敷層之情形時，若重複锻敷處 理之操作則鍵敷液中之錫及祕濃度減少，故而必須供給錫 及錢至鍍敷液中。鍍敷液中錫之供給藉由於鍍敷液中電解 溶出固體錫金屬之處理進行。另一方面，鍍敷液中叙之供 給藉由補充鉍溶液至鍍敷液中之處理進行。該鉍溶液之補 充因半導體裝置之引線根數或引線框之大小而不同，以半 導體裝置之個數為基準之情形時’例如需要以一次兩萬個 之比例進行。又，鉍溶液之補充必須停止電氣鍍敷裝置而 進行，一次之補充時間需要15分鐘至20分鐘。即，為液體 補充鍵敷液中銀之減少部分’必須以一次一小時之比例停 止電氣鍍敷裝置，故而降低電氣鍍敷裝置之運轉率（鍍敷處 理數）。該電氣鍍敷裝置之運轉率（鍍敷處理數）降低成為增 加半導體裝置之成本之主要因素。 又，藉由鉍溶液供給鍍敷液中之鉍時，自補充鉍溶液後 至補充下一次鉍溶液為止期間於鍍敷液中之鉍濃度產生不 穩定，故而於生成之Sn_Bi合金層之組成比容易產生不均 一。該組成比之不均一成為降低半導體裝置之安裝可靠性 之主要因素。 本發明之目的在於提供-種可提高電氣锻敷裝置之運轉 率（鍍敷處理數增加）的電氣鍍敷技術。 本發明之其他目的在於提供一種可降低半導體裝置成本 之技術。 96953.doc 1359214 本發明之其他目的在於提供一種可提高半導體裝置之安 裝可靠性之技術。 本發明之上述及其他目的與新特徵藉由本說明書之記述 以及附圖可明白。 【發明内容】 本申請案揭示之發明中，以代表性者之概要加以簡單說 明如下。 (1) 一種電氣鍍敷方法，係將被鍍敷處理物浸入包含錫及 鉍之鍍敷液中，於上述被鍍敷處理物之表面形成錫·鉍合金 鍍敷層之方法， 該方法係將配置於上述鍍敷液中之固體錫金屬及固體鉍 金屬連接於陽極，將上述被鍍敷處理物連接於陰極而進行 者。 (2) —種電氣鍵敷方法，係將被鑛敷處理物配置於包含錫 及鉍之鍍敷液中，於上述被鍍敷處理物之表面形成錫_鉍合 金锻敷層之方法， 該方法係將以與上述被鍍敷處理物保持特定之間隔並夾 住上述被鍍敷處理物之方式配置於上述鍍敷液中之複數個 金屬製盒子連接於陽極，該盒子分別收容固體錫金屬及固 體鉍金屬， 將上述被艘敷處理物連接於陰極而進行。 (3) 種半導體之製造方法，包含準備經樹脂密封之半導 體晶片及含有電性連接於上述半導體晶片之電極之引線之 引線框之（a)步驟， 96953.doc 1359214 將上述引線框浸入包含錫及鉍之鍍敷液中，於上述引線 形成錫·鉍合金鍍敷層之步驟， 上述（b)步驟係將配置於上述鍍敷液中之固體錫金屬及固 體鉍金屬連接於陽極，將上述引線框連接於陰極而進行。 再者，本發明者基於發明之結果，關於形成SnBi合金鍍 敷層之電氣鍍敷法進行先行技術之調查。其結果是，選出 上述專利文獻1(日本專利特公平7_652〇6號公報卜於專利文 獻1中，揭示有「於陽極使用鉍金屬，藉由上述鉍金屬陽極 之電解溶出對相應於自鍍敷液之鉍之析出而補給鉍離子， 並藉由於鍍敷液中添加溶解亞錫鹽或氧化亞錫之處理對應 於自鍍敷液之錫析出而補給亞錫離子」技術。該專利文獻i 之鍍敷技術藉由液體供給進行對鍍敷液中之錫供給，故而 於該鍍敷技術中電氣鍍敷裝置之運轉率（鍍敷處理數）亦下 降。 [發明之效果] 藉由本申請案揭示之發明中代表性者獲得之效果簡單說 明如下。 依據本發明，可提高電氣鍍敷裝置之運轉率（鍍敷處理數 增加）》 依據本發明，可降低半導體裝置之成本。 依據本發明’可提高半導體裝置之安裝可靠性。 【實施方式】 以下，參照圖式詳細說明本發明之實施形態。再者，於 用以說明發明之實施形態之所有圖中，具有同一功能者附 96953.doc 1359214 以相同符號，並省略其重複說明。 本實施形態中，關於QFN型半導體裝置之製造中適用本 發明之例加以說明。 圖1至圖15係關於本發明之一實施形態之圖， 圖1係表示半導體裝置之外觀構造之模式性平面圖， 圖2係表示半導體裝置之内部構造之圖（(a)係模式性平面 圖’（b)係模式性剖面圖）， 圖3係圖2(b)之一部分放大之模式性剖面圖， 圖4係使用於半導體裝置之製造之引線框之模式性平面 圖， 圖5係圖4之一部分放大之模式性平面圖， 圖6係表示半導體裝置之製造步驟之圖（⑷係表示線框 之產品形成區域之模式性剖面圖，（b)係表示晶片黏接步驟 之模式性剖©圖’⑷係表示線黏接步驟之模式性剖面圖）， 圖7係接續圖6表示之半導體裝置之製造步驟之圖（⑷係 表示模造步驟之模式性剖面圖，（b)係表示鍵敷步驟之模式 性剖面圖）， 圖8係表示半導體裝置之製造中模造步驟後之狀態的引 線框之模式性主要部分底面圖， 圖9係表示半導體裝晋之制蚀田+ π粗衣直之裏以宁使用之電氣鍍敷裝置之 概略構成的方塊圖， 圖1〇係表示圖9之鍍敷裝置中鍍敷處理部之概略構成之 模式性平面圖， 圖11係表示圖9之電氣鐘敷裝置中使用之錄敷液之化學 96953.doc 1359214 式之圖， 圖12係圖10之一部分放大之模式性平面圖， 圖】3係表示圖9之鍍敷裝置令鍍敷處理部之概略構成之 模式性剖面圖， 圖14係圖9之鑛敷裝f中使用之金屬製盒子之模式性立 體圖， 圖15係圖14之金屬製盒子之模式性剖面圖。 本實施形態之半導體裝置i係如圖2⑷及（b)所示，為包含 以下部分之封裝構造：半導體晶片2，複數根引線4，晶片 支撐體（模墊，側翼，晶片搭載部）5,4根吊引線53,複數根 黏接線7以及樹脂密封體8等。半導體晶片2，複數根引線*， 晶片支撐體5 ’ 4根吊引線53以及複數根黏接線7等藉由樹脂 密封體8予以密封。半導體晶片2介以黏接材料6黏接固定於 bb片支撐體5之主面（上面）’ 4根吊引線5a一體性連結於晶片 支撐體5。 半導體晶片2之與其厚度方向交又之平面形狀為方形 狀，本實施形態中為例如正方形。半導體晶片2並非限定於 此，例如為包含以下部分之構成：半導體基板，形成於該 半導體基板之主面上之複數個電晶體元件，於上述半導體 基板之主面上分別重疊複數段絕緣層、佈線層之多層佈線 層，以及以覆蓋該多層佈線層之方式形成之表面保護膜（最 終保護膜）等。 半導體晶片2具肴相互位於相反側之主面（電路形成面）及 背面，於半導體晶片2之主面側構成積體電路。積體電路主 96953.doc 11 1359214 要藉由形成於半導體基板主面上之電晶體元件以及形成於 多層佈線層上之佈線所構成。 於半導體晶片2之主面，形成有複數個黏接墊（電極）3。複 數個黏接塾3沿著半導體晶片2之各邊配置。複數個黏接塾3 开v成於半導體晶片2之多層佈線層中最上層之佈線層上，並 藉由黏接開口得以露出，該黏接開口相應於各黏接墊3形成 於半導體晶片2之表面保護臈上。 樹脂密封體8如圖1及圖2所示，其與厚度方向交又之平面 Z狀為方形狀，纟實施形態中例如為正方形。樹脂密封體8 含有相互位於相反侧之主面（上面）8χ及背面（下面，安裝 面）8y，樹脂密封體8之平面尺寸（外形尺寸）大於半導體晶片 2之平面尺寸（外形尺寸）。 作為實現低應力化之目的，樹脂密封體8例如以添加㈣ 系硬化劑’妙氧橡膠及填充劑等之聯苯系之熱硬化性樹脂 所形成。作為樹脂密封體8之形成方法，使用有適宜於大量 生產之轉移模造法。轉移模造法係使用包含㈣，繞道， 樹脂注入口，以及模穴等之成形模具（料模具），自壺罐通 過洗道及樹脂注入口將熱硬化性樹脂注入於模穴之内部並 形成樹脂密封體之方法。 於樹脂密封型半導體裝置之製造中，採用個別方式之轉 移模造法，其使用含有複數個產品形成區域之引線框，以 各產品形成區域為單位樹脂密封搭載於各產品形成區域之 半導體晶片，或者匯總方式之轉移模造法，其使用含有複 數個產品形成區域之引線框，1樹脂密封搭載於各產品 96953.doc •12- 1359214 形成區域之半導體晶片。本實施形態之半導體裝置1之製造 中’例如採用有個別方式之轉移模造法。 複數根引缘4如圖2(a)及（b)所示，沿著樹脂密封體8之4邊 配置。又’複數根引線4自樹脂密封體8之側面側朝半導體 晶片2延伸。 半導體晶片2之複數個黏接墊3分別電性連接於複數根引 線4。本實施形態1中’半導體晶片2之黏接墊3與引線4之電 性連接藉由黏接線7進行，黏接線7之一端部連接於半導體 晶片2之黏接墊3，黏接線7之與一端部相反側之他端部於半 導體晶片2之外側（周圍）連接於引線4。作為黏接線7例如使 用有金（Au)綠。又，作為黏接線7之連接方法，例如使用有 熱壓接與超聲波振動併用之釘頭黏接（球黏接）法。 複數根引線4含有相互位於相反側之主面及背面，複數根 引線4之各背面自樹脂密封體7之背面露出。本實施形態之 QFN型半導體裝置1將引線4之背面作為外部連接用端子部 使用。 於引線4之背面，如圖3所示，形成有合金鍍敷（焊錫鍍敷） 層9。該焊錫鍍敷層9以確保焊接安裝半導體裝置於佈線基 板時之焊錫可濕性為目的而形成。於本實施形態中，作為 焊錫鍍敷層9例如使用有98「重量％」Sn-2「重量％」Bi組 成之合金鍍敫層。後面將詳細說明，該Sn-Bi合金鍍敷層藉 由電氣链敷法形成《電氣鍍敷法係藉由電場反應自鍍敷液 (金屬鹽溶液）電解析出金屬於被鍍敷處理物（導電體表面） 上並形成合金鍍敷層之方法。 96953.doc 13 1359214 繼而，關於半導體裝置丨之製造中使用之引線框使用圖4 及圖5加以說明。 如圖4及圖5所示，引線框LF例如為行列狀配置複數個產 品形成區域（裝置形成區域）11之多連構造，該產品形成區域 藉由包含外框部及内框部之框主體（支撐體）1〇得以劃分。於; 各產βσ形成Q域11配置有複數根引線4，一個晶片支撐體5 以及4根吊引線5a等。晶片支撐體5配置於產品形成區域u 之中央部’介以4根吊引線5a與框主體1〇一體性形成。複數 根引線4分為4個引線群而配置，各引線群之引線4與框主體 1〇—體性形成。 引線框LF藉由於例如包含鐵^十鎳…丨）系之合金或銅 (Cu)或者Cu系之合金之平板材料（金屬板）施行蝕刻加工或 者衝壓加工並形成特定之引線圖案之處理而形成。本實施 形態之引線框LF如圖6(a)所示，於其厚度方向偏移引線4與 晶片支撐體5之高度。該偏移藉由於吊引線5&施行彎曲加工 而進行。 繼而，關於半導體裝置1之製造，使用圖6及圖7加以說明。 首先，準備如圖4、圖5及圖6(a)所示之引線框LF，其後 如圖6(b)所示，介以黏接材料6將半導體晶片2黏接固定於各 產品形成區域11之晶片支撐體5。半導體晶片2之黏接固定 係以半導體晶片2之背面與晶片支撐體5相向之狀態下進 行。 繼而，於各產品形成區域11如圖6(C)所示，以複數根黏接 線7分別電性連接半導體晶片2之複數個黏接墊3與複數根 96953.doc -14· 1359214 引線4。 繼而於各產品形成區域11如圖7(a)所示，樹脂密封半導體 晶片2，複數根引線4，晶片支撐體5，4根吊引線5a以及複 數根黏接線7等形成樹脂密封體8。本實施形態中，樹脂密 封體8之形成藉由個別方式之轉移模造法進行，該方法以各 產品形成區域為單位以樹脂密封搭載於各產品形成區域i i 之半導體晶片。 繼而，如圖7(b)所示，於引線4之背面（外部連接用端子部） 作為合金鍍敫層9例如形成98「重量％」Sn-2「重量％」Bi 組成之合金鍍敷層。後面將詳細說明，該Sn_Bi合金鍍敷層 藉由電氣鍍敷法形成。 繼而，藉由切斷自框主體10分離引線4及吊引線5a。藉 此’大致完成如圖1及圖2所示之半導體裝置1。 繼而’關於半導體裝置丨之製造製程中之鍍敷步驟，使用 圖8至圖1 5加以詳細說明。 鍍敷步驟中’使用圖9所示之電氣鍍敷裝置2〇。電氣鍍敷 裝置20並非限定於此，包含載置部21，前處理部22，鍍敷 處理部23，後處理部24，乾燥處理部25，卸載部26等。載 置部21供給引線框LF至前處理部22。於前處理部22，例如 使用鹼系之處理液，進行去除附著於引線框]11?之油性分子 等髒污之脫脂處理，例如使用氫氟酸（HF)，過氧化氫阳2〇2) 等之處理液，蝕刻引線框LF之表面進行提高合金鍍敷層（導 電性被膜）之黏接性的表面活性化處理等。於鍍敷處理部 23，於引線框之表面形成合金鍍敷層。於後處理部μ，使 96953.doc 15 1359214 用鹼系之處理液，進行申和形成於前段之鍍敷處理部23之 合金鍍敷層的中和處理，沖洗前段之處理液的洗淨處理 等》於乾燥處理部25，進行蒸發附著於引線框！^之水分等 之處理。卸載部26收容前段乾燦處理部25中經處理之引線 框LF。 於鍍敷處理部23，如圖1〇所示配置鍍敷槽3〇，於該鍍敷 槽30中裝入鍍敷液31。作為鍍敷液31，使用包含錫及鉍， 進而包含例如圖11所示之有機磺酸溶液之鍍敷液。錫及鉍 例如大概以98(錫）對2(叙）之比例含於錢敷液3丨中。 如圖10至圖12所示，於鍍敷液31中配置固體錫金屬37及 固體鉍金屬38，固體錫金屬37及固體鉍金屬38連接於電源 32之陽極，作為被鍍敷處理物之引線框][^連接於電源u之 陰極。引線框LF浸泡於鍍敷液31中，於鍍敷液31中沿著搬 運方向R搬運。引線框LF之搬運中，藉由電場反應使鍍敷 液31中之Sn及鉍電解析出於包含引線4之外部連接用端子 部之引線框LF之表面，形成大概98「重量％」Sn_2「重量 %」Bi組成之合金錄敷層9。 鍍敷液31中之錫及鉍之濃度對應於鍍敷處理之操作次數 而減少，故而需要於鍍敷液31中供給錫及鉍。鍍敷液31中 錫之供給藉由於鍍敷液31中電解溶出固體錫金屬”之處理 進行。又，鍍敷液31中鉍之供給藉由於鍍敷液31中電解溶 出固體祕金屬38之處理進行。 以此方式將配置於鍍敷液31中之固體錫金屬37及固體鉍 金屬38連接於陽極，將引線框^連接於陰極而形成合金錢 96953.doc -16- 1359214 敷層9,藉此鍍敷液31中之錫供給藉由於鍍敷液31中電解溶 出固體錫金屬37之處理進行，鍍敷液^中之鉍供給藉由於 鍍敷液31中電解溶出固體紐金屬38之處理進行，故而無需 停止鍍敷裝置30,可補充因鍍敷處理之操作造成之錫及鉍 之減少部分。其結果，與以溶液供給錫及鉍至鍍敷液中之 情形相比’不需要溶液之補充時間，故而可提高電氣鍵敷 裝置之運轉率（鍵敷處理數增加）。又，因可提高電氣鍍敷裝 置之運轉率（鑑敷處理數增加）’故而可降低半導體裝置之製 造成本。 又，時常以一定比例於鍍敷液31中電解溶出錫及鉍，故 而可抑制鍵敷液3 1中之錫及叙濃度經時變化之濃度不穩 定。其結果’可抑制生成之Sn-Bi合金鍍敷層之組成比之不 均一，故而可提高半導體裝置之安裝可靠性。 固體錫金屬37及固體叙金屬38於收容於金屬製盒子33之 狀態下配置於鍍敷液31中。金屬製盒子33連接於電源32之 陽極。金屬製盒子33如圖14所示，於鑛敷液31中為了更容 易地投入固體錫金屬37及固體鉍金屬38而敞開其上面， 又’為使鑛敷液31比較容易浸入盒子内而使前面以網36構 成。即，金屬盒子33之構造為：即使電氣錄敷裝置正在運 轉中，亦可將固體錫金屬37及固體鉍金屬38投入於鐘敷液 31中。 金屬製盒子33之内部藉由遮蔽板35劃分為兩個收容部 (34a、34b)。於收容部3 4a投入固體錫金屬37，於收容部34b 投入固體叙金屬38。遮蔽板35如圖15所示，以防止自固體 96953.doc 17 鉍金屬38電解溶出於鍍敷液31中之鉍置換析出於固體錫金 屬為目的換§之，以防止電解溶出之叙於鍵敷液31中 垂直於電場之方向移動為㈣，更進一步換言之，以防止 金屬製A子33中’電解溶出之鉍移動至固體錫金屬37為目 的而配置於金屬造盒子33中。 如圖10及圖13所示’金屬製盒子33以與引線框LF保持特 疋之間隔並夾著引線框LF之方式，分別配置於引線框LF之 搬運路徑之兩肋。以此方式於引線框LF之搬運路徑之兩侧 分別配置收容有固體錫金屬37及固體鉍金屬38之金屬製盒 子33’藉此可抑制於包含引線4之外部連接用端子部之引線 框LF之表面因電解析出而生成之Sn_Bi合金層9之不穩定。 鑛敷步驟如圖8所示，藉由於鍍敷液31中搬運經施加模造 步驟之引線愜LF而進行。引線框LF為於一方向配置複數個 產品形成區域11之多連構造，故而平面為長方形。該引線 框LF於鍍敷液3 1中以引線框LF之長度方向沿著搬運方向R 之方式搬送。因此，為進一步抑制Sn-Bi合金層9之不穩定， 如圖10及圖11所示，較好是沿著引線框LF之搬運方向R配置 固體錫金屬3 7及固體鉍金屬38。於本實施形態中，配置於 引線框搬運路徑之一側之固體錫金屬37及固體鉍金屬38， 與配置於引線框搬運路徑之另一側之固體錫金屬37及固體 鉍金屬38以爽著引線框搬運路徑並相互相向之方式配置。 固體錫金屬37及固體鉍金屬38如圖12及圖13所示，為複 數個粒狀固體金屬。如此將固體錫金屬37及固體鉍金屬38 設為複數個粒狀固體金屬’藉此增加鍍敷液31與固體錫金 96953.doc • 18· 1359214 屬37及固體鉍金屬38之接觸面積，故而可穩定進行錫及鉍 之電解溶出，可抑制Sn-Bi合金鍍敷層9之不穩定。 再者’雖未詳細地圖示’但固體錫金屬3 7之複數個粒狀 固體金屬係球形狀，固體鉍金屬38之複數個粒狀固體金屬 係圓柱狀。由於球形狀及圓柱狀時表面積變大，故而與鍍 敷液31之接觸面積增加。 圖16係表示本實施形態之第1變形例之圖（鍍敷處理部之 模式性平面圖）。 上述實施形態中，關於將配置於引線框搬運路徑之一側 之固體錫金屬37及固體鉍金屬38，與配置於引線框搬運路 徑之另一側之固體錫金屬37及固體鉍金屬38以夾著引線框 搬運路徑並相互相向之方式配置之例加以說明，如圖16所 示亦可以下述方式沿著引線框搬運方向交錯配置固體錫 金屬37與固體鉍金屬38 : 一側之固體錫金屬37與另一側之 固體祕金屬38相向，-側之固體叙金屬㈣另一側之固體 錫金屬37相向。此情形時，可進一步抑制Sn-Bi合金層9之 不穩定。 圖17係表示本實施形態之第2變形例之圖（鑛敷處理部之 模式性平面圖）》 上述實施形態中，就於金屬製盒子33中，各設置-個收 合固體錫金屬37之收容部34a與收容固體祕金屬％之收容 4 34b之例加以說明’如圖17所示，亦可設置複數個收容部 34a及收容部34be此情形時，如圖17所示，較好是沿著引 線框之搬運方向交錯配置固體踢金㈣及固㈣金屬以。 96953.doc 1359214 圖丨8係表示本實施形態之第3變形例之圖（鍍敷處理部之 模式性平面圖）。 上述實施形態中’就於一個金屬製盒子中以遮蔽板35為 界’收容固體錫金屬37與固體鉍金屬38之例加以說明，如 圖18所示’亦可將固體錫金屬37與固體鉍金屬38分別收容 於不同之金屬製盒子内。此情形時，金屬製盒子33之側面 發揮作為遮蔽板之功能。 圖19係表示本實施形態之第4變形例之圖（鍵敷處理部之 模式性平面圖）。 上述實施形態中，關於將固體錫金屬37與固體鉍金屬38 連接於同一陽極之一電源方式加以說明，如圖19所示，亦 可以雙電源方式形成Sn_Bi合金鍍敷層9，該電源方式將固 體錫金屬37連接於供給第1電位之第i陽極，將固體鉍金屬 38連接於供給高於第}電位之第2電位的第2陽極。固體鉍金 屬38之比電阻值高於固體錫金屬37，故而藉由以此雙電源 方式進行，可進一步抑制Sn_Bi合金鍍敷層9之不穩定。 再者，上述實施形態中，關於作為鍍敷液31使用包含錫 及鉍且進而包含有機磺酸溶液之鍍敷液之例加以說明，本 發明亦可適用於制包含錫及M且進而包含無機硫酸溶液 之鑛敷液之情形。 以上，基於上述實施形態具體地說明本發明者之發明， 本發明並非限定於上述實施形態者，#然於不脫離其主旨 之範圍内可實現各種變更。 例如’上述實施形態中關於QFN型半導體裝置之製造中 96953.doc •20- 1359214 適用本發明之例加以說明，但本發明可適用於於引線之外 連接用端子部形成Sn-Bi合金鐘敷層之半導體裝置之製 造。 【圖式簡單說明】 圖1係表示作為本發明之一實施形態之半導體裝置之外 觀構造的模式性平面圖。 圖2係表示作為本發明之一實施形態之半導體裝置之内 部構造的圖（（a)係模式性平面圖，（b)係模式性剖面圖卜 圖3係圖2(a)之一部分放大之模式性剖面圖。 圖4係作為本發明之實施形態1之半導體裝置之製造中使 用的引線框之模式性平面圖。 圖5係圖4之一部分放大之模式性平面圖。 圖6係表示作為本發明之一實施形態之半導體裝置之製 造步驟的圖（(a)係表示引線框之產品形成區域之模式性剖 面圖’（b)係表示晶月黏接步驟之模式性剖面圖，係表示 線黏接步驟之模式性剖面圖）。 圖7係接續圖6表示半導體裝置之製造步驟之圖（(a)係表 示成形步驟之模式性剖面圖，（b)係表线敷步驟之模式性 剖面圖）。 圖8係表示作為本發明之實施形態丨之半導體裝置之製造 中模造步驟後之狀態的引線框之模式性主要部分底面圖。 圖9係表示作為本發明之一實施形態之半導體裝置之製 造中使用的電氣鍍敷裝置之概略構成的方塊圖。 圖係表示圖9之鑛敷裝f中鑛敷處理部之概略構成之 96953.doc 21 1359214 模式性平面圖。 圖11係表示圖9之電氣鍍敷裝置中使用之鍍敷液之化學 式之圖。 圖12係圖10之一部分放大之模式性平面圖。 圖丨3係表示圖9之鍵敷裝置中鑛敷處理部之概略構成之 模式性剖面圖。 圖14係圖9之鍍敷裝置中使用之金屬製盒子之模式性立 體圖。 圖15係圖14之金屬製盒子之模式性剖面圖。 圖16係作為本發明之一實施形態之第1變形例之鍍敷處 理部的模式性平面圖。 圖17係作為本發明之一實施形態之第2變形例之鍍敷處 理部的模式性平面圖。 圖18係作為本發明之一實施形態之第3變形例之鍍敷處 理部的模式性平面圈。 圖19係作為本發明之一實施形態之第4變形例之鍍敷處 理部的模式性平面圖。 【主要元件符號說明】 1 半導體裝置 2 半導體晶片 3 黏接墊 4 引線 5 晶片支撐體 5a 吊引線 96953.doc -22- 1359214 6 黏接材料 7 黏接線 8 樹脂密封體 9 合金鍍敷層 LF 引線框 10 框主體 11 產品形成區域 20 電氣鍍敷裝置 21 載置部 22 前處理部 23 鍍敷處理部 24 後處理部 25 乾燥處理部 26 卸載部 30 液槽 31 鍍敷液（金屬鹽溶液） 32 電源 33 金屬製盒子 34a ， 34b 收容部 35 遮蔽板 36 網 37 固體錫金屬 38 固體鉍金屬 96953.doc -23,

Claims (1)

1359214 第093132441號專利申請案 中文申請專利範圍替換本(1〇〇年8月） …年#幵修正替換頁 十、申請專利範圍： 1. 一種電氣鍍敷方法’其包括以下步驟： (a) 準備一鍍敷裝置，該鍍敷裝置包含：鍍敷槽；鍍敷 液，其收容於該鍵敷槽中並含有錫及叙；金屬盒，其具 有第1收容隔間及與該第1收容隔間相鄰之第2收容隔 間；遮蔽板，其配置於該第1收容隔間與該第2收容隔間 之間；第1開口，其形成於該金屬盒子的該第丨隔間頂部 並用於將固體錫金屬供至該第1收容隔間；及第2開口， 其形成於該金屬盒子的該第2隔間頂部並用於將固體鉍 金屬供至該第2收容隔間；其中該金屬盒子位於該鍍敷液 中，並連接至電源之陽極； (b) 透過上述第1開口將上述固體錫金屬置於上述第1 收容隔間，且透過上述第2開口將上述固體鉍金屬置於上 述第2收容隔間； (c) 將被鍍敷處理物連接於上述電源之陰極，並將該被 鍵敷處理物置於鍵敷液中； (d) 於步驟（c)後，啟動上述鍍敷裝置，於上述陽極與 上述陰極之間進行電解，於上述被鍍敷處理物上形成錫- 纽合金層。 2. 如請求項1之電氣鍍敷方法，其中上述鍍敷液包含有機磺 酸溶液。 3. 如請求項1之電氣鍍敷方法，其中上述鍍敷液包含無機硫 酸溶液。 4. 如請求項1之電氣鍍敷方法，其中上述固體錫金屬與上述 96953-1000831.doc 1359214 5. 6. 7. 8. 9. 10. 11. 12. - '：：~： 年J、戶修正替換頁I。。m___ 固體鉍金屬係分別由複數個粒狀固體金屬塊所製成。 如請求項4之電氣鍍敷方法，其中上述固體錫金屬之複數 個粒狀固體金屬塊為球形狀，上述固體鉍金屬之複數個 粒狀固體金屬塊為圓柱狀。 如請求項1之電氣鍍敷方法，其中上述陽極含有連接於第 1電位之第1陽極’以及連接於電位高於上述第1電位之第 2電位的第2陽極’且上述固體錫金屬連接於上述第1陽 極，上述固體鉍金屬連接於上述第2陽極。 如凊求項1之電氣鍍敷方法’其中上述鐘敷液中之上述錫 係藉由將上述固體錫金屬電解溶入上述鍵敷液而提供 者，上述鐘敷液中之上述叙係藉由將上述固體絲金屬電 解溶入上述鍍敷液而提供者。 如請求項1之電氣鍍敷方法，其中上述金屬盒子之與上述 被鍵敷處理物相對向之表面係含網。 如請求項1之電氣鍍敷方法，其中以上述被鍍敷處理物位 於上述複數個金屬盒子之間之方式配置上述複數個金屬 盒子β 如請求項8之電氣鐘敷方法，其中上述遮蔽板防止上述電 解溶出之祕由上述固體㈣屬移動至上述固體錫金屬。 如請求項1G之電氣鍍敷方法，其中上述複數個金屬盒子 中’金屬盒子係、彼此相向，使其中之固體絲金屬與固體 鉍金屬相向’且其中之固體錫金屬與固體錫金屬相向。 如請求項狀電_敷方法，其中上述複數個金屬盒子 中，金屬i：子係彼此相向，使其中之固體錢金屬與固體 96953-1000831.doc 1359214 年月日修 1〇〇 i / --— 錫金屬相向，且其中之固體錫金屬與固體鉍金屬相向。 13.如請求項1之電氣鍍敷方法，其中上述鍍敷槽係一含有上 述鍍敷液之單槽。 96953-1000831.doc
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JP2005163152A (ja) * 2003-12-05 2005-06-23 Renesas Technology Corp 電気メッキ方法及び半導体装置の製造方法
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CN102002742B (zh) * 2010-12-15 2012-05-30 安徽华东光电技术研究所 一种镀液配方及配制方法及在铝基板上电镀的方法
CN104157595B (zh) * 2014-07-10 2016-11-02 中南大学 基于电化学生长的微电子封装引线互连方法与装置
CN104313657A (zh) * 2014-11-10 2015-01-28 临安振有电子有限公司 Hdi印制线路板通孔的电沉积装置
EP3064617B1 (de) * 2015-03-03 2018-08-15 MTV Metallveredlung GmbH & Co. KG VERFAHREN ZUR VERNICKELUNG GROßFLÄCHIGER BAUTEILE
US10763195B2 (en) * 2018-03-23 2020-09-01 Stmicroelectronics S.R.L. Leadframe package using selectively pre-plated leadframe
CN110528042B (zh) * 2019-08-28 2021-02-09 深圳赛意法微电子有限公司 一种半导体器件电镀方法及用于电镀的活化槽

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1433800A (en) * 1973-12-27 1976-04-28 Imi Refinery Holdings Ltd Method of and anodes for use in electrowinning metals
US4288298A (en) * 1979-03-14 1981-09-08 Rogers Olbert W Method and apparatus for electroplating or electroforming metal objects
US4439284A (en) * 1980-06-17 1984-03-27 Rockwell International Corporation Composition control of electrodeposited nickel-cobalt alloys
JPH0765206B2 (ja) * 1988-09-22 1995-07-12 上村工業株式会社 ビスマス―錫合金電気めっき方法
US5039576A (en) * 1989-05-22 1991-08-13 Atochem North America, Inc. Electrodeposited eutectic tin-bismuth alloy on a conductive substrate
JP3274232B2 (ja) * 1993-06-01 2002-04-15 ディップソール株式会社 錫−ビスマス合金めっき浴及びそれを使用するめっき方法
JP3061986B2 (ja) 1993-08-31 2000-07-10 株式会社東芝 自動券売機
KR0145768B1 (ko) * 1994-08-16 1998-08-01 김광호 리드 프레임과 그를 이용한 반도체 패키지 제조방법
US6342146B1 (en) * 1995-07-14 2002-01-29 Geronimo Z. Velasquez Lead-free alloy plating method
US5744013A (en) * 1996-12-12 1998-04-28 Mitsubishi Semiconductor America, Inc. Anode basket for controlling plating thickness distribution
JP2000045099A (ja) * 1998-07-28 2000-02-15 Canon Inc 電析槽、および電析装置
JP2005163152A (ja) * 2003-12-05 2005-06-23 Renesas Technology Corp 電気メッキ方法及び半導体装置の製造方法

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US7323097B2 (en) 2008-01-29
US20080132005A1 (en) 2008-06-05
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TW200533792A (en) 2005-10-16

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