TWI344694B - Sensor-type package and method for fabricating the same - Google Patents

Sensor-type package and method for fabricating the same Download PDF

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TWI344694B
TWI344694B TW096128799A TW96128799A TWI344694B TW I344694 B TWI344694 B TW I344694B TW 096128799 A TW096128799 A TW 096128799A TW 96128799 A TW96128799 A TW 96128799A TW I344694 B TWI344694 B TW I344694B
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sensing
wafer
recess
semiconductor wafer
package structure
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TW200908311A (en
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Chang Yueh Chan
Chien Ping Huang
Tse Wen Chang
Chin Huang Chang
Chih Ming Huang
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Siliconware Precision Industries Co Ltd
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Priority to US12/221,725 priority patent/US20090039527A1/en
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    • H—ELECTRICITY
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    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
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    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
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    • H01L27/144—Devices controlled by radiation
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    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
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    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Description

九、發明說明： 【發明所屬之技術領域】 本發明係有關於―種半導體封裝件及其製法，尤指一 種感測式封裝結構及其製法。 【先前技術】 傳統影像感測式封裝件（Image Sensor package)，如姜 =專^6糊，34〇、6,262,479、及6,59()，269 號案所揭露 糸預先製備攔壩結構於晶片承載件上，再將感測晶片 、者及打線至該晶片承載件上所該攔壩結構所圍之空間， 並黏置—透光玻璃於攔壩結構上以封蓋住該空間。惟此感 測式封裝件X限於晶片承載件至少必須預留足夠之空間來 置放攔壩結構，同時該感測晶片亦須透過銲線電性連接至 =片承載件，使得該感測式職件的大小受咖壩結構及 、干春佈叹限制’無法進—步縮小，且電性品質亦無法提升。 請參閱第1 _，鑑於前述缺失，美國專利第6,995,462 揭不一種毋需使用攔壩結構，且毋需透過銲線電性連接感 測晶片與晶片承載件之感測式封褒件，其主要係提供一且 有相對主動面121及非主動㈣2之感測晶片12，該主動 面m設有感測區123及複數料124，且於該主動面⑵ 上間隔—膠黏層14而接置有透光蓋體15,並透過石夕通道 (Through SiIicon Via，TSV)技術於該感測晶片12中形成 金屬柱126,以使該感測晶片12主動面ΐ2ι之銲墊124透 過該金屬柱126而電性連接至該感測晶片12非主動面η】 之銲塊125,俾供該感測晶片12藉由該銲塊125而接置且 110425 5 1344694 - 電性連接至如基板之晶片承載件。 惟前述所製得之感測式封裝件，需將感測晶片電性連 接至晶片承載件，再藉由該晶片承载件而電性連接至外部 裝置，實屬封裝件級（package_level)之封裝結構，不僅體積 大且成本高；再者，前述之感測式封裝件中無法整合如數 位訊號處理（Digitalsignalprocessor，Dsp)控制單元，因此 該感測式封裝件實無法滿足業界要求之輕、薄、短、小， 且具高度整合性之感測式封裝結構。 • 另外，請參閱第2A至2F圖，美國專利US5,27〇,261 及5,202,754揭露一種利用矽通道（Ts v )技術以供複數半 導體晶片堆疊且相互電性連接而形成多晶片模組 (^Multi-chip Module ; MCM)之結構，其主要提供一具相對 第一表面211及第二表面212之第一晶圓2U，該第一晶 圓21a包含有複數第一晶片21，其中該第一表面211形成 有複數孔洞210，並於該孔洞21〇中形成金屬柱23，以構 籲成矽通道（tsv)結構，及於該金屬柱23外露端形成銲墊 231，以將該第一晶圓21a第一表面211透過膠黏層 而黏置於一如玻璃之載板251上，俾藉由該載板251提供 製釭所需之支撐強度（如第2 A圖所示）；利用研磨作業，對 該第一晶圓21a之第二表面212進行薄化，以外露出該金 屬柱23(如第2B圖所示）；於外露出該第二表面212之金 屬柱23上形成銲墊232，以供另一形成有矽通道之具複數 第二晶片22之第二晶圓223藉由其矽通道之金屬柱26垂 直接置並電性連接於該第一晶圓2ia之第二表面212上（如 6 110425 1344694 第2C圖所示）；接著重複前述製程，研磨薄化該具複數第 二晶片22之第二晶圓22a，以外露出該矽通道之金屬柱 26，及於該金屬柱26外露端形成銲墊236(如第圖所 示）’後續為供第一及第二晶片21，22與外部裝置電:連 接，需於該第一晶圓之苐一表面植設複數銲球，此時即需 再利用另一如玻璃之載板252以透過膠黏層242而將該^ —及第二晶圓21a，22a黏置其上，且外露出該第一晶圓21a 之第一表面211(如第2E圖所示）；俾於該第一晶圓第一表 面211之銲墊231上植設銲球27(如第2F圖所示）；接著切 J該堆唛之第一及第二晶圓2ia，22a，以形成複數個相互垂 直堆豐之第一及第二晶片21，22，再經拾取及透過銲球27 而電性連接至基板28,以形成多晶片模組化之半導體封裝 件（如第2G圖所示）。 然而於前述之製程中，須額外使用複數之載板 251，252，且將第一及第二晶圓21a，22a多次反覆黏置於載 鲁板251,252上，惟此不僅增加製程成本，亦造成製程複雜 性的提高，再者，若所使用之膠黏層241，242為例如環氧 樹脂（epoxy)之高分子材料時，於形成該銲墊231 236所進 行之濺鍍（sputtering)及後續之濕式蝕刻（stdp)作業，極易 造成.製程上之污染而致生產不易。 因此前述習知利用矽通道（Tsv )以供複數半導體晶 片堆疊且相互電性連接而形成多晶片模組（Muhi_chip
Module; MCM)之技術，亦無法有效整合應用至感測式封 裝結構中。 110425 7 乂如何開發一種晶圓級（wafer_level)之輕、薄、短、 型’且具高度整合性與低製程成本及複雜性之感測式封 裝結構及製法，實為目前亟欲解決的課題。 【發明内容】 鑒於以上所述先前技術之缺點，本發明之一目的在於 Z供種晶圓級（wafer-level)之輕、薄、短、小型感測式封 襞結構及其製法。 本發明之另一目的在於提供一種製程簡單及低成本之 感測式封裝結構及其製法。 、本發明之再一目的在於提供一種且具高度整合性之感 測式封裝結構及其製法。 〜 本發明之又一目的在於提供一種可整合控 測式封裝結構及其製法。 饮 本發明之又一目的在於提供一種避免因使用高分子膠 黏層而發生污染，或使用載板之感測式封裝結構及其製法= 為達上揭及其他目的，本發明揭露一種感測式封裝結 構之製法，係包括：提供包含有複數半導體晶片之晶圓， 該晶圓及半導體晶片具有相對之第—表面及第二表面，該 半導體晶片第-表面形成有複數孔洞，且於該孔洞處形^ 有金屬柱及銲墊，以構成矽通道（TSV)結構；於該半導體 晶片之第二表面形成凹槽，且令該矽通道之金屬柱顯露於 該凹槽底4 ;將形成有料道（TSV)之感測晶片堆疊於該 半導體晶片之凹槽中並電性連接至外露出該凹槽之 柱；以及於該半導體晶片第二表面上接置—封蓋該凹槽之 110425 8 1344694 . 透光蓋體。 另該製法復包括：於該半導體晶片第一表面之銲墊上 植設複數導電元件；以及沿各該半導體晶片間進行切割。 、 該感測晶片具有相對之主動面及非主動面，該主動面 設有感測區，並於該感測晶片中形成有矽通道（Tsv)結 構’該感測晶片係以其非主動面接置於該半導體晶片之凹 槽中，以令該感測區顯露於該凹槽，並使其矽通道電性連 接至外露出該凹槽之半導體晶片之矽通道金屬柱，其中該 籲凹槽之深度大於感測晶片之接置高度。 此外，於該凹槽中可填覆絕緣材料，以將感測晶片有 效固疋於該凹槽，惟未使該絕緣材料遮覆感測區；另於該 凹槽中復可接置被動元件，以強化整體結構電性品質。再 者，於該感測式封裝結構對應透光蓋體之一側亦可設置一 鏡片承座。 透過剛述製法’本發明復揭示一種感測式封裝結構， 籲係包括：半導體晶片，具有相對之第一表面及第二表面， 該第一表面形成有孔洞，且於該孔洞處形成有金屬柱及銲 墊以構成矽通道（TSV)結構，該第一表面形成有凹槽以外 露出該矽通道（TSV)之金屬柱；感測晶片，具有相對之主 動面及非主動面，該主動面設有感測區，並於該感測晶片 中形成有矽通道（TSV)結構，該感測晶片係以其非主動 面接置於該半導體晶片之凹槽中，並電性連接至外露出該 凹槽之半導體晶片之矽通道金屬柱，且使該感測區顯露於 該凹槽；以及透光蓋體，係接置於該半導體晶片第二表面 110425 9 1344694 上且封蓋該凹槽。 該多晶片堆疊結構復包括：絕緣材料，係填充於該半 導體晶片之凹槽中，惟未覆蓋至該感測晶片之感測區；被 動元件，係設於該凹槽中且電性連接至外露該凹槽之該半 導體晶片碎通道之金屬柱。
因此，本發明之感測式封裝結構及其製法，主要係提 供-具複數半導體晶片之晶圓，該半導體晶片第一表面形 成有複數孔洞，且於該孔洞處形成有金屬柱及鮮塾，以構 成石夕通道（TSV)結構，另於該半導體晶片之第二表面形成 有外露出該料道金屬柱之凹槽，以將形成有料道（TSV、 之感測晶堆疊於該半導體晶片之凹射並電性連接至外 _凹槽之金屬纟’再於該半導體晶片第二表面上接置 -封盍該凹槽之透光蓋體，之後復可於該半導體晶片第一 上植設複數導電元件’以及沿各該半導體晶片 間進订切割’如此即可透過前述晶圓級（wafeMevel)之繁 輕、薄、㉟、小之感測式封震結構，並使設有砂 號處理_)控制單元之半導體晶;:=:= =封同時本發明中藉由未經整二= ==圓作為製程進行中之承載架構，得以 接置於s Λ/ 結㈣直堆4複數q及將該些晶片 承載件上時須多次使用載板及膠黏層，所產生 成本高以及可能遭受污染等問題0 110425 10 1344694 以下係藉由特定的具體實施例說明本創作之實施方 式’所屬技術領域中具有通常知識者可由本說明蚩所揭示 之内容輕易地瞭解本創作之其他優點與功效。 第一實施你丨 請參閱第3A至3F圖，係為本發明之感測式封裴結構 及其製法第一實施例之示意圖。 如第3A圖所示，提供一包含有複數例如數位訊號處 理（Digital signal processor, DSP)之半導體晶片3ι的晶圓 31a,該晶圓31a及各該半導體晶片31具有相對之第一表 面311及第二表面312’其中該半導體晶片31第一表面η〕 形成有複數孔洞310，以對應該孔洞31〇處形成金屬柱％ 及銲墊331 ’而構成矽通道（TSV)結構。 斤該矽通道之孔洞310與金屬柱33間係設有如二氧化矽 或氮化矽之絕緣層33”，且該絕緣層33”與金屬柱Μ間係 春2有如鎳之阻障層33,，而該金屬柱33之材質係例如為 鋼、金、铭等。 如第3B圖所示，對該半導體晶片31之第二表面η 利用如深層蝕刻（Deep Reactive Ion Etching，〇111£)之方5
=刻形成至少—凹槽迎，且令㈣通道之金屬柱33 I ^於該凹槽312G底部’其中該金屬柱33係可凸出於該c 槽3!20底部。 如第3C圖所示，將感測晶片32堆疊於該半導體晶片 且各置於相槽3 12G中，並電性連接至外露出該凹 110425 11 31 1344694 槽3120之矽通道之金屬柱33。 該感測晶片32具有相對之主動面321及非主動面 322，該主動面321設有感測區323及銲墊η#，該非主動 '-面322設有導電凸塊325,且該感測晶# 32中形成有電性 連接銲塾324及導電凸塊325之金屬柱326，以 道（TSV)結構。 、 該感測晶片32係以其非主動面322接置於該半導體晶 片31之凹槽3120中，並使其導電凸塊325電性連接至= 攀露出該凹槽3U0之半導體晶片石夕通道之金屬柱33，且使 該感測區323顯露於該凹槽3120,其中該凹槽312〇之深 度大於感測晶片32之接置高度。 如第3D圖所示，於該半導體晶片31第二表面3丨^上 接置一封蓋該凹槽3120之透光蓋體35,該透光蓋體35例 如為玻璃。 如第3E及3F圖所示，後續復可於該半導體晶片3 j 籲第一表面311之銲墊331上植設複數導電元件37，以及沿 各該半導體晶片31間進行切割，藉以形成複數感測式封^ 結構單體。 透過前述製法，本發明復揭示一種感測式封裝結構， 係包括：半導體晶片31，具有相對之第一表面3ιι及第二 表面312，該第一表面311形成有孔洞31〇，且於該孔洞 310處形成有金屬柱33及銲墊331以構成矽通道（TSV)結 構’該第二表面312形成有凹槽312〇以外露出該矽通道 (TSV)之金屬柱33 ;感測晶片32，具有相對之主動面321 110425 12 1344694 及非主動面322，兮士 & _ ^ 这主動面321設有感測區323,並於該感 Z片32中形成切通道（tsv)結構，該感測晶片係以 二非主動面322接置於該半導體晶片31之凹槽化"並 =連接至外露出該凹槽迎之半導體晶片Μ之石夕通道 水从柱33且使該感測區323顯露於該凹槽犯〇;以及透 =體35，係置於該半導體晶片31第二表面312上且封 盖該凹槽3120。 因此，本發明之感測式封裝結構及其製法，主要係提 數半導體晶片之晶圓，該半導體晶片第一表面形 ^㈣孔洞’且於該孔洞處形成有金屬柱及輝墊，以構 =，（TSV)結構’另於該半導體晶片之第二表面形成 ^ ^出該料道金屬柱之凹槽，以將 =晶二堆疊於該半導體晶片之凹槽中並() 路=凹槽之金屬柱，再於該半導體晶片第二表面 :封盖該凹槽之透光蓋體，之後復可於該半導體晶片第一 表面之銲墊上植設複數導雷 間進行切割，如此即可透過前述曰圓該半導體晶片 程，提供輕'薄'短'小之感測二(:aT 诵、音—— 、町裝結構，並使設有矽 ^道之感測晶片堆疊及電性連接至設切通道之 旒處理（DSP)控制單元之半導體曰 1 之感測式封裝結構；同時本發明中=供具向度整合性 福齡主道μ 〜月中稭由未經整體薄化之具 避免片為製程進行中之承載架構， 接置於晶片承載件上時須多次使用載板及膠黏層 110425 13 1J440V4 .的衣程繁雜、成本高以及可能遭受污染等問題。 第二實施铷j 清參閱第4目’係為本發明之感 法第二實施例之示意圖。同時為簡化本圖示本t二巧 對應前述相同或相似之元件係採用相同標號表=把例t 本實施例之感測式封裝結構及其製法與前 致相同，主要差異在於對庫日 、匕例大 第二表面扣之各半導體晶片” 、 θ 中填覆有、《巴緣材料3 4，c/ =»·、 測晶片32有效固定於該凹槽312〇，惟未 ^ 遮覆感測晶片32之感測區323。 …巴緣材料34 I三實施例 ::閱第5圖’係為本發明之感測式封震結 示意圖。同時為簡化本圖示，本實施^ 對應=相同或相似之元件係採用相同標號表示。 致相及其製法與前述實施例大 封===性連接錢動元件⑽強化感測式 110425 1344694 對應前述相同或相似之元件係採用相同標號表示。 本實施例之感測式封裝結構及其製法與前述實施例大 致相同，主要差異在於半導體晶片31對應透光蓋體35之 一側設置一鏡片承座39，以加強光線接收效能。 以上所述之具體實施例，僅係用以例釋本發明之特點 及功效，而㈣⑽定本發明之可實施料，在未脫離本 ，月上揭之精神與技術_下，任何運用本發明所揭示内 谷而完成之等效改變及修飾，均仍應為下述之申請專 圍所涵蓋。 & 【圖式簡單說明】 第1圖係為習知美國專利第6,995,462所揭示之感 式封裝件； 第2A至2G圖係為習知美國專利US5,27〇,261及 5,202,754所揭露之藉㈣通道（TSV)技術垂直堆疊複數 半導體晶片之示意圖； 第3 A至3F圖係為本發明之感測式封裝結構及其製法 第一實施例之示意圖； 第4圖係為本發明之感測式封裝結構及其製法第二實 施例之示意圖； 第5圖係為本發明之感測式封裝結構及其製法第三實 施例之示意圖；以及 第6圖係為本發明之感測式封裝結構及其製法第四實 施例之示意圖。 、 【主要元件符號說明】 110425 15 1344694
12 感測晶片 121 主動面 122 非主動面 123 感測區 124 銲墊 125 銲塊 126 金屬柱 14 膠黏層 15 透光蓋體 21 第一晶片 211 第一表面 212 第二表面 210 孔洞 22 第二晶片 23,26 金屬柱 231,232,236 銲墊 241,242 膠黏層 251,252 載板 27 鲜球 28 基板 31 半導體晶片 31a 晶圓 310 孔洞 311 第一表面 312 第二表面 3120 凹槽 32 感測晶片 321 主動面 322 非主動面 323 感測區 324 銲墊 325 導電凸塊 326 金屬柱 33 金屬柱 33， 阻障層 33，， 絕緣層 331 銲墊 34 絕緣材料 35 透光蓋體 37 導電元件 38 被動元件 39 鏡片承座 16 110425

Claims (1)

1344694 十、申請專利範圍： 1. 一種感測式封裳結構之製法，係包括： 曰提供包含有複數半導體晶片之晶圓，該晶圓及半導 體曰曰片具有相對之第一表面及第二表面，該半導體晶片 第：表面形成有複數孔洞，且於該孔洞處形成有金屬柱 及銲墊，以構成矽通道（TSV)結構； 、、於該半導體晶片之第二表面形成凹槽，且令該矽通 道之金屬柱顯露於該凹槽底部； 曰將形成有矽通道（TSV)之感測晶片堆疊於該半導體 晶片之凹槽中且電性連接至外露出該凹槽之金屬柱；以 及 於該半導體晶片第二表面上接置一封蓋該凹槽之 透光蓋體。 2.如申請專利範圍第丨項之感測式封裳結構之製法，其 中該孔，同與金屬柱間復設有絕緣層，該絕緣層與金屬 柱間復設有阻障層。 〃 如申明專利|巳圍第2項之感測式封裝結構之製法，其 中，該絕緣層為二氧切及氮切之其中—者，該阻障 層為鎳，該金屬柱之材質為銅、金、紹所組群組之一者。 4.如申請專利範圍第丨項之感測式封裝結構之製法，其 中，該凹槽係藉由深層蝕刻方式形成。 如申請專利範圍第！項之感測式封裝結構之製法，其 中’該感測晶片具有相對之主動面及非主動面，該主動 ㈣有感測區及銲塾’該非主動面設有導電凸塊，且該 110425 17 1344694 • 感測晶片中形成有電性連接銲墊及導電凸塊之金屬 柱，以構成矽通道（TSV)結構。 • 6.如申請專利範圍第1項之感測式封裴結構之製法，其 中，該凹槽之深度大於感測晶片之接置高产。 、 7. 如申請專利範圍第丨項之感測式封裝結構2製法， 括： ° 於該半導體晶片第一表面之銲墊上植設複數 元件；以及 沿各該半導體晶片間進行切割，藉以形成複數感測 式封裝結構單體。 " 8. 如申請專利範圍第丨項之感測式封裝結構之製法，其 中，該凹槽中填覆有、絕緣材料，且該絕緣材料未遮覆該 感測晶片之感測區。 9. 如申請專利範圍帛丨帛之感測式封裝結構之製法，其 中，該凹槽中復接置及電性連接有被動元件。 • ι〇.如申請專利範圍第1項之感測式封裝結構之製法，其 中，該半導體晶片對應透光蓋體之一侧設置有一鏡片^ 座。 11·一種感測式封裝結構，係包括： 半導體晶片，具有相對之第一表面及第二表面，該 第一表面形成有複數孔洞，且於該孔洞處形成有金屬柱 及銲墊以構成矽通道（TSV)結構，該第二表面形成有凹 槽以外露出該矽通道（TSV)之金屬柱； 感測晶片，具有相對之主動面及非主動面，該主動 110425 18 1344694 面"又有感測區，並於該感測晶片中形成有石夕通道（tsv ) 結構，該感測晶片係以其非主動面接置於該半導體晶片 之凹槽中並電性連接至外露出該凹槽之半導體晶片之 矽通道金屬柱，且使該感測區顯露於該凹槽；以及 透光蓋體，係置於該半導體晶片第二表面上且封蓋 該凹槽。 1 12.如申請專利範圍第11項之感測式封裝結構，其中，該 孔洞與金屬柱时設有絕緣層，朗緣層與金屬柱間復 設有阻障層。 以如申請專利範圍第12項之感測式封裝結構，其中，該 絕緣層為二氧化石夕及說化石夕之其中一者，該阻障層為 鎳，該金屬柱之材質為銅、金、鋁所組群組之一者。 14. 如申請專利範圍第η項之感測式封裝結構，其中，該 凹槽係藉由深層蝕刻方式形成。 μ 15. 如申請專利範圍第U項之感測式封裝結構，其中，該 感測晶片主動面設有感測區及銲墊，非主動面設有導； 凸塊’且該感測晶片中形成有電性連接銲墊及導電凸塊 之金屬柱，以構成矽通道（TSV)結構。 16·如申請專利範圍第u項之感測式封裝結構，其中 凹槽之深度大於感測晶片之接置高度。 =申請專利範㈣η項之感測式封I結構，復包 ¥電π件’係植設於該半導體晶片第—表面之鲜 1如申請專利範圍第㈣之感測式封裝結構，1中，^ 凹槽中填覆有絕緣材料，且該絕緣材料未遮覆該感^ 110425 19 1344694 片之感測區。 19. 如申請專利範圍第11項之感測式封裝結構，其中，該 凹槽中復接置及電性連接有被動元件。 20. 如申請專利範圍第11項之感測式封裝結構，其中，該 半導體晶片對應透光蓋體之一側設置有一鏡片承座。
20 110425
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