TW201630152A - 元件嵌入式影像感測器及其晶圓級製造方法 - Google Patents

元件嵌入式影像感測器及其晶圓級製造方法 Download PDF

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TW201630152A
TW201630152A TW104137623A TW104137623A TW201630152A TW 201630152 A TW201630152 A TW 201630152A TW 104137623 A TW104137623 A TW 104137623A TW 104137623 A TW104137623 A TW 104137623A TW 201630152 A TW201630152 A TW 201630152A
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image sensor
conductive pad
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林蔚峰
黃吉志
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豪威科技股份有限公司
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Abstract

元件嵌入式影像感測器包括一影像感測器、一頂部導電墊及一半導體元件。該影像感測器係形成於一第一半導體基板中;該頂部導電墊係形成於該第一半導體基板之一上表面;該半導體元件係形成於一第二半導體基板中,該第二半導體基板係接合至該第一半導體基板之下表面,該半導體元件電性連接至該頂部導電墊。製造元件嵌入式影像感測器之方法,係以CMOS影像感測器晶圓組件為製造基底,該CMOS影像感測器晶圓組件包括一影像感測器及一導電墊。該方法包含:裸露該導電墊、形成隔離層、裸露各導電墊之表面、於隔離層上形成圖案化之重佈層、電性隔離相鄰之RDL元件以及堆疊CMOS影像感測器晶圓組件與半導體元件晶圓,以形成未晶粒切割之元件嵌入式影像感測器。

Description

元件嵌入式影像感測器及其晶圓級製造方法
本發明係關於影像感測器和特定應用積體電路(ASICs),更具體而言,係關於嵌入影像感測器下方的ASICs。
單機數位相機(stand-alone camera)、移動裝置、汽車元件和醫療裝置等產品內含之相機模組通常包含CMOS影像感測器,影像感測器係將照相機透鏡之成像光線轉換成數字信號,該數字信號再轉換成含有影像數據的顯示影像和/或檔案。一般而言,影像感測器係安裝於印刷電路板(PCB)表面上,PCB亦包含一ASIC,其與影像感測器協作並處理數據/影像。ASIC功能可包含影像處理、視訊處理和串流及高速數據傳輸。
第一圖係顯示習知相機模組PCB 102之平面圖,習知相機模組PCB102包含影像感測器124和ASIC晶片126。上述產品所含之相機模組PCB相似於PCB 102。第二圖係顯示第一圖相機模組PCB 102之2-2’剖面圖。於第一圖和第二圖中,導線(wire bond)134和導線136的陣列分別將影像感測器124和ASIC晶片126電性連接至相機模組PCB 102。為使圖式簡潔明確,第一圖所示之導線並非標記引線和標號,僅部分標記為導線134和導線136。
縮減相機模組尺寸並保有相機功能,有助於降低生產成本並提高產品實用性。然而,無論是縮減影像感測器或/及ASIC尺寸,都可能會限制影像感測器和ASIC之功能特性。美國專利號7,633,231已揭示一種縮減相機模組尺寸之技術,其乃藉由堆疊影像感測器晶粒和ASIC晶粒方法以達成之。
受限於習知堆疊晶粒影像感測器,晶圓級製程無法達成ASIC晶粒嵌入至晶圓上影像感測器上,反而是將個別ASIC晶粒施加至每一影像感測器。對於某些應用而言,這些堆疊式晶粒影像感測器具有另一限制:外部電性連接至影像感測器和ASIC會形成於共用平面上,而非影像感測器之平面,因而本 發明所揭示之堆疊晶粒影像感測器及其相關方法足以克服先前限制和缺點。
本發明係揭示一種元件嵌入式影像感測器,其包含一影像感測器、一導電墊及一半導體元件。該影像感測器係形成於一第一半導體基板上之一上表面,該導電墊係形成於該上表面上,該半導體元件係形成於一第二半導體基板上,該第二半導體基板接合至該第一半導體基板之一下表面,例如:該影像感測器下方,該半導體裝置係電性連接至該導電墊。
本發明揭示一種用於製造元件嵌入影像感測器之方法,其係以CMOS影像感測器晶圓組件為製造基底。該CMOS影像感測器晶圓組件包含一影像感測器及一導電墊,該影像感測器係形成於一半導體晶圓內,該導電墊具有一裸露面,其形成於半導體晶圓頂側。該方法包含:移除該半導體晶圓之至少一部分,以裸露該導電墊,以及,於已移除之部分上形成一隔離層。該方法更包含:移除隔離層與導電墊接觸之部分,以裸露該導電墊之一表面,並且於該隔離層上形成圖案化重佈層(RDL),其具有數個RDL元件,致使每一導電墊係電性連接至該等RDL元件其中之一。該方法還包含電性隔離相鄰之RDL元件,以及疊層該CMOS影像感測器晶圓組件和半導體裝置晶圓,以形成未晶粒切割之元件嵌入式影像感測器。
第三圖係顯示相機模組PCB 302上之元件嵌入式影像感測器300之平面圖,元件嵌入式影像感測器300包含影像感測器324和ASIC 326,其中ASIC 326位於影像感測器324下方。舉例而言,影像感測器324可為CMOS影像感測器。導線334將元件嵌入式影像感測器300和ASIC 326電性連接至相機模組PCB 302。
第四圖係顯示元件嵌入式影像感測器300之4-4'剖面圖。相較於第一圖習知技術,第三圖明顯說明元件嵌入式影像感測器300為更小尺寸裝置/元件,同時,嵌入式影像感測器300包含影像感測器124和ASIC 126之組合功能。
第五圖係根據本發明實施例顯示晶圓級方法500之步驟流程圖,方法500係以CMOS影像感測器晶圓組件製造元件嵌入式影像感測器,CMOS影像感測器晶圓組件包括影像感測器和頂部導電墊,影像感測器係形成於半導體晶圓上表面,頂部導電墊係自上述半導體晶圓上表面導電接合。方法500得被用以製造元件嵌入式影像感測器300。
第六圖-第十七圖係顯示方法500之每一步驟結果之示意圖。在不脫離本發明之精神與範圍下,半導體元件除了可為ASIC外,更可為其他可替換裝置,例如記憶模組。下文詳細描述說明第五圖之流程步驟,並同時參酌第六圖-第十七圖之示意圖,如此更加了解本發明精神所在。
第六圖係顯示CMOS影像感測器晶圓組件600之剖面圖。CMOS影像感測器晶圓組件600包含兩個影像感測器624,其形成於半導體晶圓607之上表面。間隔層611和保護基板612用以封裝該等影像感測器624。保護基板612可包含但不限於載體玻璃晶圓或薄膜。第六圖至第十三圖僅描繪影像感測器624和間隔層611之部分陣列。CMOS影像感測器晶圓組件600亦包括頂部導電墊621,其自上述半導體晶圓607之上表面617導線接合(wire-bondable),頂部導電墊621不具備保護基板612(absent protective substrate)。
第六圖係顯示兩個頂部導電墊621位於半導體晶圓607上表面617之示意圖。於一實施例中,中間材料層(intermediate material layer)可為間隔層611之一部分,在不脫離本發明範疇與精神下,中間材料層位於頂部導電墊621和半導體晶圓607之間,致使得頂部導電墊621之其中一者非直接形成於半導體晶圓607上表面。第六圖係顯示間隔層611一部分,其位於每一頂部導電墊621和保護基板612之間。在不脫離本發明範疇與精神下,於一實施例中,CMOS影像感測器晶圓組件600內,頂部導電墊621和保護基板612之間未存有間隔層611。
步驟502係選擇性步驟,倘若選擇者,方法500採用保護基板以保護影像感測器,該保護基板橫跨影像感測器,並且連接至每一支撐件(dam),支撐件係形成於半導體晶圓上,並與影像感測器同側,每一支撐件包含一頂部導電墊。
於步驟502實施例中,方法500以保護基板612覆蓋/保護影像感測器624,如第六圖所示。於第六圖中,影像感測器624圈選於虛線框內,為使圖式簡潔明瞭,後續圖式將省略虛線框。
於步驟504中,方法500自半導體晶圓之上表面下方薄化。於步驟504實施例中,方法500自上表面617下方,將半導體晶圓607薄化,以產生一薄化半導體晶圓707,如第七圖所示。第七圖係顯示經步驟504之封裝影像感測器624之剖面圖。半導體晶圓607可藉由晶圓背面研磨、蝕刻或其他習知 技術薄化。
於步驟506中,方法500移除半導體晶圓的至少一部分,以裸露頂部導電墊。於步驟506中,方法500形成一或多個切口821,其裸露頂部導電墊621,如第八圖所示。第八圖係顯示經步驟506後之封裝影像感測器624之剖面圖。舉例而言,藉由光刻圖案化光阻層(photolithographically patterned photoresist),以蝕刻薄化半導體晶圓707,形成切口821。步驟506可採用微製程蝕刻技術和方法,其包括同向性蝕刻、異性蝕刻、濕蝕刻、乾蝕刻(例如反應性離子蝕刻、濺射蝕刻、氣相蝕刻)和其它本領域習知技術。移除半導體晶圓707之部分713以獲得半導體晶圓807。
於步驟508中,方法500於半導體晶圓之已移除部分上形成一隔離層。於步驟510中,隔離層900覆蓋於半導體晶圓807上,並覆蓋於間隔層611和頂部導電墊621的裸露區域上,如第九圖。應當理解的是,在不脫離本發明範疇與精神下,中間層可形成於隔離層900和半導體晶圓807之間。
第九圖係顯示經步驟508後之封裝影像感測器624之剖面圖,於步驟508後,以隔離層覆蓋頂部導電墊621,致使頂部導電墊621免於裸露。隔離層900可以是氧化物,例如二氧化矽,其可透過化學氣相沉積或光化學沉積,抑或是,隔離層900可為有機材料,其透過塗佈或噴霧而形成之,在不脫離本發明範疇與精神下下,得使用其他沉積方法以完成本發明所需功效。
於步驟510中,方法500移除隔離層之至少一接觸部分,以裸露每一頂部導電墊621之表面1031。於步驟510實施例中,方法500裸露每一頂部導電墊621之表面1031,如第十圖所示。第十圖係顯示經步驟510後之封裝影像感測器624之剖面圖。於步驟510中,再暴露(reexposing)頂部導電墊步驟包含:在每一間隔層611下方形成一切口1041,並移除部分頂部導電墊621,以裸露導電墊表面1031。間隔層1011係包含間隔層611和頂部導電墊621已移除區域。隔離層1000係包含隔離層900和隔離層已移除區域913(如第九圖所示)。隔離層1000之表面1004係相對於保護基板612。
於方法500之實施例,步驟510包括施加一圖案化光阻至半導體晶圓表面,並蝕刻其切口,蝕刻技術可採納如步驟506所述之技術和方法。於另一可替換步驟510之實施例中,方法500藉由半導體晶圓607所形成之矽晶穿孔(TSV),以裸露每一頂部導電墊621之表面。
於步驟512中,在隔離層上形成圖案化重佈層(RDL),其具有複數個RDL元件,致使每一頂部導電墊電性連接至該等RDL元件之其中之一。於步驟512實施例中,於隔離層1000之表面1004上形成圖案化重佈層(RDL)1100,如第十一圖所示。
第十一圖係顯示經步驟512之封裝式影像感測器624之剖面圖。RDL 1100包含RDL元件1100(1-4),RDL元件1100(2)和1100(3)分別電性連接至相異頂部導電墊621,如第十一圖所示。文中所述之RDL元件1100(2)和1100(3)將視為各自頂部導電墊621之部分,熟知該項技術領域之通常知識者應當理解,RDL 1100可由Al、Al-Cu合金和Cu之其中一者或多者所形成,且RDL1100具有由鎳層和金層所組成之表面焊墊(metal finish)。
於步驟514中,電隔離步驟512所形成之相鄰RDL元件。於步驟514之實施例中,方法500藉由隔離層元件1210以隔離彼此相鄰的RDL元件1100,舉例而言,隔離層元件1210(1-3)係位於RDL元件1100上,並視為隔離層1000之一部分,因而形成CMOS影像感測器晶圓組件1200,如第十二圖12。於方法500之實施例中,隔離層1000和隔離層元件1210得由相同材料所組成,並協同形成隔離層1304,如第十三圖所示。於另一實施例中,隔離層1000和隔離層元件1210係由不同材料製成。第十二圖係顯示步驟514完成的CMOS影像感測器晶圓組件600內封裝式影像感測器624之剖面圖。
於步驟516中,疊層(laminate)CMOS影像感測器晶圓組件和半導體晶圓,以形成含有疊層晶圓組件之元件嵌入式影像感測器。於步驟516之實施例中,疊層CMOS影像感測器晶圓組件1200和底部半導體晶圓1336,以形成疊層式晶圓組件1307。
疊層式晶圓組件1307係屬未晶粒切割化之元件嵌入式影像感測器1300之一部分,如第十三圖所示。底部半導體晶圓1336包括數個ASICs 1326,每一ASIC 1326包含底部導電墊1316,其形成於半導體晶圓807之下表面。
應當理解的是,在不脫離本發明範圍下,中間層可位於底部導電墊1316和半導體晶圓807之間。同樣地,ASIC 1326可替換為不同半導體元件,例如記憶體模組。
於步驟517中,將每一ASIC電性連接至頂部導電墊。於步驟517之實施例中,每一異相導電薄膜(ACF)1302之其中一層,經由底部導電墊1316 及RDL元件1100,以電性連接至頂部導電墊621。第十三圖之切割平面1390表示可選步驟518將疊層晶圓組件1307予以單一化,如下文所述。
於實施例中,步驟516和步驟517可同時執行為單一步驟。可選步驟517中,ACF 1302得替換為粘合劑,其用以接合底部半導體晶圓1336和CMOS影像感測器晶圓組件1200,以及,可由底部導電墊1316上之每一RDL元件1100間之導電元件替換之。
第十四圖係顯示具有切割面1390疊加於疊層式晶圓組件1307之立體圖,切割面1390係正交於疊層式晶圓組件1307之平面。為使圖式簡單明瞭,第十四圖未顯示及標記保護基板612、所有切割平面1390以及元件嵌入式影像感測器1300。
於可選步驟518中,方法500將CMOS影像感測器晶圓組件予以單一化,以形成數個元件嵌入式影像感測器。於步驟518之實施例中,沿著切割平面1390將疊層晶圓組件1307予以單一化,以形成數個元件嵌入式影像感測器1500,如第十五圖所示。每一元件嵌入式影像感測器1500包含保護基板1512、半導體基板1507,ACF 1502及底部半導體基板1536,其分別自疊層式晶圓組件1307之保護基板612、半導體晶圓607、ACF 1302及底部半導體晶圓1336上形成。半導體基板1507具有上表面1517,其與半導體晶圓607之上表面617相同。可選步驟518可藉由鋸片(saw blade)、雷射切割(laser cutting)或其他單一化晶粒之習知技術以完成之。
於可選步驟520中,方法500移除保護基板。於步驟520實施例中,方法500自元件嵌入式影像感測器1500移除保護基板1512,如第十六圖之剖面圖所示。步驟520乃藉由頂部導電墊621,以將元件嵌入式影像感測器1500電性連接至PCB。每一頂部導電墊621具有裸露表面631,其形成於元件嵌入式影像感測器1500之上方,所述之上方包含影像感測器624和頂部導電墊621。
第十七圖係顯示元件嵌入式影像感測器1500導線接合至相機模組PCB 1702之剖面圖。導線接合1734類比於第一圖之導線接合134。一些導線接合1734係電性連接至影像感測器624,其它導線接合係經由頂部導電墊以電性連接至ASIC 1326。導線接合1734自上述半導體基板之上表面1517接合至頂部導電墊621,頂部導電墊621亦可經由覆晶方法(flip-chip method)以電性連接至相機模組PCB 1702,覆晶方法包括金凸塊接合(GSB)方法。
在不脫離本發明精神與範圍下,上述元件嵌入式影像感測器及其相關方法得允許更動或潤飾。應當理解的是,先前所述之說明及其附圖僅用以解釋,而非限制本發明之範圍。下述申請專利範圍廣泛涵蓋本文所述之通用和特定技術特徵,以及本發明探討方法和系統之陳述應落入於申請專利範圍中,不受相異語言而有所影響。
102、302‧‧‧照相機模組PCB
124、324、624‧‧‧影像感測器
126、326、1326‧‧‧特定應用積體電路(ASIC)晶片
134、136、334‧‧‧導線
300、1300、1500‧‧‧元件嵌入式影像感測器
500‧‧‧方法
502-520‧‧‧步驟
600‧‧‧影像感測器晶圓組件
607、707、807‧‧‧半導體晶圓
611、1011‧‧‧間隔層
612、1512‧‧‧保護基板
617、1517‧‧‧上表面
621‧‧‧導電墊
713‧‧‧移除晶圓部分
821、1041‧‧‧切口
900、1000、1304‧‧‧隔離層
913‧‧‧隔離層已移除區域
1004、1031‧‧‧表面
1100‧‧‧重佈層(RDL)
1100(1)-1100(4)‧‧‧重佈層(RDL)元件
1302、1502‧‧‧異相導電薄膜(ACF)
1304‧‧‧隔離層
1307‧‧‧疊層式晶圓組件
1316‧‧‧底部導電墊
1336‧‧‧底部半導體晶圓
1390‧‧‧切割面/切割平面
1507、1536‧‧‧半導體基板
第一圖係顯示習知技術相機模組PCB之平面圖,其包括CMOS影像感測器和ASIC。
第二圖係顯示第一圖相機模組PCB之剖面圖。
第三圖係顯示元件嵌入式影像感測器安裝於PCB上之平面圖。
第四圖是第三圖元件嵌入式影像感測器之剖面圖。
第五圖係顯示製造晶圓級晶片尺寸封裝影像感測器之步驟流程圖,影像感測器具有嵌入式半導體元件。
第六圖係顯示CMOS影像感測器晶圓組件之剖面圖,其包括形成於半導體晶圓上且被保護基板覆蓋之兩封裝式影像感測器。
第七圖係顯示第六圖CMOS影像感測器晶圓組件之薄化半導體晶圓之剖面圖。
第八圖係顯示第七圖CMOS影像感測器晶圓組件之數個裸露導電墊之剖 面圖。
第九圖係顯示第八圖CMOS影像感測器晶圓組件之半導體晶圓上覆蓋隔離層之剖面圖。
第十圖係顯示第九圖CMOS影像感測器晶圓組件之裸露導電墊之剖面圖。
第十一圖係顯示第十圖CMOS影像感測器晶圓組件之圖案化重佈層(RDL)形成於隔離層上之剖面圖。
第十二圖係顯示第十一圖CMOS影像感測器晶圓組件之隔離層元件之剖面圖,其形成於圖案化重佈層之縫隙中。
第十三圖係顯示第十二圖CMOS影像感測器晶圓組件之剖面圖,包含CMOS影像感測器組件和ASIC晶圓,該ASIC晶圓疊層異向半導體薄膜。
第十四圖係顯示第十三圖CMOS影像感測器晶圓組件之立體圖。
第十五圖係顯示第十三圖經CMOS影像感測器晶圓組件切割而得之兩元件嵌入式影像感測器之剖面圖。
第十六圖係顯示第十五圖元件嵌入式影像感測器移除保護基板之剖面圖。
第十七圖係顯示第十六圖元件嵌入式影像感測器安裝於PCB上之剖面圖。
300‧‧‧元件嵌入式影像感測器
302‧‧‧相機模組PCB
324‧‧‧影像感測器
326‧‧‧特定應用積體電路(ASIC)晶片
334‧‧‧導線

Claims (19)

  1. 一種元件嵌入式影像感測器,其包含:一影像感測器,形成於一第一半導體基板中;一頂部導電墊,形成於該第一半導體基板之一上表面上;以及一半導體元件,形成於一第二半導體基板中,該第二半導體基板係接合至該第一半導體基板之一下表面,該半導體元件電性連接至該頂部導電墊。
  2. 如申請專利範圍第1項所述之元件嵌入式影像感測器,其中(a)一重佈層(RDL)元件,以及(b)異向性導電材料之一部分,上述其中一者或二者用以將該半導體元件之一導電墊電性連接至該頂部導電墊。
  3. 如申請專利範圍第1項所述之元件嵌入式影像感測器,該第一半導體基板之該上表面係相鄰於該頂部導電墊之一下表面之至少一部分。
  4. 如申請專利範圍第1項所述之元件嵌入式影像感測器,該半導體裝置包含一特定應用積體電路(ASIC)。
  5. 如申請專利範圍第1項所述之元件嵌入式影像感測器,該影像感測器係為一CMOS影像感測器。
  6. 如申請專利範圍第1項所述之元件嵌入式影像感測器,該半導體元件係透過一電性連接路徑,以電性連接至該頂部導電墊,該電性連接路徑橫跨該第一半導體基板之一側邊。
  7. 如申請專利範圍第6項所述之元件嵌入式影像感測器,該電性連接路徑包含一底部導電墊,該底部導電墊係形成於該第一半導體基板之該下表面上。
  8. 如申請專利範圍第1項所述之元件嵌入式影像感測器,該半導體元件係透過一電性連接路徑,以電性連接至該頂部導電墊,該電性連接路徑橫跨該第一 半導體基板。
  9. 如申請專利範圍第8項所述之元件嵌入式影像感測器,該電性連接路徑包含一底部導電墊,該底部導電墊係形成於該第一半導體基板之該下表面上。
  10. 一種用以製造一元件嵌入式影像感測器之方法,係以一CMOS影像感測器晶圓組件為製造基底,該CMOS影像感測器晶圓組件包含一影像感測器及一頂部導電墊,該影像感測器形成於一半導體晶圓中,該頂部導電墊具有一裸露面,其形成於該半導體晶圓之一頂部側邊上,該方法包含以下步驟:移除該半導體晶圓之至少一部分,以裸露該頂部導電墊;於該半導體晶圓之已移除部分上形成一隔離層;移除與該頂部導電墊表面接觸之該隔離層之至少一部分,以裸露出該頂部導電墊之該表面;於該隔離層上形成具有圖案化重佈層(RDL),其具有複數個圖案化之重佈層(RDL)元件,致使該頂部導電墊電性連接至該等RDL元件其中之一者;電性隔離相鄰之RDL元件;以及疊層該CMOS影像感測器晶圓組件與一半導體元件晶圓,以形成未晶粒切割之元件嵌入式影像感測器。
  11. 如申請專利範圍第10項所述之方法,進一步包含:該頂部導電墊電性連接至該半導體元件晶圓之一半導體元件。
  12. 如申請專利範圍第10項所述之方法,該半導體元件晶圓包含一或多個特定應用積體電路(ASIC)。
  13. 如申請專利範圍第10項所述之方法,裸露該頂部導電墊之步驟包含:於該頂部導電墊下方之該半導體晶圓內形成一切口。
  14. 如申請專利範圍第13項所述之方法,形成複數個切口之步驟包含:蝕刻該半導體晶圓。
  15. 如申請專利範圍第10項所述之方法,形成該隔離層之步驟進一步包含:直接於該半導體晶圓上形成該隔離層。
  16. 如申請專利範圍第10項所述之方法,裸露該頂部導電墊之一表面之步驟包含:蝕刻該隔離層。
  17. 如申請專利範圍第10項所述之方法,其中裸露該頂部導電墊之一表面之步驟包含:形成一矽晶穿孔,以貫穿該半導體晶圓。
  18. 如申請專利範圍第10項所述之方法,電性隔離之步驟包含:於相鄰RDL元件間之縫隙中,各自形成複數個隔離層元件。
  19. 如申請專利範圍第10項所述之方法,該影像感測器係為一CMOS影像感測器。
TW104137623A 2014-11-14 2015-11-13 元件嵌入式影像感測器及其晶圓級製造方法 TWI573247B (zh)

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