TWI332790B - Image sensor module with a three-dimensional dies-stacking structure - Google Patents
Image sensor module with a three-dimensional dies-stacking structure Download PDFInfo
- Publication number
- TWI332790B TWI332790B TW096121327A TW96121327A TWI332790B TW I332790 B TWI332790 B TW I332790B TW 096121327 A TW096121327 A TW 096121327A TW 96121327 A TW96121327 A TW 96121327A TW I332790 B TWI332790 B TW I332790B
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- Prior art keywords
- image sensing
- die
- sensing module
- image
- stacked structure
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- 239000010410 layer Substances 0.000 claims description 38
- 239000000758 substrate Substances 0.000 claims description 18
- 229910000679 solder Inorganic materials 0.000 claims description 17
- 239000012790 adhesive layer Substances 0.000 claims description 6
- 230000006870 function Effects 0.000 claims description 5
- 239000002245 particle Substances 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 239000000463 material Substances 0.000 description 17
- 239000013078 crystal Substances 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 11
- 239000002184 metal Substances 0.000 description 11
- 239000011241 protective layer Substances 0.000 description 6
- 239000004020 conductor Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 238000005286 illumination Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005265 energy consumption Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000002313 adhesive film Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052792 caesium Inorganic materials 0.000 description 1
- TVFDJXOCXUVLDH-UHFFFAOYSA-N caesium atom Chemical compound [Cs] TVFDJXOCXUVLDH-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000008187 granular material Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 229940127554 medical product Drugs 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 229920000307 polymer substrate Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 235000013311 vegetables Nutrition 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
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- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H01L2223/66—High-frequency adaptations
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- H01L2224/0502—Disposition
- H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
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- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- Condensed Matter Physics & Semiconductors (AREA)
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- Electromagnetism (AREA)
- Manufacturing & Machinery (AREA)
- Solid State Image Pick-Up Elements (AREA)
Description
1332790 九、發明說明: 【發明所屬之技術領域】 本發明係關於一種影像感測模組之構裝結構;特別是 有關於一種具晶粒三維堆疊結構之影像感測模組構裝結 構。 【先前技術】 影像感測器已經被廣泛的應用在照相手機、照相機、 醫療診斷與保全監視方面,其中應用在可攜式與醫療產品 時,輕薄短小與減少能量損耗並降低製造成本一直是市場 的般切需求。已知的影像感測器構裝結構有以下幾種:美 國專利第6,646,289號第十一 A圖揭露一種影像感測器的 晶圓級封裝結構’係利用一重分佈導線層(Redistributed layer)將導線從晶粒邊緣重分佈到晶背,並用兩層玻璃夾住 該影像感測器;美國專利第5,051,802號第三圖揭露一種 影像感測器,係將影像感測器磨得非常薄,以致於從晶背 即可感光;美國專利第7,061,106號第一圖揭露一種影像 感測模組,係利用一插入元件(interposer)將一影像感測器 與其它晶粒作電性連接,並且將透鏡元件連接於該插入元 件上方;美國專利第6,429,036號第二圖揭露一種影像感 測器’係將保護該影像感測器的上蓋基材鑽孔形成電性導 通孔,以將電路外引,再利用錫球或金屬層接合方式將該 上蓋基材與該影像感測器作電性連接。 上述傳統影像感測器構裝方式係採半導體二維晶粒構 裝與線路連接方式,不僅電性連接距離較長,整體組裝模 組亦佔據較大面積,已經不符合未來產品朝輕薄短小、省 電與高效能的需求趨勢。因此,若將二維之晶粒導線佈局 5 1 J JZ/ i 方式改為三維的連接方式, 所遭遇的技術缺失。 將可以克服傳統二維構裝方式 【發明内容】 本發明提供-種具晶粒三維 二像處 建立垂直與水平的電性連接,以縮短
==模組的電性連接距離,並於該影像感測模組背 面形成錫球凸塊’使該影像感測模組直接峰於一電路板 上0
本發明提供的-種具晶粒三維堆疊結構之影像感測模 組,係包括至少一個影像感測晶粒、至少一個影像處理晶 粒、,一透光基材及複數個導電性銲墊。該影像感測晶粒與 該影像處理晶粒係上下堆疊接合,其中該影像感測晶粒之 一感測面朝上,該影像感測晶粒具有複數條垂直導線,藉 此以與該影像處理晶粒建立垂直與水平的電性導通。該透 光基材形成於該影像感測晶粒之該感測面上方,及該等導 電性銲墊形成於該影像感測模組背面。 本發明上述之影像感測模組係具有晶圓級構裝架構及 晶粒三維堆疊結構,可縮短該影像感測模組的電性連接距 離及降低該影像感測模組的整體組裝面積及高度,進而有 效增加單位面積的元件密度。 本發明前述之影像感測模組亦可結合並堆疊無線射 頻元件(RF component)、發光二極體元件、天線等主、被 動元件’以進一步提供無線傳輸與自我照明之功能。 【實施方式】 6 1332790 本發明具晶粒三維堆疊結構之影像感測模組係利用 三維晶圓級構裝之製造方式完成。以下就一實施例舉例說 明本發明具晶粒三維堆疊結構之影像感測模組的晶圓級構 裝製造方法。 第二圖係本發明具晶粒三維堆疊結構之影像感測模 組之第一具體實施例的結構截面示意圖。第一 A圖至第一 I圖係第二圖之具晶粒三維堆疊結構之影像感測模組20的 各製程步驟對應的結構截面示意圖。首先,參第一 A圖, 分別提供一透光基材10與一影像感測器晶圓12 »該透光 基材10可以是一玻璃基材或高分子基材。該影像感測器晶 圓12包含複數個影像感測晶粒12a,例如CMOS影像感測 晶粒,每一該影像感測晶粒12a具有·一感光區域121及複 數金屬層122形成於其上表面,以及複數個金屬銲墊123, 例如鋁墊,分別形成於一該金屬層122下方該影像感測晶 粒12a中,並與該金屬層122電性接觸《本發明利用黏著 層101將該透光基材10下表面與該影像感測器晶圓12上 表面接合在一起,該黏著層101可以是無機材料、高分子 材料或其等組合成之材料,以形成第一 B圖之結構,該透 光基材10係用以保護每一該影像感測晶粒12a。接著’仍 參第一 B圖,利用研磨方式(grinding)薄化該影像感測器晶 圓12之背面。參第一 C圖,利用晶粒黏著薄膜(die attach film) 142將複數個影像處理晶粒14以正面朝上方式分別 堆疊接合於每一該影像感測晶粒12a下表面。每一該影像 處理晶粒14之下表面形成有複數個銲墊143。參第一 D 圖,利用雷射鑽孔或蝕刻方式於該影像感測器晶圓12内形 成複數個導通孔(Through Silicon Via, TSV) 124,每一該導 通孔124係貫通該影像感測器晶圓12直至一該金屬層 1332790 122。參第一 E圖,將一絕緣層材料16以塗佈或壓合方式 内埋該等影像處理晶粒14,並且該絕緣層材料16填入該 影像感測器晶圓12的該等導通孔124内。參第—F圖, 形成袓數個介層洞161及162,每一該介層洞161貫通該
絕緣層材料16與該影像感測器晶圓12之一該導通孔124 直至該金屬層122。每一該介層洞162穿經該絕緣層材料 16直至每一該影像處理晶粒14之一該銲墊143。接著,參 第一 G圖,以賤鐘或無電極電鍵方式或電鑛方式將導電性 材料例如金屬填入該等介層洞161及162内,以形成導電 性内連線163及164,並同時於該絕緣層材料16的表面形 成重分佈導線層(redistributed layer) 165,進而建立每一該 影像感測晶粒12a與一該影像處理晶粒14的銲墊143的垂 直,水,的電性連接。參第一 H圖,以塗佈或壓合方式形 成二保Ϊ層18於該絕緣層材料16下方,並於該保護層18 内形成複數個錫球銲墊開口 182,分別位於一該導電性内 ,線163或丨64下方。參第一 I圖,形成一導電性銲墊183 =如金屬銲墊於每一該錫球銲墊開口 182中,接著以植 Ρ刷或電錢方式形成錫球凸塊184於該導電性銲塾183 I方再^此Γ來即形成本發明晶圓級構裝的影像感測模 ^沁著晶圓切割線切割晶圓,以將每一具晶粒尺寸構 ^衫像感測模組20從該晶圓分離出來。每一該影像 2〇戴面結構如第二圖所示。前述影像感測模組 -Δ 7錫球凸塊184即可直接組裝在一印刷電路板(未 三維^ Ϊ〔 W所示’本發明前述影像感測模組2 G具有晶粒 ^感測’係利用前述晶粒黏著賴142使該影 a與該影像處理晶粒14上下堆疊接合,而利 g 叫79〇 用該影像感測晶粒12a的該等導通孔與該絕緣層材料16 的該等介層洞填入導電性材料形成導電性内連線163及 164,並同時於該絕緣層材料16表面形成重分佈導線層165 電性連接該等導電性内連線163及164,以建立該影像感 別aa教12a與該影像處理晶粒14的垂直與水平電性連接, 進而縮短該衫像感測模組20的電性連接距離,以降低能量 的耗損。再者,該影像感測模組20的晶粒三維堆疊構裝方 式可減少整體組裝面積及高度,而有.效增加單位面積之元 •件密度,崎低製造成本。 第三圖係本發明具晶粒三維堆疊結構之影像感測模組 之第二具體實施例的結構戴面示意圖。在第二具體實施例 中’本發明具晶粒三維堆疊結構之影像感測模組3〇與第一 具體實施例之具晶粒三維堆疊結構之影像感測模組之 差別係在於先將該影像感測器晶圓12背面先形成複數個 凹槽,即母該影像感測晶粒12a的背面先形成一凹槽, 再將該影像處理晶粒14以正面朝上方式放置於該凹槽 鲁中,並利用一晶粒黏著薄膜142接合該影像感測晶粒121 與該影像處理晶粒14。第四圖係本發明具晶粒三維堆疊結 構之影像感測模組之第三具體實施例的結構截面示意圖。 在第三具體實施例中,本發明具晶粒三維堆疊結構之影像 感測模組40與第一具體實施例之具晶粒三維堆疊結構之 影像感測模組20之差別係在於該影像處理晶粒14係以背 面與該影像感測晶粒12a接合,並且該影像感測晶粒12& 與該影像處理晶粒14之間的水平電性連接係形成於該影 像處理晶粒14與該等錫球凸塊184之間。第五圖係本發^ 具晶粒二維堆疊結構之影像感測模組之第四具體實施例的 結構截面不意圖。在第四具體實施例中,本發明具晶粒三 維堆叠結構之影像感測模組50與第三具體實施例之具晶 粒二維堆疊結構之影像感測模組40之差別係在於該影像 ,測晶粒12a與該影像處理晶粒14之間的水平電性連接係 形成於該影像感測晶粒12a與該影像處理晶粒14之間。 第六圖係本發明具晶粒三維堆疊結構之影像感測模組 之第五具體實施例的結構截面示意圖。在第五具體實施例 中’本發明具晶粒三維堆疊結構之影像感測模組6〇與第一 具體實施例之具晶粒三維堆疊結構之影像感測模組20之 差別係在於該影像處理晶粒14與該影像感測晶粒12a之晶 ,大小一致’而該影像處理晶粒14並未内埋於該絕緣層材 料令’並且複數個導通孔均貫通該影像感測晶粒l2a 與該影像處理晶粒14,再藉由將導電性材料填入該等導通 孔與該絕緣層材料16的介層洞形成導電性内連線163及 164,並同時在該絕緣層材料16表面形成的重分佈導線層 165 ’以建立該影像感測晶粒12a與該影像處理晶粒14的 垂,與水平電性導通。換句話說,該影像感測晶粒12a與 該影像處理晶粒14之間的水平電性連接係形成於該影像 ,理晶粒14與該等錫球凸塊184之間。第七圖係本發明具 晶粒二,堆疊結構之影像感測模組之第六具體實施例的結 構截面不意圖。在第六具體實施例中,本發明具晶粒三維 ,叠結,之影像感測模組70與第五具體實施例之具晶粒 二=堆疊結構之影像感測模組60之差別係在於該影像處 f晶粒14係以背面接合於該影像感測晶粒12a下方,而該 影像感測晶粒12a與該影像處理晶粒14之間的導電性内連 線163及164係於該影像處理晶粒14背面完成。第八圖係 ^發明具晶粒三維堆疊結構之影像感測模組之第七具體實 施例的結構截面示意圖。在第七具體實施例中,本發明具 1332790 晶粒三維堆疊結構之影像感測模組80與第六具體實施例 之具晶粒三維堆疊結構之影像感測模組70之差別係在於 該影像感測晶粒12a與該影像處理晶粒14之間夾有一層絕 緣層材料19,並且該影像感測晶粒12a與該影像處理晶粒 14之間的水平電性連接166係形成於該影像感測晶粒12a 與該影像處理晶粒14之間的該絕緣層材料19中。 再者,本發明前述各種實施例之具晶粒三維堆疊結構 之影像感測模組亦可結合並堆疊無線射頻元件(RF component)、發光二極體元件、天線等主、被動元件(未示 出),以進一步提供無線傳輸與自我照明的功能。 此外,本發明亦可將前述影像感測晶粒12a與影像處 理晶粒14整合成一顆系統晶片(System On Chip, SOC)晶 粒,而該系統晶片晶粒下層可以是記憶體、無線射頻元件、 整合性被動元件(Integrated Passive Device, IPD)等元件或 其組合之另一系統晶片晶粒。 第九圖係本發明具晶粒三維堆疊結構之影像感測模組 之第八具體實施例的結構截面示意圖。在第九具體實施例 中,本發明具晶粒三維堆疊結構之影像感測模組9 0係包含 一透光基材10、一具影像處理功能之影像感測晶粒901、 一整合有記憶體、無線射頻元件及整合性被動元件之系統 晶片晶粒905、一絕緣層材料16、一保護層18及複數個錫 球凸塊184。該影像感測晶粒901具有一感光區域121,其 藉由黏著層101接合於該透光基材10下方。該系統晶片晶 粒905係内埋於該絕緣層材料16十並藉由晶粒黏著薄膜 142接合於該影像感測晶粒901的背面。該保護層18係形 成於該絕緣層材料16下方’而該等錫球凸塊184位於該保 護層18之銲墊開口(未示出)中,藉該等錫球凸塊184使該 1332790 具晶粒三維堆疊結構之影像感測模組9〇直接組裝於一電 路板上,例如印刷電路板上。 • 第十圖係本發明具晶粒三維堆疊結構之影像感測模組 之第九具體實施例的結構截面示意圖。在第九具禮實施例 中’本發明具晶粒三維堆疊結構之影像感測模組100與第 八具體實施例之具晶粒三維堆疊結構之影像感測模組90 之差別在於記憶體902、無線射頻元件9〇3及被動元件904 係内埋於該絕緣層材料16中並藉由晶粒黏著薄膜142分別 • 接合於該影像感測晶粒901的背面。第十一圖係本發明具 晶粒三維堆疊結構之影像感測模組之第十具體實施例的結 構戴面示意圖。在第十具體實施例中,本發明具晶粒三維 堆疊結構之影像感測模組11〇與第八具體實施例之具晶粒 三維堆疊結構之影像感測模組90之差別在於將至少一個 發光二極體元件906放置於該影像感測晶粒901上方,並 於該透光基材10中對應每一該發光二極體元件906上方形 成一導光通道907及一透鏡元件908形成於該導光通道 0 9〇7頂端。如此一來,該具晶粒三維堆疊結構之影像感測 模組110即具有自我照明之功能。第十二圖係本發明具晶 粒三維堆疊結構之影像感測模組之第十一具體實施例的結 構截面示意圖。在第十一具體實施例中,本發明具晶粒三 維堆疊結構之影像感測模組12〇與第八具體實施例之具晶 粒三維堆疊結構之影像感測模組9〇之差別在於該影像感 測晶粒901的上表面係利用濺鍍或電鍍方式形成天線結構 909’以使該具晶粒三維堆疊結構之影像感測模組12〇具有 無線傳輸的功能。 以上所述僅為本發明之具體實施例而已,並非用以限 定本發明之申請專利範圍;凡其它未脫離本發明所揭示之 12 1332790 精神下所完成之等效改變或修飾,均應包含在下述之申請 專利範圍内。
13 1332790 【圓式簡單說明】 第一 A圖至第一I圖係本發明具晶粒三維堆疊結構之 影像感測模組之第一具體實施例之各製程步驟對應的結構 截面示意圖; 第二圖係本發明具晶粒三維堆疊結構之影像感測模 組之第一具體實施例的結構截面示意圖; 第三圖係本發明具晶粒三維堆疊結構之影像感測模 組之第二具體實施例的結構截面示意圖; 第四圖係本發明具晶粒三維堆疊結構之影像感測模 組之第三具體實施例的結構截面示意圖; 第五圖係本發明具晶粒三維堆疊結構之影像感測模 組之第四具體實施例的結構截面示意圖; 第六圖係本發明具晶粒三維堆疊結構之影像感測模 組之第五具體實施例的結構截面示意圖; 第七圖係本發明具晶粒三維堆疊結構之影像感測模 組之第六具體實施例的結構截面示意圖; 第八圖係本發明具晶粒三維堆疊結構之影像感測模 組之第七具體實施例的結構截面示意圖; 第九圖係本發明具晶粒三維堆疊結構之影像感測模 組之第八具體實施例的結構截面示意圖; 第十圖係本發明具晶粒三維堆疊結構之影像感測模 組之第九具體實施例的結構截面示意圖; 第十一圖係本發明具晶粒三維堆疊結構之影像感測 模組之第十具體實施例的結構截面示意圖;及 第十二圖係本發明具晶粒三維堆疊結構之影像感測 模組之第十一具體實施例的結構截面示意圖。 1332790 【主要元件符號對照說明】 10—透光基材 12----影像感測益晶圓 12a、901-…影像感測晶粒 14—--影像處理晶粒 16、19—絕緣層材料 18—保護層 20 ' 30、40 ' 50 ' 60 ' 70 ' 80 ' 90、100、110 ' 120 -…具晶粒三維堆疊結構之影像感測模組
101 —黏著層 122…-金屬層 124—--導通孔 143…-銲墊 163、164-…導電性内連線 165-…重分佈導線層 182-…錫球銲墊開口 184—錫球凸塊 902…-記憶體 904—被動·7〇件 906-…發光二極體元件 908-…透鏡元件 121----感光區域 123-…金屬銲墊 142 —晶粒黏者薄膜 161、162—介層洞 166—水平電性連接 183-…導電性銲墊 903—無線電頻元件 905 —糸統晶片晶粒 907-…導光通道 909-…天線結構 15
Claims (1)
1332790 十、申請專利範固: 1 · 一種具晶粒三維堆疊結構之影像感測模組,其包括: 至少一個影像感測晶粒; 至少一個影像處理晶粒,該影像感測晶粒與該影像處 理晶粒係上下堆疊接合,其中該影像感測晶粒之一感測面 朝上,該影像感測aa粒具有複數條垂直導線,藉此以盘該 影像處理晶粒建立垂直與水平的電性導通; 一透光基材’形成於該影像感測晶粒之該感測面上 方;及 複數個導電性銲墊’形成於該影像感測模組背面。 2·如申請專利範圍第1項所述之具晶粒三維堆疊结構 之影像感測模組,其中更包含一絕緣層,使該影像處理曰 粒内埋於其中。 3·如申請專利範圍第1項所述之具晶粒三維堆疊結構 之影像感測模組,其中該影像感測晶粒背面具有一二& 以放置該影像處理晶粒。 4.如申請專利範圍第丨項所述之具晶粒三維堆最纟士 之影像感測模組,其中該影像處理晶粒係以正面ϋ 面朝下的方式堆疊於該影像感測晶粒下方。 $正 5·=申請專利範圍第i項所述之具晶粒三維堆爲 之影像感測模組’其中該影像制晶粒與 、= 的水平電性連接係位於該影像處理晶粒與粒 墊之間或該影像處理晶粒與該影像感測晶粒之間。眭銲 16 1332790 6.如申請專利範圍第1項所述之具晶粒三維堆疊結構 之影像感測模組,其中至少一該垂直導線係貫通該ϋ 測晶粒及該影像處理晶粒。 ° 7.如申請專利範圍第6項所述之具晶粒三維堆疊結構 之影像感測模組,其中該影像感測晶粒與該影像處粒 的水平電性連接係位於該影像處理晶粒與該等導電:銲 • 墊之間或該影像處理晶粒與該影像感測晶粒之間。 8·如申請專利範圍第6項所述之具晶粒三維堆疊結構 之影像感測模組,其中該影像處理晶粒係以正面朝上或正 面朝下的方式堆疊於該影像感測晶粒下方。 9·如申請專利範圍第丨項所述之具晶粒三維堆疊結構 之影像感測模組,其中更包含至少一個發光二極體元件位 於該影像感測晶粒上方。 10.如申睛專利範圍第9項所述之具晶粒三維堆疊結 構之影像感測模組,其中更包含至少一導光通道貫通該透 光基材並形成該發光二極體元件上方及至少一個透鏡元 件形成於該導光通道上方。 11.如申請專利範圍第1項所述之具晶粒三維堆疊結 構之影像感測模組,其中更包含至少一個天線元件形成於 該影像感測晶粒上方。 17 1332790 12.如申請專利範圍第1項所述之具晶粒三維堆疊結 構之影像感測模組,其中更包含一黏著層’以接合該影像 感測晶粒與該影像處理晶粒。 13·如申請專利範圍第1項所述之具晶粒三維堆疊結構 之影像感測模組,其中更包含複數個錫球凸塊,係分別形 成於一該導電性銲墊下方,而藉該等錫球凸塊使該影像感 測模組與外界產生電性導通。
14.一種具晶粒三維堆疊結構之影像感測模組,其包 括: 至少一個影像感測晶粒,係内含有影像處理功能; 一絕緣層,係形成於該影像感測晶粒下方; 一系統晶片晶粒與該影像感測晶粒上下堆疊接合,复 中該影像感測晶粒之一感測面朝上,該系統晶片内埋於^ 絕緣層中; 、
一透光基材,形成於該影像感測晶粒之該感測面上 方;及 複數個導電性銲墊,形成於該影像感測模組背面。 15.如申請專利範圍第14項所述之具晶粒三維 绛 構之影像感測模組,其中該系統晶片晶粒包含記憶體 線射頻元件、整合性被動元件、獨立的被動元件^其等^ 組合。 16.如申請專利範圍第14項所述之具晶粒三維 姓 構之影像感測模組,其中更包含至少一個發光二極體 18 1332790 位於該影像感測晶粒上方。 17·如申請專利範圍第16項所述之具晶粒三維堆疊結 構之影像感測模組,其中更包含至少一導光通道貫通 光基材並形成該發光二極體元件上方及至少一個透鏡元 件形成於該導光通道上方。 兄 18.如申請專利範圍第14項所述之具晶粒三維堆疊結 • 構之影像感測模組’其中更包含至少一個天線元件开彡出认 該影像感測晶粒上方^ 成; 19·如申請專利範圍第14項所述之具晶粒三維堆疊妗 構之影像感測模組,其中更包含一黏著層,以接合該^ 感測晶粒與該系統晶片晶粒。 〜
20.如申請專利範圍第14項所述之具晶粒三維堆疊結 構之影像感測模組,其中更包含複數個錫球凸塊,係 形成於一該導電性銲墊下方’而藉該等錫球凸塊使該f象 感測模組與外界產生電性導通。 人如 19
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