TWI326479B - Selective capping of copper wiring - Google Patents

Selective capping of copper wiring Download PDF

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Publication number
TWI326479B
TWI326479B TW093119947A TW93119947A TWI326479B TW I326479 B TWI326479 B TW I326479B TW 093119947 A TW093119947 A TW 093119947A TW 93119947 A TW93119947 A TW 93119947A TW I326479 B TWI326479 B TW I326479B
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Taiwan
Prior art keywords
copper
dielectric material
channel
group
trench
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TW093119947A
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English (en)
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TW200520151A (en
Inventor
Panayotis C Andricacos
Shyng-Tsong Chen
John M Cotte
Hariklia Deligianni
Mahadevaiyer Krishnan
Wei-Tsu Tseng
Philippe M Vereecken
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Ibm
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67075—Apparatus for fluid treatment for etching for wet etching
    • H01L21/6708—Apparatus for fluid treatment for etching for wet etching using mainly spraying means, e.g. nozzles
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electroplating Methods And Accessories (AREA)

Description

1326479 九、發明說明： 【發明所屬之技術領域】 本發明係關於製作圖案化銅結構且尤其係關於銅與襯墊 材料接觸之圖案化銅結構。本發明係關於採用選擇性蝕刻 及/或選擇性電鍍而選擇性地封蓋銅。本發明亦係關於適於 使封蓋材料沈積於銅上之裝置。 【先前技術】 用於晶片内互連、當前藉由（單或雙）鑲嵌整合方法製作 之銅引線藉由襯墊或障壁（例如，-Ta、W、其氮化物及其多 層）圍繞在側面及底部，其作用是防止Cu擴散至層間介電材 料（ILD)(例如，Si02及低k介電質）且提供Cu導體與ILD之間 的極好黏附。另外，襯墊防止〇2或其它物質擴散至Cu導體 中。該等材料之擴散將引起導體的化學變化且不利地影響 其電阻率及其它性質。近期作品：Hu等人之 "Electromigration in On-Chip Single/Dual Damascene Cu Interconnections", J. Electrochem. Soc ，第 149 頁， G408(2002)；及 Hu 等人之"Scaling Effect on Electromigration in On-Chip Cu Wiring", Proc. IITC(1999) 第 267 頁；C.-K. Hu 及 S. Reynolds 之，，CVD Cu Interconnections and Electromigration", Electrochem. Soc. Proc.第97-25卷（1997)，第1514頁，已展示表面擴散是Cu 電遷移之主要方式，因此Cu導體至襯墊之良好黏附幫助抑 制電遷移是顯然的。已展示諸如Ta/TaN之雙層材料是極好 的擴散障壁且提供極好的黏附及電遷移抑制。舉例而言， 94117.doc 1326479 參看 Edelstein等人之"a High Performance Uner f〇r c〇沖^
Damascene Interconnects”，2001 IEEE IITC 之會議錄 (Proceedings)，第 9_11 頁，（2001)。 在銅上提供適當的封蓋材料抑制銅導體材料之電遷移。 雖然鑲嵌整合提供便利方式保護在側面上與底部之c u導 體，但是其未提供在結構頂部之令人滿意的解決辦法。 封蓋此等結構之頂部引起更多挑戰，此歸因於在製作多 層互連結構中對層之間的平面度的要求。無 選擇性沈積於互連結構上；法餘供= 材料且層之間不平坦。同樣，目前為抑制自頂部之a擴散 或電遷移，在Cu及周圍的ILD平坦化之後且建置隨後的金 屬化層之前沈積如SixNy之毯覆式薄膜材料（圖1}。雖然已證 明該等層適合前代處理器，但是朝減少有效層間介電常= 且增強避免電遷移之驅動力建議發展選擇性沈積於&導體 頂部的新材料及整合方法(圖D。顯然即使毯覆式薄膜解決 了電遷移及擴散問胃，但其可引起該結構之整個介電常數 的無法接受的增加。 因此，本發明係關於用於選擇性封蓋銅之改良的方法及 裝置。 【發明内容】 本發明係關於解決銅之封篆門 …〃 心釕盍問碭。詳言之，本發明之一 悲樣係關於一種用於製作圖荦 口系化銅結構之方法，其包括在 基板上提供介電材料；在介 冤材枓中提供至少一個渠溝/通 迢’在至少一個渠溝/通道 底0卩與側壁上及至少一個渠溝 94117.doc 1326479 /通道附近之介電材料的水平表面上提供襯墊；在至少一個 渠溝/通道中襯墊上沈積銅以填充該渠溝/通道；選擇性電蝕 刻或選擇性化學蝕刻銅以使銅相對於該結構之頂表面凹 陷0 本發明之另一態樣係關於圖案化銅結構，其包括：—基 板，在該基板上具有介電材料，其中介電材料於其中含有 至少一個渠溝/通道； 一位於至少一個渠溝/通道之底部及侧壁上的襯墊； 位於至少一個渠溝/通道中之襯墊上的銅；及 一封蓋結構’其直接位於銅上且包括選自由Co、c〇p、
CoWP、CoMoP、Ni、NiP、NiWP、NiMoP、NiW、NiMo、 CoMo、NiFe、CoFe、NiFeP、CoFeP、NiB、CoB、NiFeB、 CoFeB ' NiCo、NiCoP、NiCoB、NiWB、NiMoB、CoWB、 CoMoB、CoV、NiV、CoFeV、NiFeV、NiCoV、NiCoFeV、 N1C0組成之群的第一金屬或合金層；及選自由Ru、Re、p卜
Pd Rh ' 〇s、NiPd、CoPd、Pb、Sn、Sb及 In組成之群的第 二金屬或合金層。 本發明之又一態樣係關於圖案化銅結構，其包括：一基 板，在该基板上具有介電材料，其中介電材料於其中含有 至少一個渠溝/通道； 一位於至少一個渠溝/通道之底部及側壁上的襯墊； 位於至少一個渠溝/通道中襯墊上的銅；及一位於銅上且 包括含有釕、鍊、餓及铑之層的封蓋結構。 本心明之另m系關於_種用於製作圖案化銅結構之 94I17.doc 1326479 封蓋存在襯墊材料情況下的銅。根據本發明，在襯墊材料 移除之前停止在典型製程中所採用以建立銅結構的平坦化 製程，如鑲嵌或雙鑲嵌製程。根據本發明在存在襯墊材料 的情況下執行選擇性蝕刻及/或選擇性電鍍。此使得在隨後 移除襯墊後消除分路（bridging)與短路（sh〇rt)成為可能。 如圖1A所說明，（舉例而言）晶圓表面此時係平面且由兩 類型表面組成’ Cu表面1〇及襯墊表面12(Ta、TaN、w、WN 及其類似物）。 如將在下文中詳細論述的，銅表面藉由封蓋材料而進行 選擇性蝕刻及/或選擇性電鍍。為了理解本發明，將參考圖 框（frame) 〇 如圖1A所說明的，銅引線10包含於半導體基板14上如 矽、矽鍺合金及碳化矽或砷酸鎵。銅引線1〇藉由包含諸如 二氧化矽（si〇2)、磷矽酸鹽玻璃（PSG)、硼摻雜pSG(BDpsG) 或四乙基正矽酸鹽（TE0S)之介電質16而電絕緣。另外，介 電質可包含低介電常數材料，諸如氟化Si〇2 '有機聚合物 及多孔介電質。 在銅引線10與介電質16之間沿銅引線10之底部及側壁採 用襯墊或障壁層12。襯墊12亦存在於銅引線1〇附近之介電 質16的水平表面上。 根據本發明之一態樣，如圖1B所展示，在存在襯墊12的 情況下藉由電蝕刻使銅10選擇性凹陷。 概塾12通常係Ta、TaN、W、_或該等材料之兩個或兩 個以上的多層。 94117.doc -10- 1326479 及大約㈣伏特的電麼。下面表格中揭示了典㈣刻參數。 如在圖1C中所說明’藉由電鍍選擇性沈積封蓋或障壁層 18、20 〇障壁層不電鐘在襯墊上且僅在鋼上。典型的電錢 製程，用釕作為實例，採用自亞確醯基硫酸鹽釕鹽與大^ 2〇g/lH2S〇4製備之含有大約2的釕的溶液。典型的沈積溫 度為大約50。至大約航且更一般為大約6〇。至大約赃，具 有大約15%至大約30%的電流效率。電流密度通常為大約5 mA/cm2至大約100 mA/cm2且更一般為大約i〇 mA/cm2。工 件（晶圓）一般以大約50至大約12〇 rpm旋轉，較佳為大約9〇 rpm。時間變化取決於所要求的厚度，但是一般小於大約 10 0 0 秒。 在另釕電鑛貫例中，將自Enthone OMI之在商標名稱 'Ruthenex SP”下市售的浸泡劑進行修改以含有大約4旦八 Ru至大約12 g/i ru。此外，”Ruthenex sp，,浸泡劑含有相對 大量的Mg鹽及相對少量的Ni ^ ]^§與1^金屬一起沈積且充 當應力消除劑（reducer)。對於藉由含有厘§及Ni之浸泡劑的 電沈積條件類似於上述條件。 在又一實例中’自Enthone OMI在商標名稱"Rhodex 100" 下市售之浸泡劑中沈積Rh。該浸泡劑含有大約4 g/1 Rh及應 力消除添加劑。通常以小於10 mA/cm2之電流密度與大於約 3〇%之電流效率沈積铑。較佳地相對電流密度控制沈積速 率以便控制沈積粗糙度。 圖7展示已選擇性電鍍於凹陷Cu上之薄Ru層。釕對Cu擴 散而言是择好的障壁且同時足夠惰性（noble)以經受住隨後 94117.doc -12· 1326479 的襯墊移除製程（諸如CMP或RIE)之化學變化。另外，在Ru 沈積之前，可藉由電解電鍍使抑制電遷移之CoWP層沈積於 Cu上，藉此形成雙CoWP/Ru障壁。 用作封蓋層之其它適當的金屬或合金之實例為Ta、 TaN、TaSiN、W、WN、Co、COP、CoMoP、Ni、NiP、NiWP、 NiMoP、NiW、NiMo、CoMo、NiFe、CoFe、NiFeP、CoFeP、 NiB、CoB、NiFeB、CoFeB、NiCo、NiCoP、NiCoB、NiWB、 NiMoB、CoWB、CoMoB、CoV、NiV、CoFeV、NiFeV、 NiCoV、NiCoFeV、NiCo、Ru、Re、Pt、Pd、Rh、Os、NiPd、 CoPd、Pb、Sn '、Sb及 In o 根據本發明之一些較佳結構包含Cu導線，其藉由選自由 Co、CoP、CoWP、CoMoP、Ni、NiP、NiWP、NiMoP、NiW、 NiMo、CoMo、NiFe、CoFe、NiFeP、CoFeP、NiB、CoB、 NiFeB、CoFeB、NiCo、NiCoP、NiCoB、NiWB、NiMoB、 CoWB、CoMoB、CoV、NiV、CoFeV、NiFeV、NiCoV、 NiCoFeV、NiCo組成之群的第一金屬或合金及選自由Ru、 Re、Pt、Pd、Rh、Os、NiPd、CoPd、Pb、Sn、Sb及 In組成 之群的第二金屬或合金所封蓋。 下一個如圖1D所展示，如藉由化學機械拋光自介電質16 上之水平表面移除襯墊材料12。典型的CMP製程包含用含 有氧化劑、研磨劑及腐蝕抑制劑之漿來拋光襯墊，如美國 專利第6,375,693號中所描述，該揭示案以引用的方式倂入 本文中。選擇所採用之封蓋材料使得其不被化學機械平坦 化製程不利地影響。 94117.doc -13 - 1326479 在替代製程順序中’藉由無電鍍或交換電鍍選擇性沈積 于a根據所採用的材料，在使銅i 〇凹陷之後，如藉由CMp 移除水平表面上的襯塾且使諸如把或錫叙催化劑之晶種層 選擇性沈積於銅10上，接著在晶種表面上選擇性電鍍。藉 由用含有錯合劑（諸如EDTA或檸檬酸鈉）之溶液漂洗以移除 附於；|电貝上之任何pd離子而不移除在銅表面上之μ金 屬可達成選擇性種於銅上且避免種於介電質上，該方法揭 不於（例如）美國專利第6,503,834 B1號中，該揭示案以引用 的方式倂入本文中。例如，參看其第3行、第64與65列。可 在以職1 等人所著的”Synthesis and Characterization of Hydrous Ruthenium Oxide-Carbon Supercapacitor", J. Electrochem. Soc., 148(4)，A374-380(2001)中找到用於釕之 無電沈積的實例，該揭示案以引用的方式倂入本文中。例 如，所採用的典型浸泡劑含有大約〇〇14莫爾濃度氯化釕、 大約0.27莫爾濃度次磷酸納、大約G ()14莫爾濃度捧樣酸氮 一鉍及大約0.07莫爾濃度草酸銨。浸泡劑之pH值藉由週期 性添加氫氧化鈉而一般維持在大約9 5且浸泡劑的溫度一 般保持在大約90°C。 參考圖2A-2D說明了根據本發明之另一製程順序。圖μ 與2B類似於上述之圖以與⑺中所說明的製程順序，造成圖 2B所展示之凹陷的銅結構。在圖％中，藉由如(例如则 ic中之步驟所描述的電解電鍍而毯覆式沈積封蓋層。如 在圖2D中所展示，如藉由化學機械抛光而移除介電質此 水平表面上的層18以電絕緣導線。同樣，如在圖扣中所展 94117.doc -14- 不，如藉由化學機械拋光而移除介電質16之水平表面上的 襯墊12。
在圖3A3D中展不了根據本發明之另一製程順序。圖3A 與3B頒似於如上所揭示的圖1 A與1B中所說明的製程順 序’造成圖3B所展示之凹陷的銅結構。毯覆式沈積封蓋層 8繼而可&積金屬、金屬合金或介電層22(參看圖3 c)。 代替電解沈積，可採用視為無電鍵之其它沈積技術，⑽ 及 CVD。 如圖3D中所展示，如藉由化學機械抛光可自介電質16之 水平表面移除層18及層22。同樣，如圖31)中所展示，如藉 由化學機械拋光移除介電質16之水平表面上的襯墊12。 圖4A-4C說明了根據本發明之另一製程。在圖4八中，可 得到類似於上面所揭示的圖丨人之此結構的結構。下一步， 如圖4B中所說明，根據本發明之此態樣，代替沈積毯覆式 材料，晶圓經歷電解步驟，其中一材料或複數種材料18、 20選擇性沈積在Cu表面上而不是在襯墊表面上。設計電鍍 製程以提供所要的選擇性。較佳地襯墊材料為Ta或w、或 其氮化物，此係因為此等材料在其上電鍍時具有相當大的 抵抗性。如圖4C中所展示’障壁層18、20之選擇性電鍍之 後，如藉由CMP或RIE製程移除襯墊材料。在各種實施例中 障壁總成之頂層20的額外功能為保護該總成之其餘部分免 受用於移除襯墊12之製程的影響。 較佳地障壁或封蓋總成之總厚度至多為Cu導體厚度之大 約10%且一般至少為大約50埃且更一般為大約5〇埃至大約 94117.doc -15- 1326479 5〇〇埃 0 如圖1B、2B及3B中所說明，本發明之較佳製程採用使銅 ^擇性凹陷。為了便利整合，較佳地使Cu導體相對於襯塾 表面所界定之平面凹陷。以此方式，選擇性沈積於Cu上的 任何材料不突出。 顯然’上述整合序列不限於製作以互連結構。使用以金 屬化且要求使銅凹陷之任何其它設備可使用上述方法。該 等設備可包含厚Cu電感器、金屬板由Cu製成之電容器、 MEMS設備如MEMS開關及MEMS諧振器及其類似物。 根據本發明之電蝕刻最初在Datta等人之美國專 5,486,282號中描述的裝置中進行，該裝置裝備有喷泉型^ 嘴’其寬度為晶圓直徑之約10%且長度大於晶圓直徑。4 喷泉喷嘴/陰極之上面朝下置放晶圓（陽極）；電極距離間3 滿電解質（濃磷酸）。在陽極/晶圓與陰極/噴嘴之間以直流至 脈動形式施加電位。如下表丨中所展示，藉由諸如施加的$ 壓波形式之工作循環與噴嘴速度的該等參數可控制銅凹p 量 '然而’在晶圓中心之凹陷Cu量大大少於在晶圓邊⑽ 量。因此，本發明之較佳態樣將克服”端效應（termin; effect)" 電解質 電位 (伏特) 噴嘴速度 jcm/sec) 工作循環 (%) 移除銅 _ (ang)
94117.doc 1326479 ' 因此此描述並非意欲將本發明+ 示的W。I 不赞明限疋於本文所揭 ^ 同樣，希望將附加申請專剎r w \ 代實施例。 利範圍为析為包含替 【圖式簡單說明】 圖說明了採用選擇性_之本發明的製程順序。 =:心說明了採用選擇㈣刻之本發明的替代序列。 A-3D說明了採用選擇性㈣之本發明的替代序列。 圖4A-4C說明了採用選擇性電 疋评丨电緞之本發明的製程順序。 5 C)時鋼之afm影像 5A-5C係電鑛（圖5A)及在 1、。*^ 你个丨』條件下電蝕刻（圖5B及
〆} 0弄翻夕Δ 17 A/Γ ^ JA 截Γ具有經選㈣電㈣之_雙錢結構之 圖7係在經選擇性電抛光之銅凹陷部分内的經選擇性電 鍍之釕的SEM。 电 圖8係適於選擇性電㈣及回填銅之工具的示意圖 圖9A-9C係在圖8之工具令使用的歧管電極之示意圖 【主要元件符號說明】 10 銅引線/銅表面 12 襯墊/襯墊表面 14 基板 16 介電質 18 障壁/封蓋層/材料 20 障壁/封蓋層/材料/頂層 22 介電層 94117.doc •19·

Claims (1)

1326479 第093119947號專利申請案 中文申請專利範圍替換本(98年11月） 十、申請專利範圍： 一種用於製作一圖案化銅姓 钔、，、〇構之方法，其包括在一基板 上提供介電材料，在該介雷鉍 , 社㈠丨屯材枓中提供至少—個渠溝/通 遏；在該至少一個渠溝/通道之底部與側壁上及該至少一 個渠溝/通道附近之該介電材料的水平表面上提供一襯 墊； 在該襯墊上該至少一個渠溝/通道中沈積銅；且藉由電 _選擇性_該銅以使該銅相對於該介電材料之頂表 面凹陷；及 藉由電解電鍍或無電鍍而選擇性沉積一或多種材料於 該Cu上；及 其中經由一用於該電蝕刻之喷嘴來施加蝕刻劑，且該 噴觜係直徑小於該基板之直徑的圓形，以在該電蝕刻過 耘中減少總電流，且其中在大體上恒定的電流條件下執 行该電餘刻。 虫明求項1之方法，其中該選擇性钱刻Cu之後是—或多個 障壁或介電材料的毯覆式沈積。 3. 如請求項2之方法，其中該毯覆式沈積之後是用於自該介 電材料之s玄等水平表面移除襯墊之平坦化。 4. 如請求項1之方法’其中該選擇性蝕刻Cu之後是藉由電解 電鍛使一或多種材料選擇性沈積於該Cu上。 5·如請求項4之方法，其中該等材料選自c〇、CoP、CoWP、 CoMoP、Ni、NiP、NiWP、NiMoP、NiW、NiMo、CoMo、 NiFe、CoFe、NiFeP、CoFeP、NiB、CoB、NiFeB、CoFeB、 94117-981123.doc 1326479 NiCo、NiCoP、NiCoB、NiWB、NiMoB、CoWB、CoMoB、 C〇V、NiV、CoFeV、NiFeV、NiCoV、NiCoFeV、NiCo、 Ru、Re、pt、pd、Rh、〇s、Nipd、c〇pd、pb、、外 及In之群。 6. 如請求項5之方法，其中該電解電鍍之後是用於自該介電 材料之該等水平表面移除襯塾之平坦化。 7. 如請求項4之方法，其中該藉由電解電鍍之選擇性沈積之 後是金屬或合金之該毯覆式沈積。 8. 如請求項7之方法，其進一步包括該毯覆式沈積之後的平 坦化。 9. 如咕求項4之方法，其中經由一用於該選擇性沉積之電解 電鍍之噴嘴來施加該等材料，且該喷嘴係直徑小於該基 板之直徑的圓形，以在該電解電鍍過程中減少總電流， 且其中在大體上恒定的電流條件下執行該電解電鍍。 1〇·如請求項6之方法，其中該等材料包含一第一金屬或合金 層，、選自由 Co、CoP、CoWP、CoMoP、Ni、NiP、NiWP、 NiMoP、NiW、NiM〇、c〇M〇、NiFe、c〇Fe、NiFep、、 CoB NiFeB、CoFeB、NiCo、NiCoP、NiCoB、NiWB、 NiMoB、c〇WB、CoMoB、CoV、NiV、CoFeV、NiFeV、 NiCoV、NiCoFeV及NiC〇組成之群；及一第二金屬或合金 層，其選自由 Ru、Re、Pt、Pd、Rh、〇s、Nipd、c〇pd、 Pb、Sn、Sb及In組成之群。 11. 如請求項4之方法，其中該材料包含Ru。 12. 如請求項1之方法，其中該等材料包含一第一金屬或合金 94117-981123.doc 1326479 層，其選自由 Co、CoP、CoWP、CoMoP、Ni、NiP、NiWP、 NiMoP、NiW、NiMo、CoMo、NiFe、CoFe、NiFeP、NiB、 CoB、NiFeB、CoFeB、NiCo、NiCoP、NiCoB、NiWB、 NiMoB、c〇WB、CoMoB、CoV、NiV、CoFeV、NiFeV、 NiCoV、NiCoFeV及NiCo組成之群；及一第二金屬或合金 層’其選自由 Ru、Re、pt、Pd、Rh、Os、NiPd、CoPd、 Pb、Sn、Sb及In組成之群。 13. 14. 15. 16. 17. 如请求項1之方法，其中該材料包含 一種藉由如請求項1之方法所獲得之產物。 一種用於製作一圖案化銅結構之方法，其包括在一基板 上提供介電材料，在該介電材料中提供至少一個渠溝/通 遏，在忒至少一個渠溝/通道之底部與側壁上及該至少一 個渠溝/通道附近之該介電材料的水平表面上提供一概 墊； 在該襯塾上該至少一個渠溝/通道中沈積銅；及藉由電 钱刻來遥擇性㈣該銅以使該銅相對於該介電材料之頂 表面凹陷； 藉由電解電鍍或無電鍍而選擇性沉積一或多種材料於 該Cu上，進_步包括自該介電材料上之水平表面移除該 襯塾、.·！而補性種晶（seeding)該銅且隨後藉由無電鑛在 該種晶(seeding)上電鍍一封蓋層。 如請求項15之方法，豆由兮 电其中该無電鍍之後是金屬或合金之 毯覆式沈積。 如。月求項16之方法，其中該毯覆式沈積之後是平坦化。 94117-981123.doc 丄8，一種用於製作一（f|垒儿h 圖案化銅結構之方法，其包括在一基板 上提供介電材料；為q A A 卄在叇介電材料中提供至少一個渠溝/通 道； 在至少-個渠溝/通道之底部與側壁上及該至少一個渠 L C附近之5玄介電材料的水平表面上提供一襯墊； 在β襯塾上該至少—個渠溝/通道中沈積銅以填充該至 少一個渠溝/通道；及 在該銅上選擇性電鍍金屬或合金，及 經由一用於該選擇性電鍍之喷嘴來施加該等金屬或合 金且”亥喷令係直彳空小於該基板之直徑的圓形，以在該 毛鍍過私中減少總電流，且其中在大體上恒定的電流條 件下執行該電鍍。 19·如W求項18之方法，其中該等金屬或合金選自Co、CoP、 CoWP、CoMoP ' Ni、NiP、NiWP、NiMoP、NiW、NiMo、 CoMo、NiFe、CoFe、NiFeP、CoFeP、NiB、CoB、NiFeB、 CoFeB、NiCo、NiCoP、NiCoB、NiWB、NiMoB ' CoWB、 CoMoB、CoV、NiV ' CoFeV、NiFeV、NiCoV、NiCoFeV、 N1C0、Ru、Re、pt、pd、Rh、〇s、Nipd、c〇pd、pb、Sn、 Sb及In之群。 20. 如請求項18之方法，其進一步包括該電鍍之後用於自該 介電材料之該等水平表面移除襯墊的平坦化。 21. 如請求項18之方法，其中該選擇性電鍍之後是金屬或合 金之該毯覆式沈積。 22. 如請求項21之方法，其進一步包括該毯覆式沈積之後的 94117-981123.doc 1326479 平坦化。 23·如請求項18之方法，其中該等金屬或合金包含一第一金 屬或合金層，其選自由Co、CoP、CoWP、CoMoP、Ni、 NiP、NiWP、NiMoP、NiW、NiMo、CoMo、NiFe、CoFe、 NiFeP、NiB、CoB、NiFeB、CoFeB、NiCo、NiCoP、NiCoB、 NiWB、NiMoB、CoWB、CoMoB、CoV、NiV、CoFeV、 NiFeV、NiCoV、NiCoFeV及NiCo組成之群；及一第二金 屬或合金層’其選自由Ru、Re、pt、Pd、Rh、Os、NiPd、 CoPd、Pb、Sn、Sb及In組成之群。 24·如請求項18之方法，其中該金屬或合金包含Rw 25. —種藉由如請求項18之方法所獲得之產物。 26. —種包括一基板之圖案化銅結構，在該基板上具有介電 材料，其中該介電材料於其中含有至少一個渠溝/通道； 一位於該至少一個渠溝/通道之底部及側壁上的襯墊； 位於該至少一個渠溝/通道中該襯墊上的銅丨及 一封蓋結構，其位於該銅上且包括一含有 銖、餓及铑組成之群之至少一項的層。 、、 27. 如凊求項26之銅結構，其中該銅相對於該介電材料之上 表面凹陷。 之銅結構，其中-含有⑽之層直接位於t 銅與该含有選自由釕、鍊、餓及錢組成 的層之間且置於該銅上。 29·如請求項28之銅結構1中該含有对之層相 材料之上表面係平的或凹陷的。 、~丨与 94ΙΠ-98】丨 23.doc 1326479 3〇.如請求項26之銅結構，其中—含有c〇wp之層直接位於該 鋼與該含有選自由釕、銖' 锇及铑組成之群之至少一項 的層之間且置於該銅上。 31·如請求項26之銅結構，其進一步包括一位於該含釕層上 之介電材料層。 32. 如請求項30之銅結構，其進一步包括一位於含有選自由 釕、銖、餓及铑組成之群之至少一項的該層上之介電材 料層。 33. 種包括一基板之圖案化銅結構，在該基板上具有介電 材料，其中該介電材料於其中含有至少一個渠溝/通道； 一位於該至少一個渠溝/通道之底部及側壁上的襯墊； 位於該至少一個渠溝/通道中該襯墊上的銅；及 一封盍結構’其直接位於該銅上且包括選自由Co、 CoP、CoWP、CoMoP、Ni、NiP、NiWP、NiMoP、NiW、 NiMo、CoMo、NiFe、CoFe、NiFeP、NiB、CoB、NiFeB、 CoFeB、NiCo、NiCoP、NiCoB、NiWB、NiMoB、CoWB、 CoMoB、CoV、NiV、CoFeV、NiFeV、NiCoV、NiCoFeV 及NiCo組成之群的一第一金屬或合金層；及 選自由 Ru、Re、Pt、Pd、Rh、Os、NiPd、CoPd、Pb、 Sn、Sb及In組成之群的一第二金屬或合金層。 34. 如請求項33之銅結構，其中該銅相對於該介電材料之上 表面凹陷。 35. 如請求項34之銅結構，其中該第二金屬或合金層相對於 該介電材料之上表面係平的或凹陷的。 94J17-981123.doc -6 - 1326479 36.如請求項33之銅結構，其中進一步包括一位於該第二金 屬或合金層上之介電材料層。 94117-981I23.doc V,1326479 第093119947號專利申請案 中文圖式替換頁(96年11月） 圖5A 電鍍
Z-範圍：35nm RMS: 3.3nm 4伏特 5B -5.00 2.50 6伏特 晒嶋 I» 5.00 •2.50 2.5 5.00^m Z-範圍：33nm RMS: 3.6nm
2.5 5.0JJm Z-範圍：64nm RMS: 4.9nm 圖5C 94117-ilg-961130.doc 1326479 第093119947號專利申請案 中文圖式替換頁(96年11月）
94117-fig-961130.doc 1326479 第093119947號專利申請案 中文圖式替換頁(96年11月）
圖7 94H7-fig-961130.doc 1326479 第093119947號專利申請案 中文圖式替換頁(96年11月）
局域電化電池
1 η ίΊ γ ,,jWti
V 圖9C 94117-fig-961130.doc -10-
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US20050001325A1 (en) 2005-01-06

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