TWI323041B - - Google Patents

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Publication number
TWI323041B
TWI323041B TW093117111A TW93117111A TWI323041B TW I323041 B TWI323041 B TW I323041B TW 093117111 A TW093117111 A TW 093117111A TW 93117111 A TW93117111 A TW 93117111A TW I323041 B TWI323041 B TW I323041B
Authority
TW
Taiwan
Prior art keywords
bonding
metal layer
layer
semiconductor
convex portion
Prior art date
Application number
TW093117111A
Other languages
English (en)
Chinese (zh)
Other versions
TW200505060A (en
Original Assignee
Shinetsu Handotai Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinetsu Handotai Kk filed Critical Shinetsu Handotai Kk
Publication of TW200505060A publication Critical patent/TW200505060A/zh
Application granted granted Critical
Publication of TWI323041B publication Critical patent/TWI323041B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0093Wafer bonding; Removal of the growth substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Led Devices (AREA)
  • Die Bonding (AREA)
TW093117111A 2003-07-24 2004-06-15 Semiconductor-pasted bonding body and its manufacturing method, light-emitting device and its manufacturing method TW200505060A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003201005A JP4114566B2 (ja) 2003-07-24 2003-07-24 半導体貼り合わせ結合体及びその製造方法、並びに発光素子及びその製造方法

Publications (2)

Publication Number Publication Date
TW200505060A TW200505060A (en) 2005-02-01
TWI323041B true TWI323041B (ja) 2010-04-01

Family

ID=34100470

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093117111A TW200505060A (en) 2003-07-24 2004-06-15 Semiconductor-pasted bonding body and its manufacturing method, light-emitting device and its manufacturing method

Country Status (3)

Country Link
JP (1) JP4114566B2 (ja)
TW (1) TW200505060A (ja)
WO (1) WO2005010957A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102709204A (zh) * 2012-05-30 2012-10-03 杭州士兰明芯科技有限公司 一种led芯片的键合方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5041653B2 (ja) * 2004-04-21 2012-10-03 シャープ株式会社 窒化物半導体発光素子およびその製造方法
JP4933130B2 (ja) * 2006-02-16 2012-05-16 昭和電工株式会社 GaN系半導体発光素子およびその製造方法
JP5123573B2 (ja) * 2007-06-13 2013-01-23 ローム株式会社 半導体発光素子およびその製造方法
JP2010192701A (ja) * 2009-02-18 2010-09-02 Showa Denko Kk 発光ダイオード、発光ダイオードランプ及び発光ダイオードの製造方法
JP6058897B2 (ja) * 2012-02-21 2017-01-11 スタンレー電気株式会社 半導体素子の製造方法
US9887155B2 (en) 2012-09-28 2018-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple metal layer semiconductor device and low temperature stacking method of fabricating the same
JP5396526B2 (ja) * 2012-10-23 2014-01-22 ローム株式会社 半導体発光素子

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06314644A (ja) * 1993-04-30 1994-11-08 Canon Inc シリコン基板、シリコン基板のアライメント方法及びそれを適用した記録再生装置
JPH11186120A (ja) * 1997-12-24 1999-07-09 Canon Inc 同種あるいは異種材料基板間の密着接合法
JP2002185080A (ja) * 2000-12-15 2002-06-28 Fujitsu Ltd 半導体装置及びその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102709204A (zh) * 2012-05-30 2012-10-03 杭州士兰明芯科技有限公司 一种led芯片的键合方法
CN102709204B (zh) * 2012-05-30 2015-01-21 杭州士兰明芯科技有限公司 一种led芯片的键合方法

Also Published As

Publication number Publication date
TW200505060A (en) 2005-02-01
JP4114566B2 (ja) 2008-07-09
WO2005010957A1 (ja) 2005-02-03
JP2005044887A (ja) 2005-02-17

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees