TWI316720B - Apparatus and method for controlling on die termination - Google Patents

Apparatus and method for controlling on die termination Download PDF

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Publication number
TWI316720B
TWI316720B TW095136280A TW95136280A TWI316720B TW I316720 B TWI316720 B TW I316720B TW 095136280 A TW095136280 A TW 095136280A TW 95136280 A TW95136280 A TW 95136280A TW I316720 B TWI316720 B TW I316720B
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TW
Taiwan
Prior art keywords
signal
code
dll
unit
external
Prior art date
Application number
TW095136280A
Other languages
English (en)
Chinese (zh)
Other versions
TW200721195A (en
Inventor
Kyung-Hoon Kim
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200721195A publication Critical patent/TW200721195A/zh
Application granted granted Critical
Publication of TWI316720B publication Critical patent/TWI316720B/zh

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Dram (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)
  • Logic Circuits (AREA)
TW095136280A 2005-09-29 2006-09-29 Apparatus and method for controlling on die termination TWI316720B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR20050090953 2005-09-29
KR1020060049027A KR100761359B1 (ko) 2005-09-29 2006-05-30 온-다이 터미네이션 제어회로 및 방법

Publications (2)

Publication Number Publication Date
TW200721195A TW200721195A (en) 2007-06-01
TWI316720B true TWI316720B (en) 2009-11-01

Family

ID=37959477

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095136280A TWI316720B (en) 2005-09-29 2006-09-29 Apparatus and method for controlling on die termination

Country Status (3)

Country Link
KR (1) KR100761359B1 (ko)
CN (1) CN1941629B (ko)
TW (1) TWI316720B (ko)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100929846B1 (ko) 2007-10-23 2009-12-04 주식회사 하이닉스반도체 온 다이 터미네이션 제어 회로
KR100921832B1 (ko) 2008-03-03 2009-10-16 주식회사 하이닉스반도체 반도체 메모리장치의 온 다이 터미네이션 제어회로
KR100929833B1 (ko) 2008-04-02 2009-12-07 주식회사 하이닉스반도체 출력 인에이블 신호 생성 회로와 생성 방법
KR100949276B1 (ko) * 2008-09-08 2010-03-25 주식회사 하이닉스반도체 터미네이션 조절회로 및 이를 포함하는 반도체 메모리장치
KR101043722B1 (ko) 2010-02-04 2011-06-27 주식회사 하이닉스반도체 레이턴시 제어회로 및 이를 포함하는 반도체 메모리장치
US10153014B1 (en) * 2017-08-17 2018-12-11 Micron Technology, Inc. DQS-offset and read-RTT-disable edge control
CN113808634B (zh) * 2020-06-11 2024-02-27 华邦电子股份有限公司 延迟锁相回路装置及其更新方法
CN115599196A (zh) * 2021-07-09 2023-01-13 长鑫存储技术有限公司（Cn） 使能控制电路以及半导体存储器

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100468728B1 (ko) * 2002-04-19 2005-01-29 삼성전자주식회사 반도체 집적회로의 온-칩 터미네이터, 그 제어 회로 및 그제어 방법
KR100502408B1 (ko) * 2002-06-21 2005-07-19 삼성전자주식회사 액티브 터미네이션을 내장한 메모리 장치의 파워-업시퀀스를 제어하는 메모리 시스템과 그 파워-업 및 초기화방법
KR100464437B1 (ko) * 2002-11-20 2004-12-31 삼성전자주식회사 온칩 ｄｃ 전류 소모를 최소화할 수 있는 ｏｄｔ 회로와ｏｄｔ 방법 및 이를 구비하는 메모리장치를 채용하는메모리 시스템
KR100506976B1 (ko) * 2003-01-03 2005-08-09 삼성전자주식회사 온다이 터미네이션 회로를 가지는 동기 반도체 메모리 장치
KR100528164B1 (ko) * 2004-02-13 2005-11-15 주식회사 하이닉스반도체 반도체 기억 소자에서의 온 다이 터미네이션 모드 전환회로 및 그 방법
KR100670674B1 (ko) * 2005-06-30 2007-01-17 주식회사 하이닉스반도체 반도체 메모리 장치

Also Published As

Publication number Publication date
KR100761359B1 (ko) 2007-09-27
CN1941629B (zh) 2010-05-12
TW200721195A (en) 2007-06-01
KR20070036635A (ko) 2007-04-03
CN1941629A (zh) 2007-04-04

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