TWI310212B - Substrate assembly for stressed systems - Google Patents

Substrate assembly for stressed systems Download PDF

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TWI310212B
TWI310212B TW093120670A TW93120670A TWI310212B TW I310212 B TWI310212 B TW I310212B TW 093120670 A TW093120670 A TW 093120670A TW 93120670 A TW93120670 A TW 93120670A TW I310212 B TWI310212 B TW I310212B
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substrate
thermal expansion
coefficient
substrates
film
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TW200509217A (en
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Fabrice Letertre
Bruno Ghyselen
Olivier Rayssac
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Soitec Silicon On Insulator
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/86—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS

Description

I310212 九、發明說明： 【發明所屬之技術領域】 本發明係關於基材的領域，更具體而言係關於用於微電 子技術或光電子技術之基材，諸如矽或碳化梦基材。 【先前技術】 在該領域中，基材通常必須裝配在一起。然而，此基材 不必具有相同的性質，具體而言係熱性質。當該裝配接受 溫度上升和/或下降階段，有時超過1000t數量級的幅度 時’從而出現了關於拉伸和壓縮二者應力的問題。 該等基材之一和/或另一個在該等應力的作用下會被損 壞（例如裂紋的出現），或者它可能完全被毁壞。 此裝配之實例係GaAs(砷化鎵）_Si、藍寶石_矽、鍺·矽 (Si-Ge)、矽-石英或氮化鎵（GaN)_石夕。 該等基材之一本身可能係一多層的裝配，或者它也可能 係僅一層或一薄膜。 因此，在將具有不同熱膨脹係數的兩個基材、或一基材 與一層、成一某姑I — .
問題。 且該裝配接受超 度偏移時，造成 【發明内容】
基材中。 94606.doc 1310212 在忒等面之一和/或另叫固中產生的該等花紋對製造其 之基材在平行於該等裝配面的平面中提供彈性。 八 时此類型的結構從而使用了可吸收在該裝配介面産生的熱 彈性應力的機械構件或機械系統（例如藉由㈣或^ 紋來獲得）。 战两個基材然後可 10%的熱膨脹係數。 至於實例，該等基材之一可以由矽、石英、藍寶石、碳 化石夕或玻璃形成，且另-個可以由坤化鎵、藍寶石、石夕錯 (slGe)、磷化鈿、氮化鋁或碳化矽形成。 該第-基材可為由一或多個薄層組成的薄膜的形式，每 :薄層具有例如(U微米(㈣至2 _範圍内的厚度。具體而 。"亥第-基材可為一薄膜或一薄層以便與該第二基材形 成。裝配，該震配可用作一用於藉由異質蟲晶形成層的裝 置從而，在該第二基材中形成的花紋可吸收在異質Μ 沈積時産生的熱彈性或機械應力。 該結構可為具有-矽層、-氧化物層或絕緣體層和一基 材的SOI型。 本發明也提供—種裝配分別具有第一與第〜 2第二基材的方法，其t在該第二基材中製造花紋。i 化紋係彈性的或撓性的’或對製造其之基材在平行於1 等裝配面的平面中提供彈性。 該兩個裝配在_ 的步驟；該等蝕刻 起的基材組可以進行溫度上升然後下降 的花紋可以吸收溫度上升或下降時産生 94606.doc 1310212 的機械應力。 本發明還提供-種製造由—基材上的第―材料形成的薄 臈的方法，其中該基材由第二材料形成，該方法包括： 如上所述，將第一材料構成的第一基材與第二材料構成 的第二基材裝配在一起； -使該等基材之一的一部分分離或斷裂以便在另一基材 上留下薄膜。 【實施方式】 以下將參照圖1A描述本發明的一個態樣。 其係關於將兩個基材40、42裝配在一起，該兩個基材可 、/、有不同的熱私脹係數CQ與C2，例如一石英基材（膨脹係 數5xl〇-7k-i)或AsGa(膨脹係數6xl〇_6k_1}和—矽基材⑽脹係 數 2.5\1〇-6]^)。 鍺（膨脹係數όχΙΟ-Ι-1)、鋁氧（Al2〇3，膨脹係數7><1〇-6]^1) 和碳化矽SiC(膨脹係數係其他可能材料的實 例0 基材40與42之間的熱膨脹係數差異（實際上，係相對差異 lc〇-qi/CG或iCo-cy/c：2)較佳為在環境溫度（大約20°c或25 C )測疋.其在環境溫度為至少丨〇%、或至少2〇%至。 母—基材40、42都可為幾百μηι數量級的厚度，例如在厚 度1 〇〇 μιη至1毫米（mm)的範圍内。 然而’如下所述，基材可以爲一或多個薄層的形式，每 一薄層具有例如〇· 1 μιη至2 μιη範圍内的厚度。此裝配可用 作用於藉由異質磊晶形成層的裝置。 94606.doc 1310212 本發明的此態樣不僅關於諸如上面所描述的基材_基材或 基材上單層系統，還關於任何涉及在基材上沈積層的多層 系統。 圖3B中所示的結構可被有利地用作一用於藉由異質磊晶 形成層的基材。實際上，由於在該基材82中姓刻花紋或溝 槽，所以在該薄膜8 5上形成一異質磊晶層時産生的熱彈性 應力被吸收。由於該等花紋對該基材82提供之彈性或撓 性，相較於不具有此花紋的基材比，在生長時或在冷卻時 可使由於該基材與該異質磊晶層的熱膨脹係數的差異而出 現的缺陷最小。 關於此點，該薄膜85可用作晶種層，以用於生長較大範 圍的熱膨脹係數之異質累晶層。該裝配的結構，即具有該 薄膜85的基材82，可以用於生長異質磊晶層，諸如、 AIN、InN或 SiC層。 例如，該基材82可為矽基材而該薄膜85係薄單晶碳化矽 層，從該薄膜85中可形成一異質磊晶單晶層。按照另一實 例’ 5玄薄膜85可為用作晶種層的GaN層，以在si基材上進行 GaN層的異質磊晶生長。 如上所述，在該基材82中形成的該等花紋或溝槽可以從 該表面蝕刻形成，在該表面上，如圖3B中所示，或從相對 表面（參見圖4A)黏接該薄膜85。 該薄膜85以及隨後形成於其上的層可以具有〇 1 至2 μπι範圍内的厚度。 δ亥方法的一變化示於圖4 Α和4Β中。與圖3Α中所干才 丁相同之 94606.doc -13- 1310212 參考號碼，除了加10，表示相似的或相應的元件。在該基 材90中製造一蝕刻的花紋結構而意圖在該第二基材92上産 生薄層95。 用於製備薄弱平面和裝配該兩個基材的技術與上述關於 圖3A和3B所描述的技術相同。 與圖3B相反，在最後的結構中（圖4B)未出現該等花紋。 然後該板或該基材90可以再利用，例如將一新的薄膜轉移 到另一基材上。 其表示對於數個轉移操作僅需要進行一個花紋蝕刻操 作。 【圖式簡單說明】 圖1A、IB、1C和2示出本發明的實施例；
圖3A和3B以及4A和4B示出一某姑齡刭κ , M 土材斷裂技術的兩個變化 中的步驟。 【主要元件符號說明】 40 基材 41 裝配表面 42 基材 43 裝配表面 45 彈性供應層 47 背部表面 48 溝槽 49 彈性供應層 51 割紋 94606.doc -14- 1310212 80 基材 81 裝配表面 82 基材 83 裝配表面 84 上部區域 85 薄膜 87 薄弱的平面 90 基材 91 裝配表面 92 第二基材 93 裝配表面 94 彈性供應層 95 薄層 97 薄弱的平面 94606.doc -15-

Claims (1)

  1. 思ss^5™卜卿細_ 十、申請專利範圍： 1·-種由—薄膜與一基材(85、82)裝配而成的結構，該薄膜與 s亥基材分別具有第一熱膨脹係數與不同於該第一熱膨脹 係數的第二熱膨脹係數，且分別具有第一與第二裝配面 (81、83) ’其中花紋係從該裝配面（83)的相反面形成在該 基材（82)中，該等花紋在與該第一與第二裝配面平行的平 面中係彈性的或撓性的’從而形成用於吸收在裝配介面 產生之熱彈性應力的機械系統。 2.如請求们之結構，其十該等花紋爲支柱或溝槽或鑛齒狀 割紋的形式。 L如μ求項1或2之結構’其中該薄臈與該基材具有在環境 溫度相差至少10%的熱膨脹係數。 4 ·如叫求項1或2之結構’盆中兮其#山 # 〃 T a基材由下列材料之一構 成：矽、石英、藍寶石、碳化矽和玻璃。 5·如請求項1或2之結構，苴中哕壤 /、甲该4臈由下列材料之一構 成·石申化鎵、藍寶石、鍺、氣作 来 虱化叙、矽、矽·鍺（SiGe)、 %化銦、氮化鋁和碳化矽。 6·如㈤求項1或2之結構，其中該薄膜 7·如請求項6之結構，其中兮薄層…4層(85)的形式。 範圍内。 層的厚度如陶至的 8. 一種藉由異質磊晶沈積 嘖灰頂叶〇裝置’其中該裳置包括如 «月长員1至7中任一項之結構。 9 - 種在由第二材料形成的美;^ μ制 土材上製造由第_姑牲游士、的 薄膜的方法，其包括： 材枓形成的 94606-95J228.doc 1310212 -將第一與第二基材（80、82)裝配在一起，該第一與第 二基材分別具有第一熱膨脹係數和不同於該第一熱膨脹 係數的第二熱膨脹係數，且分別具有第一與第二裝配面 (8卜83)，其中花紋已形成在該第二基材（82)之裝配面（μ) 的相反面中，該等花紋在與該第一與第二裝配面平行的 平面中係彈性的或撓性的，從而形成用於吸收在裝配介 面產生之熱彈性應力的機械系統， 分離該等基材之一的一部分或使該等基材之_變薄， 以便在另一基材上留下一薄膜（85)。 ίο. 11. 12. 13. 14. 15. 16. 如請求項9之方法，其中該兩個裝配在一起的基材組接受 一溫度上升的步驟。 如請求項9或10之方法，其中該兩個基材係藉由晶圓接合 (wafer bonding)或藉由分子接觸或藉由黏性接合 (adhesive bonding)裝配在一起。 如請求項9或10之方法，其中該第—基材（8〇)包含一薄弱 區（87)。 如請求項9或10之方法，其中該第二基材（8〇)包含一薄弱 區（87)。 如請求項12之方法，其中該薄弱區係藉由形成—多孔層 而産生。 如請求項13之方法，其中該薄弱區係藉由形成—多孔層 而産生。 如請求項12之方法，其中該薄弱區係藉由離子注入而産 生。 生 94606-951228.doc 1310212 17.如請求項13之方法，其中該薄弱區係藉由離子注入而產 生。 1 8.如請求項9之方法，其中將該等基材之一分離或變薄係藉 由抛光或#刻執行。 94606-951228.doc
TW093120670A 2003-07-10 2004-07-09 Substrate assembly for stressed systems TWI310212B (en)

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FR0308447A FR2857502B1 (fr) 2003-07-10 2003-07-10 Substrats pour systemes contraints

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TWI310212B true TWI310212B (en) 2009-05-21

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EP (1) EP1644967A2 (zh)
JP (1) JP4576381B2 (zh)
KR (1) KR100863081B1 (zh)
CN (1) CN1816897B (zh)
FR (1) FR2857502B1 (zh)
TW (1) TWI310212B (zh)
WO (1) WO2005006419A2 (zh)

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CN1816897B (zh) 2010-06-23
KR100863081B1 (ko) 2008-10-13
TW200509217A (en) 2005-03-01
KR20060034685A (ko) 2006-04-24
US7279779B2 (en) 2007-10-09
EP1644967A2 (en) 2006-04-12
US20060192269A1 (en) 2006-08-31
JP2007527108A (ja) 2007-09-20
FR2857502B1 (fr) 2006-02-24
JP4576381B2 (ja) 2010-11-04
FR2857502A1 (fr) 2005-01-14
CN1816897A (zh) 2006-08-09

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