TWI309447B - - Google Patents

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TWI309447B
TWI309447B TW95130304A TW95130304A TWI309447B TW I309447 B TWI309447 B TW I309447B TW 95130304 A TW95130304 A TW 95130304A TW 95130304 A TW95130304 A TW 95130304A TW I309447 B TWI309447 B TW I309447B
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Taiwan
Prior art keywords
semiconductor wafer
region
tray
wafer
base portion
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TW95130304A
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Chinese (zh)
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TW200719424A (en
Inventor
Akiko Kamigori
Masami Yakabe
Takanori Hyakudomi
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Tokyo Electron Ltd
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Publication of TWI309447B publication Critical patent/TWI309447B/zh

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6838Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping with gripping and holding devices using a vacuum; Bernoulli devices

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Description

1309447 • 九、發明說明: 【發明所屬之技術領域】 , 本發明係關於半導體晶圓用搬運托盤,特別係關於搬運 * 成 1 被】構 4 體,例如 MEMS(Micro Electro Mechanical1309447 • IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a carrier tray for a semiconductor wafer, and particularly relates to a carrier, such as a MEMS (Micro Electro Mechanical)

Systems ·微電機系統)之半導體晶圓之半導體晶圓用搬運 •托盤。 - 【先前技術】 籲 近年來,利用半導體微細加工技術等將機械電子. 光化學等多種功能聚集之裝置之MEMS特別備受注目。 作為以往實用化之MEMS技術,例如作為汽車.醫療用之 各種感應器’已逐漸在作為微感應器之加速度感應器及 壓力感應器、氣流感應器等搭載MEMS裝置。又,在噴 . 墨印表機噴頭採用該MEMS技術時,可達成喷出墨水之 喷嘴數之增加與正確之墨水喷出,可謀求晝質之提高與 印刷速度之高速化。另外,使用於反射型投影機之微反 _ &鏡陣列等也屬於已知之-般的MEMS裝置。 又,今後,透過利用MEMS技術之各式各樣之感應器 及致動器之開發,預期可拓展對光通信.移動式機器之應 用、對電腦之周if斗幾器之應用U &對生物分析及攜帶用 電源之應用。在技術調查報告第3期(曰本經濟產業省產 業技術%境局技術調查室製造產業局產業機械課發行 2〇03年3月28日)中,曾以有關MEMS之技術現狀與課題 為議題介紹種種MEMs技術。 另方面,MEMS裝置因係微細之構造體,故其搬運 112514.doc 1309447 機構也變得愈來愈重要。尤 ^ 尤其在晶圓上成型具有可動 露^動崎置之狀態下,由於係在封裝之前,故屬於 =可動部等之狀態,為防止對所希望之袋置特性造成 衫曰,在搬運之際也有充分加以注意之必要。 [非專利文獻1]技術調查報告第3期(曰本經濟產業省產 業技術環境局技術調查室努 八 1每產業局產業機械課發行 2003年3月28曰) [發明所欲解決之問題] 一般’在搬運半導體晶圓之際,通常利用以真空吸附 吸附半導體晶ϋ而搬運之方式,但在細⑽裝置之構造 中’有難以採用該方式之情形。 例如,在成型於半導體晶圓之_廳裝置中,設有形 成可動部用之貫通區域之情形,有可能不能藉該貫通區 域^丁真工吸附。又’在具有薄膜之隔膜構造之腿刚 裝置中,真空吸附成為可動部之隔膜構造之情形,由於 需藉真空吸附吸附成為可動部之薄膜之隔膜構造,故吸 附力強時,薄膜部分有被破壞之可能性。 因此,特別在細⑽裝置之情形,在藉真空吸附搬運 半導體晶圓之際,最好利用搬運半導體晶圓用之搬運托 盤穩定地加以搬運。 本發明係為解決如上述之問題而設計者,其目的在於 提供可穩定地搬運成型有他⑽裝置之半導體晶圓之半 導體晶圓用搬運托盤。 【發明内容】 1125I4.doc 9¾^¾130304號專利申請案 ------ 文4明書替換頁(98年1月)W月,日修(更)正替換頁 本發明之半導體晶、用搬遂私金係載置I至少成型】個 具有可動部之微小構造體之半導體晶圓者,且包含:基 底°卩,其係在載置半導體晶圓之表面側設有防止半導體 曰曰圓之偏移用之偏移防止機構,在搬運之際背面側被真 X·吸附者。基底部具有設在未成型半導體晶圓之微小構 造體之周邊區域之貫通部。半導體晶圓係經由貫通部而 與基底部一起被真空吸附。 最好半導體晶圓具有孔部。進一步包含保持突起部, 其係设於基底部之表面側,構成偏移防止機構並嵌合於 孔部者。 尤其是孔部設於未成型微小構造體之區域。 尤其是半導體晶圓具有複數之孔部。基底部進一步包 含.複數之保持突起部,其係分別對應於複數之孔部而 被設置者。 尤其是孔部及保持突起部之形狀剖面形成多角形狀。 最好基底部之表面側具有特定深度之柱坑區域,其係 對向於比未成型微小構造體之半導體晶圓之周邊區域更 内側之區域而被設置,藉柱坑加工形成凹型。 尤其是形成於基底部之表面侧之枉坑區域係對向於位 在半導體晶圓中成型有微小構造體之可動部之區域而被 設置。 尤其是半導體晶圓至少成型1個具有設有成為可動區 域之貝通區域之可動部之微小構造體,孔部係藉形成貫 通區域之步驟同時被成型。 1125141-980115.doc 1309447 ::半導體晶圓用搬運托編、於半導體晶圓而大於 形成4小構造體之區域。 最好半㈣晶圓用搬運托盤係沿著執行真空吸附用之 真空吸附導件之形狀而被真空吸附。基底部之背面旦有 對應於真空吸附導件而設置之凹部,以擴大在直空吸附 導件與背面間被真空吸附之吸附面積。 最好進-步包含外壁部,其係與基底部連結,構成在 載置丰導體晶圓之面沿著半導體晶圓之外周端部之至少 一部分區域設置之偏移防止機構者。 尤其是基底部之表面側具有特定深度之柱坑區域,其 係對向於比未成型微小構造體之半導體晶圓之周邊區域 更内側之區域而被設置,藉柱坑加工形成凹型。 尤其疋形成於基底部之表面側之柱坑區域係對向於位 在半導體晶圓中成型有微小構造體之可動部之區域而被 設置。 尤其疋半導體晶圓具有定向平面(〇rientati〇n 或缺 口(notch)區域; 外壁σ卩係對應於半導體晶圓之定向平面或缺口區域之 外周端部之至少一部分而被設置。 本發明之另一半導體晶圓用搬運托盤係载置至少成型 1個具有可動部之微小構造體之半導體晶圓者;半導體晶 圓係與設在與半導體晶圓用搬運托盤之間之玻璃基板接 合’並介隔玻璃基板被搬運。半導體晶圓用搬運托盤包 含基底部’其係在載置介隔玻璃基板之半導體晶圓之表 112514.doc 13 05¾¾¾30304號專利申請案 厂^--------- 中文説明書替換頁(98年1月)汾年/月相修(更)正替換頁 ' ιϊτΐ -i*A» -ir* 一 — J又有夕孔質層,在搬運之際背面側被真空吸附者。 土底邛具有達到多孔質層之貫通孔。半導體晶圓係經由 多孔質層而與基底部一起被真空吸附。 最好半導體晶圓用搬運托盤係在載置半導體晶圓之表 面側設置防止半導體晶圓之偏移之偏移防止機構。 最好半導體晶圓及玻璃基板具有孔部。基底部具有保 持突起部’其係構成偏移防止機構並嵌合於孔部者。 尤其疋孔部設於未成型微小構造體之區域。 尤其是半導體晶圓及玻璃基板具有複數之孔部。基底 部具有複數之保持突起部,其係分別對應於複數之孔部 而被設置者。 尤其是孔部及保持突起部之形狀剖面形成多角形狀。 尤其是半導體晶圓至少成型1個具有設有成為可動區 域之貫通區域之可動部之微小構造體,孔部係藉形成貫 通區域之步驟同時被形成。Systems · Micromotor Systems) Semiconductor wafers for semiconductor wafer handling • Pallets. - [Prior Art] In recent years, MEMS, which is a device that integrates various functions such as mechatronics and photochemistry, such as semiconductor microfabrication technology, has attracted attention. As a conventional MEMS technology, for example, various sensors for automobiles and medical applications have been gradually equipped with MEMS devices as acceleration sensors, pressure sensors, and air flow sensors of micro sensors. Further, when the MEMS technology is used for the ink jet printer head, the number of nozzles for ejecting ink and the correct ink ejection can be achieved, and the quality of the enamel can be improved and the printing speed can be increased. In addition, a micro-reflex _ & mirror array used in a reflective projector is also known as a MEMS device. In the future, through the development of various sensors and actuators using MEMS technology, it is expected to expand the application of optical communication, mobile applications, and the application of computer peripherals. Bioanalytical and portable power applications. In the third issue of the technical investigation report (Sakamoto Ministry of Economy, Trade and Industry, Industrial Technology, Industrial Technology, Industrial Technology, Manufacturing Industry Bureau, Industrial Machinery Division, March 28, 2003), the status quo and issues related to MEMS technology were discussed. Introduce various MEMs technologies. On the other hand, MEMS devices are becoming more and more important because of their fine structure. In particular, in the state in which the movable molding is performed on the wafer, it is in a state of being = movable portion or the like before being packaged, and in order to prevent the occurrence of the desired bag characteristics, the handling is carried out. There is also a need to pay sufficient attention to it. [Non-Patent Document 1] Technical Investigation Report No. 3 (Sumamoto Ministry of Economy, Trade and Industry, Industrial Technology and Environment Bureau, Technical Laboratory, No. 8, Industrial Machinery Division, Industrial Bureau, Issued March 28, 2003) [Invented Problem to be Solved] Generally, when a semiconductor wafer is transported, it is usually transported by vacuum adsorption of a semiconductor wafer, but in the structure of a thin (10) device, it is difficult to adopt this method. For example, in the case where the semiconductor wafer is formed in the semiconductor wafer, a through region for forming the movable portion is provided, and there is a possibility that the through region cannot be absorbed by the through region. Further, in the leg-rigid device having a membrane-structured membrane structure, vacuum adsorption becomes a diaphragm structure of the movable portion, and since the membrane structure of the movable portion is required by vacuum adsorption adsorption, when the adsorption force is strong, the film portion is partially The possibility of destruction. Therefore, particularly in the case of the thin (10) device, it is preferable to carry the semiconductor wafer by vacuum transfer, and it is preferable to carry it stably by the transport tray for transporting the semiconductor wafer. The present invention has been made to solve the above problems, and an object of the invention is to provide a transfer tray for a semiconductor wafer which can stably convey a semiconductor wafer on which the device (10) is formed. [Description of the Invention] Patent application No. 1125I4.doc 93⁄4^3⁄4130304 ------ Wen 4 replacement page (January 98) W month, Japanese repair (more) is replacing the semiconductor crystal of the present invention A semiconductor wafer in which at least one of the microstructures having a movable portion is formed, and includes a substrate, which is provided with a semiconductor chip on the surface side on which the semiconductor wafer is placed. The offset prevention mechanism for the offset is a true X·adsorber on the back side of the conveyance. The base portion has a through portion provided in a peripheral region of the microstructure of the unmolded semiconductor wafer. The semiconductor wafer is vacuum-adsorbed together with the base portion via the through portion. Preferably, the semiconductor wafer has a hole portion. Further, the holding projection portion is provided on the surface side of the base portion to constitute an offset preventing mechanism and is fitted to the hole portion. In particular, the hole portion is provided in a region where the microstructure is not formed. In particular, semiconductor wafers have a plurality of holes. The base portion further includes a plurality of retaining projections which are respectively provided corresponding to the plurality of holes. In particular, the shape cross section of the hole portion and the holding projection portion has a polygonal shape. Preferably, the surface side of the base portion has a pit region of a specific depth which is disposed opposite to a region on the inner side of the peripheral region of the semiconductor wafer in which the microstructure is not formed, and is formed into a concave shape by column pit processing. In particular, the pit region formed on the surface side of the base portion is provided in a region facing the movable portion in which the minute structure is formed in the semiconductor wafer. In particular, at least one semiconductor structure is formed with a minute structure having a movable portion which is a beton region which is a movable region, and the hole portion is simultaneously molded by the step of forming a through region. 1125141-980115.doc 1309447: The semiconductor wafer is transported on the semiconductor wafer and larger than the area where the four small structures are formed. It is preferable that the half (four) wafer transfer tray is vacuum-adsorbed along the shape of the vacuum suction guide for performing vacuum suction. The back surface of the base has a recess corresponding to the vacuum suction guide to expand the suction area which is vacuum-adsorbed between the direct adsorption guide and the back surface. Preferably, the step further includes an outer wall portion that is coupled to the base portion to form an offset preventing mechanism provided on at least a portion of the outer peripheral end portion of the semiconductor wafer on the surface on which the conductor wafer is placed. In particular, a pit region having a specific depth on the surface side of the base portion is provided to face a region further inside than a peripheral region of the semiconductor wafer in which the microstructure is not formed, and is formed into a concave shape by column pit processing. In particular, the pillar region formed on the surface side of the base portion is provided in a region facing the movable portion in which the minute structure is formed in the semiconductor wafer. In particular, the semiconductor wafer has an orientation flat (notch) region; the outer wall σ卩 is provided corresponding to at least a portion of the outer circumferential end portion of the semiconductor wafer or the outer peripheral portion of the notched region. A semiconductor wafer transfer tray is mounted on a semiconductor wafer in which at least one microstructure having a movable portion is formed; and a semiconductor wafer is bonded to a glass substrate provided between the transfer tray and the semiconductor wafer. The glass substrate is transported. The semiconductor wafer transfer tray includes a base portion 'which is attached to the semiconductor wafer on which the glass substrate is placed. 112514.doc 13 053⁄43⁄43⁄430304 Patent Application Factory ^-------- - Chinese manual replacement page (January 98) 汾年/月相修 (more) is replacing page ' ϊ ϊ ΐ -i*A» -ir* one - J has a grading layer, on the back side of the handling The bottom enthalpy has a through hole that reaches the porous layer. The semiconductor wafer is vacuum-adsorbed together with the base portion via the porous layer. Preferably, the semiconductor wafer transfer tray is placed on the semiconductor wafer. surface It is preferable to provide an offset preventing mechanism for preventing the offset of the semiconductor wafer. Preferably, the semiconductor wafer and the glass substrate have a hole portion, and the base portion has a holding protrusion portion which constitutes an offset preventing mechanism and is fitted to the hole portion. The hole portion is provided in a region where the microstructure is not formed. In particular, the semiconductor wafer and the glass substrate have a plurality of holes, and the base portion has a plurality of holding protrusions, which are respectively provided corresponding to the plurality of holes. The shape of the hole portion and the holding projection is formed into a polygonal shape. In particular, at least one semiconductor structure is formed with a minute structure having a movable portion that is a through region of the movable region, and the hole portion is formed by the step of forming the through region. Was formed.

最好半導體晶圓用搬運托盤係小於半導體晶圓及玻璃 基板而大於形成微小構造體之區域。 最好進一步包含外壁部,其係與基底部連結,構成在 介隔玻璃基板而載置半導體晶圓之面沿著半導體晶圓及 玻璃基板之外周端部之至少一部分區域設置之偏移防止 機構者。 尤其是半導體晶圓&玻璃基板具有定向+面或缺口區 域。外壁部係對應於半導體晶圓之定向平面或缺口區域 之外周端部之至少一部分而被設置。 1125141-980115.doc -10· 1309447 敢好多孔質層係奈米結晶石夕。 ί發明之效果] :發明之半導體晶圓用搬運托盤係包含:基底部,其 載置半導體晶圓之表面側設有防止半導體晶圓之偏 =用之偏移防止機構,在搬運之際f面側被真空吸附Preferably, the transfer tray for the semiconductor wafer is smaller than the semiconductor wafer and the glass substrate and larger than the region where the microstructure is formed. Preferably, the outer wall portion is further connected to the base portion, and the offset preventing mechanism is provided on at least a part of the outer peripheral end portion of the semiconductor wafer and the glass substrate on the surface on which the semiconductor wafer is placed on the glass substrate. By. In particular, the semiconductor wafer & glass substrate has an orientation + face or a notch region. The outer wall portion is provided corresponding to at least a portion of the outer circumferential end portion of the orientation flat or the notched region of the semiconductor wafer. 1125141-980115.doc -10· 1309447 Dare to make a porous layer of nanocrystalline crystal eve. The effect of the invention is that the transfer tray for a semiconductor wafer according to the invention includes a base portion on which a surface side of the semiconductor wafer is placed, and an offset preventing mechanism for preventing a bias of the semiconductor wafer is provided. The side is vacuum absorbed

圓之:底部由於具有貫通區域,故可-面防止半導體晶 圓之偏移,一面穩定地加以搬運。 又’本發明之半導體晶圓用搬運托盤係介隔多孔質層 t空吸附與半導體晶圓接合之玻璃基板。藉該構成,^ 通區域位於半導體晶圓之情形下,亦可一面防止半 體晶圓之偏移,一面穩定地加以吸附。 【實施方式】 > 乂下’面參照圖式面詳細說明有關本發明之實 ^ 又,在圖中,在同一或相當部分附上同一符號Round: Since the bottom portion has a through region, the surface can be stably transported while preventing the offset of the semiconductor crystal. Further, the semiconductor wafer transfer tray of the present invention is a glass substrate which is bonded to a semiconductor wafer via a porous layer. According to this configuration, in the case where the semiconductor region is located in the semiconductor wafer, it is possible to stably adsorb the semiconductor wafer while preventing the offset of the semiconductor wafer. [Embodiment] > The following is a detailed description of the present invention with reference to the drawings. In the drawings, the same symbol is attached to the same or equivalent parts.

而不重複其說明。 υ (實施型態1) 圖1係本發明之實施型態丨之檢查裝置3〇之說明圖。 ^參照圖1,本發明之實施型態i之檢查裝置3〇之主要部 係由具有搬運作為被檢查體之半導體晶圓(以下又僅稱晶 圓)之搬運臂32之轉子部33、檢查部36及晶圓保持機構 斤構成此清开),配没於轉子部3 3之搬運臂3 2係藉可向 平方向%轉且可向垂直方向移動之多關節之連桿機構 所形成,而構成可將由收容複數片晶圓之匣盒(未圖示) 内取出之晶圓與後述之半導體晶圓用搬運托盤同時搬運Without repeating its description. υ (Embodiment 1) Fig. 1 is an explanatory view of an inspection apparatus 3 of the embodiment of the present invention. Referring to Fig. 1, the main part of the inspection apparatus 3 of the embodiment i of the present invention is a rotor portion 33 having a transfer arm 32 that carries a semiconductor wafer (hereinafter, simply referred to as a wafer) as a test object, and inspection. The portion 36 and the wafer holding mechanism are configured to be opened, and the transfer arm 3 2 that is not attached to the rotor portion 3 is formed by a multi-joint linkage mechanism that can be rotated in the flat direction and can be moved in the vertical direction. The wafer can be transported simultaneously with a wafer for transporting a plurality of wafers (not shown) and a semiconductor wafer transport tray to be described later.

】12514.doc 11 · 1309447 至晶圓保持機構35,並將在檢查部36被檢查後之晶圓再 搬入®盒。 由IE盒被搬運臂32取出之晶圓係被載置於後述之半導 體晶圓用搬運托盤(以下又僅稱為托盤)而與托盤同時被 搬運至晶圓保持機構35之吸盤34。晶圓保持機構35係維 持此狀態而將其搬運至檢查部3 6。而,在檢查部3 6,夢 對準裝置37之位置檢測攝影機38等檢測被搬運之晶圓位 置。依據此被檢測之位置資訊執行對準,以執行使後述 之探針接觸於成型於晶圓之裝置之希望之測試墊用之位 置調整等。 圖2係說明檢查部3 6之概略構成圖。 參照圖2,安裝探針51之探針卡5〇係被連接於測試頭 55 ° 測忒頭55係利用搭載施加至晶圓之檢查用電源及電極 塾之圖案輸出部或將電極塾之輸出取入於測定部用之輸 入邛等之電氣機器(未圖示)之獨立之柱狀體所形成。 曰s圓保持機構35係包含透過可撓性之管路丨7而與吸盤 3 4連接之作為吸附機構之真空泵1 $。 可藉此真工泵18而利用吸盤34真空吸附晶圓及半導體 晶圓用搬運托盤而維持該狀態,以執行檢查。 圖3係本發明之實施型態1之半導體晶圓用搬運托盤之 說明圖。 圖3(a)係本發明之實施型態1之半導體晶圓用搬運托盤 2由上部所見之圖。 112514.doc 1309447 參照圖3 (a),以可覆蓋晶圓!方式而依照該晶圓外徑設 置半導體晶圓用搬運托盤2,並將其形成可保持半導體晶 圓之形狀。在本例中,作為—例,係對應於晶圓外捏而 、”大於此之外徑之晶圓同樣之圓板狀形狀形成半導體 晶圓用搬運托盤2。 圖3(b)係將本發明之實施型以之半導體晶圓用搬運托 盤2切剖時由橫向所見之剖面圖。 如圖3(b)所示,設有載置晶圓之圓才反狀形狀之基底部 2c、及連結於基底部2(:而以固定半導體晶圓之目的形成 凹邛开y狀之外壁部2b。此外壁部2b之内周面係沿著半導 體晶圓之形狀而被設置’並被設計成在載置半導體晶圓 之際可被保持。又,基底部2e/f系對應於半導體晶圓之外 徑而被設置,具有載置半導體晶圓之表面與搬運之際真 空吸附用之背面。 又’此半導體晶圓用搬運托盤可使用水晶(quartz)或聚 醯亞胺樹脂、P臟、陶竟溶膠等工程塑膠、陶变(例如 氧化鋁(Al2〇3)、氮化鋁㈧N)、氧化鍅(Zr〇2)、氧化鋅 办〇)、一氮化硼(BN、PBN))、石英、矽、紹、不銹鋼 等。尤其’在矽、鋁或不銹鋼中,因熱傳導率較高,故 在檢查之際可透過@、銘或不_抑制對半導體晶圓之 衫響’執行尚精度之檢查。 圖4係被搬運臂32搬運至晶圓保持機構%之情形之說 明圖。 圖4⑷係表示圖3所說明之晶圓及載置晶圓之托盤被載 112514.doc -13· 1309447 置於搬運臂32之情形。 圖4(b)係載置於搬運臂32之狀態由上方所見之圖。 如圖4(b)所示,托盤2係被載置於形成在丫字形上之 32a及32b上。 薄 在本例中,作為一例,說明在對此搬運臂32之載置之 際,在拖盤2載置晶圓1之情形。 例如,由存放未圖示之半導體晶圓用搬運托盤之匿盒 (未圖示),利用未圖示之別的搬運臂取出該半導體晶圓 用搬運托盤2而首先載置於此臂32a&32b。 而’為了利用別的搬運臂將由收容複數片晶圓之匿盒 (未圖不)内取出之晶圓收容於托盤2 ,利用對準裝置等執 行對準調整後载置於托盤2。又,作為對準裝置,有利用 攝影機圖像’以圖像處理執行對準調整之方式、及利用 雷射執行對準調整之方式等種種方式,但由於均屬一般 的技術,故不重複其詳細之說明。 而,在將晶圓i載置於托盤2之狀態下,如上所述,將 其搬運至晶圓保持機構35之吸盤34。 圖5係晶圓保持機構35之一部分之說明圖。 如圖5所示,晶圓保持機構3 5係由被沿著γ方向配設之 Y方向導軌43滑動自如地導動之¥台、被沿著正交於設於 此Υσ2Υ方向之方向,即χ方向設置之X方向導軌U滑 動自如地導動之Χ台、及對此X台安裝成可升降(Ζ方向) 及旋轉之吸盤34所構成。此情形,如後所述,吸盤34係 开y成具有吸引用小孔之中空狀,在吸盤之中空部經由 112514.doc • 14 - 1309447 可撓性管路17連接有作為吸附機構之真空泵i8。 圖6係利用真空泵18吸附托盤2之情形之說明圖。 參照圖6,吸盤34具有複數之吸引用小孔3,其上載置 著托盤2。而,藉由起動真空泵18,可使吸盤“之中空部 内成為負壓而吸附保持托盤2。托盤2保持著晶圓卜故可 在此狀態穩定地加以吸附。 在此,作為一例,說明有關成型於晶圓1之作為mems 裝置之3軸加速度感應器。 圖7係3軸加速度感應器由裝置上面所見之圖。 如圖7所示,在形成於晶圓1之晶片τρ之周邊配置有複 數塾PD。而,為對墊傳達電氣信號或由塾傳達電氣信 號,投有金屬布線。而,在中央部配置有形成克羅巴型 之4個重錐體。 圖8係3轴加速度感應器之概略圖。 參照圖8,此3軸加速度感應器屬於壓電電阻型,設有 作為檢測元件之壓電電阻元件作為擴散電阻。此壓電電 阻型之加速度感應器可利用廉價之1C製程,且即使形成 較小之作為檢測元件之電阻元件,其感度也不會降低, 故對小型化.低廉化相當有利。 作為具體的構成,中央之重錐體八尺呈現以4支樑ΒΜ支 持之構造。樑ΒΜ係以在X,γ之2軸方向互相正交之方式 形成每1軸具有4個壓電電阻元件。ζ軸方向檢測用之4個 壓電電阻元件係配置於X軸方向檢測用壓電電阻元件之 側面。重錐體AR之上面形狀係形成克羅巴型,在中央部 H2514.doc 1309447 與樑BM連結。採用此克羅巴型構造時,可增大重錐體 AR,同時延長樑長度,故即使小型,也可實現高感度之 加速度感應器。又’重錐體AR之周邊部為貫通區域,樑 BM之下側區域為空洞區域。可藉該貫通區域及空洞區 域,使重錐體AR與樑BM呈現可動狀態《即,該貫通區 域及空洞區域之一部分成為重錐體AR與樑bm之可動區 域。 又,饭汉此重錐體AR之高度h2係設計成低於與樑b Μ 連結之重錐體之支持構造(半導體基板)之高度hi。 此壓電電阻型之3軸加速度感應器之動作原理係依據 在重錐體受到加速度(慣性力)時,樑BM會變形,而藉形 成於其表面之壓電電阻元件之電阻值之變化檢測加速度 之機理。而,設定成可由3軸各自獨立裝入之後述之惠斯 通電橋之輸出取出此感應器之輸出之構成。 圖9係說明爻到各軸方向之加速度之情形之重錐體與 樑之變形之概念圖。 如圖9所示,壓電電阻元件具有其電阻值會因被施加 之j變而發生變化之性質(壓電電阻效應),在拉力應變 之^形,電阻值會增加,在壓縮應變之情形,電阻值會 …、在本例中,係以X軸方向檢測用屢電電阻元件 Rx4、Y軸方向檢測用壓電電阻元件Ryl〜Ry4、及z 軸方向檢測用壓電電阻元件Rzl〜Rz4作為—例加以表 7T> 。 圖0係對各轴所設之惠斯通電橋之電路構成圖。 112514.doc -16- 1309447 圖剛係在x⑺軸之惠斯㈣橋之_ X軸及γ軸之輸出電壓,假設分別為Vxol^v 〇作為 圖10⑻係z軸之惠斯通電橋之電路構成圖。n 輸出電壓,假設為Vzout。 卞马z軸之 如上所述,各轴之4個壓電電阻元件之電阻 施加之應變而變化,依據此變化,例如衫^因^】12514.doc 11 · 1309447 The wafer holding mechanism 35 is loaded, and the wafer that has been inspected by the inspection unit 36 is reloaded into the ® box. The wafer taken out by the transfer arm 32 by the IE cassette is placed on a suction tray 34 (hereinafter simply referred to as a tray), which will be described later, and transported to the chuck 34 of the wafer holding mechanism 35 at the same time as the tray. The wafer holding mechanism 35 maintains this state and transports it to the inspection unit 36. On the other hand, in the inspection unit 36, the position detecting camera 38 of the dream aligning device 37 detects the position of the wafer to be transported. Alignment is performed based on the detected position information to perform position adjustment or the like for contacting a probe to be described later to a desired test pad of the device formed on the wafer. FIG. 2 is a schematic configuration diagram of the inspection unit 36. Referring to Fig. 2, the probe card 5 to which the probe 51 is attached is connected to the test head 55. The test head 55 is used to mount the pattern output portion of the inspection power source and the electrode electrode applied to the wafer or to output the electrode It is formed by a separate columnar body of an electric device (not shown) such as an input port for the measuring unit. The 曰s round holding mechanism 35 is a vacuum pump 1 $ as an adsorption mechanism that is connected to the suction cup 34 through a flexible conduit 丨7. The vacuum pump 18 can vacuum-adsorb the wafer and the semiconductor wafer transfer tray by the vacuum pump 18 to maintain the state to perform inspection. Fig. 3 is an explanatory view showing a transport tray for a semiconductor wafer according to Embodiment 1 of the present invention. Fig. 3 (a) is a view of the transport tray 2 for a semiconductor wafer according to the first embodiment of the present invention as seen from the upper portion. 112514.doc 1309447 Refer to Figure 3 (a) to cover the wafer! In this manner, the carrier tray 2 for a semiconductor wafer is placed in accordance with the outer diameter of the wafer, and formed into a shape capable of maintaining a semiconductor wafer. In this example, as an example, a wafer transfer tray 2 is formed in a disk shape similar to the wafer having an outer diameter larger than the outer diameter of the wafer. Fig. 3(b) In the embodiment of the invention, the semiconductor wafer transfer tray 2 is cut away from the cross-sectional view as seen in the lateral direction. As shown in Fig. 3(b), the base portion 2c having the inverted shape of the wafer is placed, and It is connected to the base portion 2 (the recessed open y-shaped outer wall portion 2b is formed for the purpose of fixing the semiconductor wafer. Further, the inner peripheral surface of the wall portion 2b is disposed along the shape of the semiconductor wafer' and is designed to be The semiconductor wafer can be held while the semiconductor wafer is placed. Further, the base portion 2e/f is provided corresponding to the outer diameter of the semiconductor wafer, and has a surface on which the semiconductor wafer is placed and a back surface for vacuum suction during transportation. Moreover, the semiconductor wafer transfer tray can use engineering plastics such as quartz or polyimine resin, P dirty, ceramic sol, and ceramics (for example, alumina (Al 2 〇 3), aluminum nitride (8) N), Cerium oxide (Zr〇2), zinc oxide, boron nitride (BN, PBN), quartz, germanium, and Stainless steel, etc. Especially in enamel, aluminum or stainless steel, because of the high thermal conductivity, it is possible to check the precision of the semiconductor wafer by @, 铭, or not. FIG. 4(4) shows that the wafer illustrated in FIG. 3 and the tray on which the wafer is placed are placed on the transfer arm 32 by 112514.doc -13· 1309447. Fig. 4(b) is a view seen from above in the state of being placed on the transport arm 32. As shown in Fig. 4(b), the tray 2 is placed on the 32a and 32b formed on the U shape. In this example, the case where the wafer 1 is placed on the tray 2 when the transfer arm 32 is placed is described as an example. For example, a storage tray for storing a semiconductor wafer (not shown) is used. (not shown), the semiconductor wafer transfer tray 2 is taken out by another transfer arm (not shown) and first placed on the arms 32a & 32b. In order to use a plurality of transfer arms, a plurality of wafers are accommodated. The wafer taken out of the box (not shown) is stored in the tray 2, and alignment is performed by using an alignment device or the like. After being adjusted, it is placed on the tray 2. Further, as an alignment device, there are various methods such as a method of performing alignment adjustment by image processing using a camera image, and a method of performing alignment adjustment by using a laser, but In the state where the wafer i is placed on the tray 2, as described above, it is transported to the chuck 34 of the wafer holding mechanism 35. Fig. 5 is a wafer An illustration of a portion of the holding mechanism 35. As shown in Fig. 5, the wafer holding mechanism 35 is slidably guided by a Y-direction guide rail 43 disposed along the γ direction, and is orthogonal to The direction in which the Υσ2Υ direction is set, that is, the X-direction guide rail U provided in the χ direction is slidably guided, and the X-stage is mounted so as to be movable up and down (Ζ direction) and to rotate the suction cup 34. In this case, as will be described later, the suction cup 34 is opened to have a hollow shape having a small hole for suction, and a vacuum pump i8 as an adsorption mechanism is connected to the hollow portion of the suction cup via a flexible line 17 of 112514.doc • 14 - 1309447. . Fig. 6 is an explanatory view showing a state in which the tray 2 is sucked by the vacuum pump 18. Referring to Fig. 6, the suction cup 34 has a plurality of suction apertures 3 on which the tray 2 is placed. By the activation of the vacuum pump 18, the inside of the hollow portion of the suction cup can be negatively pressurized and the tray 2 can be adsorbed and held. The tray 2 can be stably adsorbed in this state while holding the wafer. Here, as an example, the molding will be described. The three-axis acceleration sensor of the MEMS device is used in the wafer 1. Fig. 7 is a diagram of the three-axis acceleration sensor as seen from the device. As shown in Fig. 7, a plurality of wafers τρ formed on the wafer 1 are arranged.塾PD. In order to transmit an electrical signal to the pad or to transmit an electrical signal, metal wiring is placed. In the center, four heavy cones forming a Crowe type are arranged. Fig. 8 is a 3-axis acceleration sensor. Referring to Fig. 8, the 3-axis acceleration sensor is of a piezoresistive type, and has a piezoresistive element as a detecting element as a diffusion resistor. This piezoresistive type acceleration sensor can utilize an inexpensive 1C process. Even if a small resistive element as a detecting element is formed, the sensitivity is not lowered, so that it is advantageous for miniaturization and low cost. As a specific configuration, the central heavy cone is eight feet and presents four beams.构造Supported structure: The beam-and-beam system has four piezoresistive elements per one axis so that the two axes of X and γ are orthogonal to each other. Four piezoresistive elements for detecting the x-axis direction are arranged in X. The side surface of the piezoresistive element for the axial direction detection. The upper shape of the heavy cone AR is formed into a Cropa type, and is connected to the beam BM at the central portion H2514.doc 1309447. When this structure is used, the weight can be increased. Cone AR, while extending the length of the beam, can realize high-sensitivity acceleration sensor even if it is small. The peripheral part of the heavy cone AR is the through area, and the lower side of the beam BM is the hollow area. In the region and the void region, the heavy cone AR and the beam BM are in a movable state. That is, one of the through region and the void region becomes a movable region of the heavy cone AR and the beam bm. Moreover, the height of the heavy cone AR of the rice The h2 system is designed to be lower than the height hi of the support structure (semiconductor substrate) of the heavy cone connected to the beam b 。. The action principle of the piezoresistive 3-axis acceleration sensor is based on the acceleration of the heavy cone (inertia When the force), the beam BM will change And detecting the acceleration mechanism by the change in the resistance value of the piezoresistive element formed on the surface thereof, and setting the output of the inductor to be taken out from the output of the Wheatstone bridge described later by the three axes independently. Fig. 9 is a conceptual diagram illustrating the deformation of the heavy cone and the beam in the case of the acceleration in the direction of each axis. As shown in Fig. 9, the piezoresistive element has a resistance value which varies depending on the applied j. The nature (piezoelectric resistance effect), the resistance value will increase in the tensile strain, and the resistance value will be in the case of compressive strain. In this example, the electric resistance component Rx4 is detected in the X-axis direction, The piezoresistive elements Ryl to Ry4 for detecting the Y-axis direction and the piezoresistive elements Rz1 to Rz4 for detecting the z-axis direction are referred to as Table 7T as an example. Fig. 0 is a circuit diagram of a Wheatstone bridge provided for each axis. 112514.doc -16- 1309447 Figure is the output voltage of the X-axis and γ-axis of the Whist (four) bridge of the x (7) axis, assuming Vxol^v 分别 as the circuit structure of the Wheatstone bridge of the z-axis of Figure 10 (8) Figure. n Output voltage, assumed to be Vzout. The z-axis of the Hummer is as described above, and the strain applied by the resistance of the four piezoresistive elements of each axis changes, and according to this change, for example, the shirt ^^

f電電阻元件會檢測惠斯通電橋所形成之電路之輸出^ 軸之加速度成分作為被獨立地分離之輸出電麗。」出: 構成上述之電路,㈣連結如圖7所 士為 等,並由特定之墊可檢測對 这之金屬布線 檢利對各軸之輸出電壓之構成方 J T双W 7瓜迷度之DC成分 故也可使用作為檢測重力加速度之傾斜角感應器。 在本實施型態之構成令,在晶圓保持機構35中The f-resistance element detects the acceleration component of the output shaft of the circuit formed by the Wheatstone bridge as the output of the independently separated output. "Output: constituting the above-mentioned circuit, (4) connecting as shown in Figure 7, etc., and the specific pad can detect the metal wiring wiring for the output voltage of each axis. JT double W 7 The DC component can also be used as a tilt angle sensor for detecting gravitational acceleration. In the embodiment of the present embodiment, in the wafer holding mechanism 35

吸附之際’托盤係㈣吸盤34之吸制小孔執行吸附At the time of adsorption, the suction hole of the tray (four) suction cup 34 performs adsorption.

搬運即’在形成有上述加速度感應器之晶圓中,如S 所說明,因玫有貫通區域,故不能利用真空i 1 8之真 吸附直接搬運晶圓。 一 仁在載置半導體晶圓之本發明之實施型態1之托盤2 中在利用吸盤34之吸引用小孔吸附托盤2之際,因在托 盤中並…、貝通部,故可施行真空吸附,不需要特別之裝 了知疋地吸附晶圓1,例如,可在上述之檢查部 σ Θ易地執行希望之檢查。又,在本例中,雖說明 在檢查裝置30之檢查部36中藉吸附而搬運半導體晶圓之 112514.doc 17 1309447 情形,但並不特別限制於檢查裝置,例如,在藉真空吸 附吸附半導體晶圓而搬運至其他裝置之情形,也可利用 本發明之實施型態1之半導體晶圓用搬運托盤簡易且穩定 地予以吸附搬運。 (實施型態1之變形例1) 圖11係本發明之實施型態1之變形例1之半導體晶圓用 搬運托盤2#之說明圖。 參照圖11,半導體晶圓用搬運托盤2#與半導體晶圓用 搬運托盤2相比,不同之點在於在特定區域設有貫通部, 其他之點相同’故不重複其詳細說明。 圖12係成型於一般的半導體晶圓j之複數晶片τρ之說 明圖。 參…、圖12,在此,例如表示3軸加速度感應器之 裝置形成複數個晶片狀之情形。在晶圓】,一般採用具有 形成設有可動部之微小構造體之MEMS裝置之形成區 域、設有未形成任何構件或設有半導體裝置之檢查用之 所謂TEG(TeSt Element Gr〇up ;測試元件群)圖案之周邊 區域之構成。在此’顯示在晶圓i之外周區域以外之中央 區域設有複數個MEMS裝置之晶片τρ之情形。晶^之外 周區域由SMEMS裝置之特性誤差之影響較大,故被使 用作為周邊區域之情形較多。因此,此種情形,即,在 晶圓之外周Μ,不會設置成型赃⑽裝置之情形之貫 通區域。從而’聽瞭解在晶圓之某特定區域無貫通區 域之情形’即可直接利用真空吸附吸住該晶圓之該特定 112514.doc 1309447 區域。 j本發明之實施型態丨之變形例1中,例如對應於未設 有貫通區域之晶圓之特定區域部分,在 ^ 干導體晶圓用搬 運托盤2 #設置貫通部4。 同時,真m可經由吸引用小孔3及貫通心 空吸附半導體晶圓1。 一 因此,上述實施型態丨之托盤2#雖構 1抒取1重具空吸附托 盤2 #之構成’但本例因採用也可直 > 八I及附晶圓1之構 成,而更具有固定效果。是故, 吸附。 在更穩-之狀態加以 又’在此,作為一例,雖係說明在瞭解在晶圓之外周 區域無貫通區域時,於外周區域設置貫通部而直接真办 吸附半導體晶圓之情形,但並不限定於此,當缺也 瞭解在其他特定區域(含形成區域)無貫通區二;,== 其他特定區域部分設置貫㉟部而依照與上述同I方式= 接真空吸附半導體晶圓》 $ 圖13係本發明之實施型態丨之變形 71 十導體晶 圓用搬運托盤2 # a之說明圖。在此,传 ^ 货、刘举對應於瞭解 無貫通區域之特定區域之位置,於半導體晶圓用搬運托 盤2 # a設置貫通部4時,使其不與吸引用小孔3之位置對 應之情形之例。在此種情形’由於在托盤2“之背面侧 形成有吸引用小孔3之位置與貫通部4間之路徑,故也可 成型成在半導體晶圓用搬運托盤2形成引導貫通部$。 D (實施型態1之變形例2) 112514.doc -19- 1309447 在上述貫施型態1中’說明有關對應於晶圓外經形成 外徑比其更大而與晶圓同樣之圓板狀形狀之半導體晶圓 用搬運托盤之情形。具體上,係說明有關由載置晶圓之 圓板狀之形狀之基底部2c、與内周面沿著半導體晶圓之 形狀設置之外壁部2b所構成之托盤之情形,但在本實施 型態1之變形例2中,則說明有關其他形狀之托盤。 圖14係本發明之實施型態1之變形例2之半導體晶圓用 搬運托盤之說明圖。 圖14(a)係本發明之實施型態1之變形例2之半導體晶圓 用搬運托盤之一例圖。係本發明之實施型態丨之變形例2 之半導體晶圓用搬運托盤2〇由上部所見之圖。 如圖14(a)所示,半導體晶圓用搬運托盤2〇係由載置晶 圓之基底部2 0 a、及沿著半導體晶圓工之外周端部之至少 一部區域設置之外壁部20b所構成。在此,外壁部2〇b與 圖3之外壁部2b相比,並非採用對應於半導體晶圓1之外 周端部之全區域而沿著晶圓外周面設置外壁部几之構 成,而係採用對應於外周端部之一部分區域而沿著晶圓 外周面設置之構成。又,在此,係設有2個外壁部2〇b, 將其設成介隔基底部20a而互相相對,而形成可將晶圓保 持於此之形狀。再者,在此,基底部20a係對應於半導體 晶圓之外徑而被設置’並形成可載置晶圓全面之圓板狀 之形狀。 圖14(b)係本發明之實施型態丨之變形例2之別的半導體 晶圓用搬運托盤之-例圖。係本發明之實施型I之變形 112514.doc 1309447 例2之別的半導體晶圓用搬運托盤2〇 #由上部所見之圖。 如圖14(b)所示,半導體晶圓用搬運托盤2〇#係由載置 晶圓之基底部20a、及沿著半導體晶圓i之外周端部之至 少一部區域設置之外壁部20c所構成。在此,外壁部2〇c 與圖14(a)之外壁部20b相比,並非採用設置2個互相相對 之外壁部之構成,而係採用設成以4個外壁部2〇c包圍晶 圓之外周端部之構成,而形成可將晶圓保持於此之形 狀。又,在此,雖顯示4個外壁部2〇c,但並不限定於 此,也可設成沿著外周端部之至少丨個區域,以複數個外 壁部包圍晶圓之外周端部。 又,半導體晶圓用搬運托盤之重量愈重時,愈會造成 ’而有搬運精度惡化之可能性,但In the wafer in which the above-described acceleration sensor is formed, as described in S, since the rose has a through region, the wafer cannot be directly transported by the vacuum i 1 8 . In the tray 2 of the first embodiment of the present invention in which the semiconductor wafer is placed, when the tray 2 is sucked by the suction hole of the suction cup 34, the vacuum can be applied in the tray and the Beton portion. The adsorption does not require a special adsorption of the wafer 1, and for example, the desired inspection can be easily performed at the inspection unit σ described above. Further, in the present embodiment, the case where the semiconductor wafer is transported by the inspection unit 36 of the inspection apparatus 30 is described in the case of 112514.doc 17 1309447, but it is not particularly limited to the inspection apparatus, for example, by vacuum adsorption of the semiconductor. In the case where the wafer is transported to another device, the transfer tray for the semiconductor wafer according to the first embodiment of the present invention can be easily and stably adsorbed and transported. (Variation 1 of the first embodiment) FIG. 11 is an explanatory view of the transport tray 2# for a semiconductor wafer according to the first modification of the first embodiment of the present invention. Referring to Fig. 11, the semiconductor wafer transfer tray 2# differs from the semiconductor wafer transfer tray 2 in that a through portion is provided in a specific region, and the other points are the same. Therefore, detailed description thereof will not be repeated. Fig. 12 is an explanatory view showing a plurality of wafers τρ formed on a general semiconductor wafer j. Here, Fig. 12, for example, shows a case where a device of a three-axis acceleration sensor forms a plurality of wafers. In the wafer, a so-called TEG (TeSt Element Gr〇up; test element) having a formation region of a MEMS device in which a micro structure having a movable portion is formed, and a member in which no member is formed or a semiconductor device is provided is generally used. Group) The composition of the surrounding area of the pattern. Here, the case where the wafer τρ of a plurality of MEMS devices is provided in the central region other than the outer peripheral region of the wafer i is shown. Since the peripheral region of the crystal is greatly affected by the characteristic error of the SMEMS device, it is often used as a peripheral region. Therefore, in such a case, that is, outside the wafer, the through region of the case where the crucible (10) device is formed is not provided. Thus, by listening to the fact that there is no through region in a particular area of the wafer, the specific 112514.doc 1309447 region of the wafer can be directly absorbed by vacuum adsorption. In the first modification of the embodiment of the present invention, for example, the through portion 4 is provided in the dry conductor wafer transport tray 2 # corresponding to the specific region portion of the wafer in which the through region is not provided. At the same time, the true m can adsorb the semiconductor wafer 1 through the suction hole 3 and through the core. Therefore, the tray 2# of the above-mentioned embodiment is configured to take the configuration of the 1st empty adsorption tray 2#, but this example can also be used because of the configuration of the eighth and the wafer 1. Has a fixed effect. Therefore, adsorption. In the case of a more stable state, it is described that, as an example, when it is understood that there is no through region in the outer peripheral region of the wafer, the through portion is provided in the outer peripheral region, and the semiconductor wafer is directly adsorbed. It is not limited to this. When it is missing, it is also known that there is no through-region 2 in other specific regions (including formation regions); and == other portions of the specific region are provided at 35 portions according to the same I-mode = vacuum-adsorbing semiconductor wafers. Fig. 13 is an explanatory view showing a deformation of the embodiment of the present invention 71, a transport tray 2 for a ten-conductor wafer. Here, the transfer and the Liuju correspond to the position of the specific region having no through-region, and when the penetration portion 4 is provided in the semiconductor wafer transfer tray 2 # a, it does not correspond to the position of the suction small hole 3 An example of the situation. In this case, the path between the position of the suction small hole 3 and the penetration portion 4 is formed on the back side of the tray 2, so that the guide through portion $ can be formed in the semiconductor wafer transfer tray 2. (Modification 2 of Embodiment 1) 112514.doc -19- 1309447 In the above-described first embodiment, 'the description relates to a disk shape similar to the wafer corresponding to the outer diameter of the wafer. In the case of a carrier tray for a semiconductor wafer having a shape, specifically, the base portion 2c having a disk-shaped shape in which the wafer is placed and the outer peripheral portion 2b provided along the shape of the semiconductor wafer on the inner peripheral surface are described. In the case of the trays of the first embodiment, the trays of the other shapes are described. FIG. 14 is a description of the carrier tray for semiconductor wafers according to the second modification of the first embodiment of the present invention. Fig. 14 (a) is a view showing an example of a transport tray for a semiconductor wafer according to a second modification of the first embodiment of the present invention. The transport tray 2 for a semiconductor wafer according to a second modification of the embodiment of the present invention. 〇The picture seen from the top. As shown in Figure 14 (a), the semiconductor The circular transport tray 2 is composed of a base portion 20a that mounts the wafer and an outer wall portion 20b that is provided along at least one of the outer peripheral end portions of the semiconductor wafer worker. Here, the outer wall portion 2b b is a configuration in which an outer wall portion is provided along the outer peripheral surface of the wafer corresponding to the entire outer peripheral end portion of the semiconductor wafer 1 as compared with the outer wall portion 2b of FIG. 3, and a portion corresponding to the outer peripheral end portion is employed. The region is disposed along the outer peripheral surface of the wafer. Here, two outer wall portions 2〇b are provided, which are disposed to face each other with the base portion 20a interposed therebetween, thereby forming a wafer to be held there. Further, here, the base portion 20a is provided in accordance with the outer diameter of the semiconductor wafer and forms a disk-like shape in which the entire wafer can be placed. Fig. 14(b) shows the implementation of the present invention. Example of a transfer tray for a semiconductor wafer according to a modification of the second aspect of the invention. FIG. 1 is a modification of the embodiment I of the present invention. 112514.doc 1309447 The transport tray for a semiconductor wafer of the second embodiment is used. As shown in Fig. 14 (b), the carrier tray for semiconductor wafers The base portion 20a of the wafer and the outer wall portion 20c are provided along at least one of the outer peripheral ends of the semiconductor wafer i. Here, the outer wall portion 2〇c and the outer wall portion 20b of Fig. 14(a) In contrast, instead of arranging two mutually opposite outer wall portions, a configuration in which the outer peripheral end portions of the wafer are surrounded by the four outer wall portions 2〇c is formed to form a wafer in which the wafer can be held. Here, although the four outer wall portions 2〇c are shown, the present invention is not limited thereto, and the outer peripheral end portion of the wafer may be surrounded by a plurality of outer wall portions along at least one of the outer peripheral end portions. Moreover, the heavier the weight of the transport tray for a semiconductor wafer, the more likely it is to have a deterioration in handling accuracy, but

以設計半導體晶圓用搬運托盤之形狀為宜。 (實施型態1之變形例3) 搬運臂等墜彎之原因, 如該構成所示,為保It is preferable to design the shape of the transport tray for a semiconductor wafer. (Modification 3 of Embodiment 1) The reason why the arm is bent, etc., as shown in this configuration, is to protect

圖15係對應於定向平面型 卜’雖說明有關晶圓形狀為圓狀之 此也有所謂定向平面(orientation 稱為才U )或缺口型之晶圓存 晶圓之情形’係在晶圓之—部分設 口)區域(缺口區域)。 平面型晶圓之半導體晶圓用搬運托 112514.doc 1309447 盤之說明圖。 在㈣⑷,對應於半導體晶圓1#之外周端 域而沿著晶圓之外周 ^ 冋— 置外壁部’而以可在此保持晶 圓之方式形成半導體晶圓用搬運托盤21。 圖剛所示之半導體晶圓用搬運托盤2u係對 導體晶圓1#,端部之-部分區域而非全區域,而沿 著晶圓之外周面設置外壁部。又,在對應於定向平面型 晶圓之特徵之切斷區域(定向平面區域)之—部分,另外 設有外壁部21b。又,也可同樣適用於缺口型之晶圓。 此外壁部21b由於係形成自晶圓中心點至外壁部21匕之 内周部之長度短於晶圓之外周端部之半徑長度之最大 值,故可防止晶圓在外壁部所包圍之區域内之旋轉。 (實施型態1之變形例4 ) 茲說明在本實施型態!之變形例4中,藉真空吸附更穩 定地保持半導體晶圓用搬運托盤之方式。 圖16係對應於本發明之實施型態1之變形例4之定向平 面型aa圓之半導體晶圓用搬運托盤2丨#之說明圖。又, 在此’作為一例,雖說明有關圖1 5 (a)所說明之定向平面 型晶圓之半導體晶圓用搬運托盤,但並不限定於此,例 如’也可同樣適用於對應於通常之圓形狀之晶圓之托 盤。 參照圖16(a),在半導體晶圓用搬運托盤21 #之背面, 例如以中心點〇為中心,且在中心點〇周圍對稱地設有複 數個圓形狀之吸引用小孔3。而,對應於此吸引用小孑L 3 112514.doc -22- 1309447 盤之月面6又置凹部5 #,以擴大真空吸附之吸附面 積。凹部5#係沿著托盤之中心點。方向對應於複數個吸 引用小孔3而被設置。 、,圖1 6(b)係對應於本發明之實施型態丨之變形例4之定向 平面型晶圓之半導體晶圓用搬運托盤21 #由侧面方向所 見之圖。 在本例之半導體晶圓用搬運托盤21# ,對應於吸引用 小孔3在托盤之背面設置凹部5 #,以擴大吸附面積。 而,此凹部5 #係在中心點0周圍對稱地被設置。 如此,可經由凹部5 #而藉真空泵執行真空吸附,此 際,吸附力可以中心點0為中心均等地被施加,故可以中 心點〇為中心固定托盤,且也可抑制托盤之旋轉。 (實施型態2) 在上述實施型態1中,說明有關以包圍半導體晶圓方 式設置外壁部而固定之半導體晶圓用搬運托盤。 在本貫施型態2中,說明有關以別的方式固定半導體 晶圓之情形。 圖17係本發明之實施型態2之半導體晶圓丨〇之說明 圖。 參照圖1 7 ’本發明之實施型態2之半導體晶圓1 〇具有 孔部11。在此,係設有2個孔部11作為—例。又,作為半 導體晶圓10之形狀,在此雖顯示定向平面型晶圓,但也 可同樣適用於通常之圓板狀晶圓。又,如上所述,一般 而言’晶圓一般係採用形成具有可動部之微小構造體之 112514.doc -23· 1309447 MEMS裝置之形成區域、與具有未形成任何構件之周邊 區域之構成。例如,晶圓之外周區域例如由於在成型 ♦ MEMS裝置之情形,其特性誤差之影響較大,故可考慮 將其使用作為周邊區域。因此,在設置孔部i丨之際,在 • MEMS裝置難以成型之晶圓之外周區域設置孔部U時, 可較有效地利用周邊區域。 圖18係本發明之實施型態2之半導體晶圓用搬運托盤 Φ 之說明圖。 在此,係表示半導體晶圓用搬運托盤26由側面方向所 見之圖。 參照圖18 ’半導體晶圓用搬運托盤26係由突起部1 〇〇 與基底部25所構成。在基底部25之表面側上載置半導體 晶圓10。而,此際,設於基底部25之表面之突起部1〇〇可 貫通設於半導體晶圓ίο之孔部η而將半導體晶圓1〇與基 底部25固定。 ® 同時,藉上述真空泵1 8經由吸引用小孔3真空吸附托 盤時’可穩定地加以保持,並以穩定狀態吸附半導體晶 圓。 又,在此,上述孔部11雖也可利用鑽頭開設,但也可 在裝置之製程中形成。 圖19係成型圖7及圖8所説明之3軸加速度感應器之際 之製程之概略說明圖。 如圖19(a)所示,首先,在此,顯示具有s〇I層 300(SOI)、埋入氧化膜301(BOX)、及 Si基板 302(Si-Sub) 112514.doc •24· 1309447 之s〇I晶圓(S0I Wafer)。而,藉光微影步驟形成感應器 之電路圖案。I又而言,係將抗钱劑滴在晶圓表面,經 由遮罩對抗㈣照射紫外光而使其曝光顯影。而,重複 施行蝕刻、抗蝕劑剥離等步驟,以形成電路圖案。在圖 19(b)中,係表示於s〇I層上形成絕緣膜3〇5後,利用離子 注入法及絕緣膜之圖案化,形成壓電電阻306,而後,形 成鋁布線3〇4,以鈍化膜3〇3(SiN)保護其表面之情形f 在在圖19⑷中’係表示接著藉Si Deep RIE技術 將則層之重錐體與樑及固定框部之間隙部分餘刻上部 側至BOX層為止之情形。其次,在圖19⑷中,係表示藉Figure 15 corresponds to the orientation of the plane type. Although the description of the wafer shape is circular, there is also a so-called orientation plane (orientation called U) or a gap-type wafer storage wafer. Partially set) area (notched area). Handling tray for semiconductor wafers for flat wafers 112514.doc 1309447 Illustration of the disk. In (4) and (4), the semiconductor wafer transfer tray 21 is formed so as to be able to maintain a crystal shape along the outer periphery of the wafer in accordance with the outer peripheral end region of the semiconductor wafer 1#. The semiconductor wafer transfer tray 2u shown in the figure is a pair of conductor wafers 1#, an end portion-partial region instead of the entire region, and an outer wall portion is provided along the outer peripheral surface of the wafer. Further, an outer wall portion 21b is additionally provided in a portion corresponding to the cut region (orientation plane region) of the feature of the oriented flat type wafer. Also, the same applies to the notched type wafer. Further, since the length of the inner peripheral portion of the wall portion 21b from the center point of the wafer to the outer wall portion 21 is shorter than the maximum length of the outer peripheral end portion of the wafer, the wafer can be prevented from being surrounded by the outer wall portion. The rotation inside. (Modification 4 of Embodiment 1) It is explained in this embodiment mode! In the fourth modification, the method of transporting the tray for the semiconductor wafer is more stably maintained by vacuum suction. Fig. 16 is an explanatory view of a transfer tray 2丨 for a semiconductor wafer of an oriented flat type aa round according to a fourth modification of the first embodiment of the present invention. In addition, although the conveyance tray for the semiconductor wafer of the oriented planar type wafer described in FIG. 15 (a) is described here as an example, it is not limited to this, for example, it can apply similarly to the normal. A wafer tray of round shapes. Referring to Fig. 16 (a), on the back surface of the semiconductor wafer transfer tray 21 #, for example, a plurality of circular suction holes 3 are provided symmetrically around the center point 〇 around the center point 。. On the other hand, the concave surface 5# corresponding to the suction face L 3 112514.doc -22- 1309447 is used to enlarge the adsorption area of the vacuum adsorption. The recess 5# is along the center point of the tray. The direction is set corresponding to a plurality of suction apertures 3. Fig. 16(b) is a view showing the transfer tray 21 for the semiconductor wafer of the orientation flat type wafer corresponding to the modification 4 of the embodiment of the present invention, as seen from the side direction. In the semiconductor wafer transfer tray 21# of this example, a recess 5# is provided on the back surface of the tray corresponding to the suction small hole 3 to enlarge the suction area. However, this recess 5# is symmetrically disposed around the center point 0. In this way, vacuum suction can be performed by the vacuum pump via the recess 5#. In this case, the suction force can be equally applied centering on the center point 0. Therefore, the center can be fixed as a center, and the rotation of the tray can be suppressed. (Embodiment 2) In the above-described first embodiment, a transfer tray for a semiconductor wafer which is fixed by providing an outer wall portion around a semiconductor wafer will be described. In the present embodiment 2, a description will be given of a case where the semiconductor wafer is fixed in another manner. Fig. 17 is an explanatory view showing a semiconductor wafer cassette of the embodiment 2 of the present invention. Referring to Fig. 17, a semiconductor wafer 1 of the embodiment 2 of the present invention has a hole portion 11. Here, two hole portions 11 are provided as an example. Further, although the shape of the semiconductor wafer 10 is shown as an oriented planar wafer, the same can be applied to a normal disk-shaped wafer. Further, as described above, in general, the wafer is generally formed by forming a region of a 112514.doc -23· 1309447 MEMS device having a microstructure having a movable portion and a peripheral region having no member formed. For example, since the peripheral region of the wafer has a large influence on the characteristic error, for example, in the case of molding a MEMS device, it can be considered as a peripheral region. Therefore, when the hole portion i is provided, when the hole portion U is provided in the outer peripheral region of the wafer which is difficult to mold by the MEMS device, the peripheral region can be utilized more effectively. Fig. 18 is an explanatory view showing a transport tray Φ for a semiconductor wafer according to Embodiment 2 of the present invention. Here, the semiconductor wafer transfer tray 26 is shown in the side direction. Referring to Fig. 18, the semiconductor wafer transfer tray 26 is composed of a projection 1 and a base portion 25. The semiconductor wafer 10 is placed on the surface side of the base portion 25. On the other hand, the projections 1 provided on the surface of the base portion 25 can pass through the hole portion η of the semiconductor wafer λ to fix the semiconductor wafer 1 to the base portion 25. At the same time, when the vacuum pump 18 is vacuum-adsorbed through the suction hole 3, it can be stably held, and the semiconductor crystal is adsorbed in a stable state. Here, the hole portion 11 may be formed by a drill, but it may be formed in the process of the device. Fig. 19 is a schematic explanatory view showing a process of molding the three-axis acceleration sensor illustrated in Figs. 7 and 8. As shown in FIG. 19(a), first, here, there is shown a s〇I layer 300 (SOI), a buried oxide film 301 (BOX), and a Si substrate 302 (Si-Sub) 112514.doc • 24· 1309447 s〇I wafer (S0I Wafer). Instead, the circuit pattern of the inductor is formed by the photolithography step. In addition, the anti-money agent is dropped on the surface of the wafer, and exposed to ultraviolet light by a mask to expose it to exposure and development. On the other hand, steps such as etching and resist stripping are repeatedly performed to form a circuit pattern. In Fig. 19(b), after forming the insulating film 3?5 on the s?I layer, patterning is performed by ion implantation and patterning of the insulating film to form the piezoresistor 306, and then aluminum wiring 3?4 is formed. The case where the surface is protected by the passivation film 3〇3 (SiN) f is shown in Fig. 19(4), which is followed by the Si Deep RIE technique to remove the gap between the heavy cone of the layer and the beam and the fixed frame portion. The situation up to the BOX layer. Secondly, in Figure 19 (4), it means to borrow

Sl Deep RIE技術由背面餘刻基板側Si基板之間隙部及樑 下部至BOX層為止’最後蝕刻Β〇χ層而釋放構造體之情 形0 依照上述製程,即可成型圖8所示之重錐體與樑及固 定框部。 也可利用此Si Deep RIE技術,在半導體晶圓之未形成 任何構件之周邊區域’由表面及背面蝕 體與襟及固定框部同時成型上述孔部η。具體上= 光微影步驟中,預先在遮罩上形成與孔部叩一之形 狀’在光微影步驟中’將與孔部_一之形狀燒結於附 在基板之抗触劑而將抗餘劑顯影後’藉Si Deep RIE技術 由表面及背面_基板’即可高精度地形成孔部Π。因 b不而要β又置特別之裝置或設置孔部用之特別之製 私,即可在加速度感應'器之成型之同時一併成型孔部 112514.doc -25- 1309447 11,故可簡易地成塑孔部11。又,由於可藉Si Deep rie 技術形成南精度之孔部Π之形狀’故在成本方面也相备 有利。Sl Deep RIE technology is the case where the structure is released by the process of the above process, and the heavy cone shown in FIG. 8 can be formed by the process of releasing the structure from the gap portion of the Si substrate on the back side of the substrate and the lower portion of the beam to the BOX layer. Body and beam and fixed frame. The Si deep RIE technique can also be used to form the hole portion η at the same time as the peripheral region of the semiconductor wafer where no member is formed, by the surface and back etching, and the crucible and the fixing frame portion. Specifically, in the photolithography step, the shape formed in the mask and the shape of the hole portion in the photolithography step is sintered in the photolithography step to the anti-contact agent attached to the substrate. After the development of the residual agent, the hole portion 即可 can be formed with high precision by the surface and back surface _ substrate by the Si Deep RIE technique. Because b does not need to set a special device or set a special part for the hole part, the hole part 112514.doc -25- 1309447 11 can be formed at the same time as the acceleration sensor is formed. The hole portion 11 is formed in the ground. Moreover, since the shape of the hole portion of the south precision can be formed by the Si Deep rie technique, it is also advantageous in terms of cost.

又,在此’雖說明有關嵌合貫通之孔部丨丨與突起部1〇〇 之情形作為一例,但’不貫通之情形也無妨。例如,嵌 合未貫通之孔部11與突起部100時,也可期待同樣之效 果。又,在孔部11之孔之形狀與突起部100之形狀方面, 雖可形成圓形狀之孔部11與突起部100作為一例,但例如 也可將孔部11與突起部100之形狀形成多角形。 圖2 0係本發明之實施型態2之另一半導體晶圓i #之 說明圖。 參照圖2〇 ’本發明之實施型態2之另一半導體晶圓i #具有孔部11# °在此’設有2個孔部11#作為-例。^ 孔部異於圖17所說明之孔部u,係、以三角形… 形狀成型作為多㈣狀之-例。m角形之剖Η 狀成型突起部,以便與孔部u#嵌合。因&,在 起部與孔部之際,肖圓形之形狀相比,可: 部分產生扣合力,故可推^ 部25之關係之旋轉/ 步抑制半導體晶圓㈣ 二IS部25之大小也可小於半導體晶圓之大小1 大於形成微小構造體之區域=面積,例如使其㈣ 體晶圓之缺口或所…:之面積。因此’可利用半導 對準調整。斤…平面容易地執行半導體晶圓之 112514.doc -26- 1309447 又在上述中,雖說明有關在成型裝置之中央區域以 外之外周區域設置孔部11A11#之情形M旦關於此孔部 . 11及11#之位置,也可形成於任意區域,藉設置對應之 • 大起部,也可獲得與上述同樣之效果。又,也可設計成 在成里裝置之區域中,利用一部份之區域設置孔部及對 應之突起部。 ‘ (實施型態2之變形例〇 籲 圖21係本發明之實施型態2之變形例1之半導體晶圓用 搬運托盤27之說明圖。 參照圖21,半導體晶圓用搬運托盤27與半導體晶圓用 搬運托盤26相比,相異之點在於將基底部25置換成基底 部25 #。基底部25 #基底部25相比,相異之點在於在特 疋區域设有貫通部。其他之點相同,故不重複其詳細說 明。 如上所述’在預先瞭解在晶圓之某特定區域無貫通區 ® 域之情形’可藉真空吸附吸引該晶圓之該特定區域。 在本發明之實施型態2之變形例1中,例如對應於未設 有貝通區域之晶圓之特定區域部分而在半導體晶圓用搬 運托盤27設置貫通部4。 同時,真空泵18可經由吸引用小孔3及貫通部4直接真 空吸附半導體晶圓1#。 因此’可比上述實施型態2更穩定地加以保持,並可 在更穩定之狀態加以吸附。 又,在此,作為一例,雖係說明在瞭解在晶圓之外周 112514.doc -27 - 1309447 區域無貫通區域時,於外周區域設置貫通區域而直接真 工吸附半導體晶圓之情形,但並不限定於此,當然也可 f瞭解在其他特定區域(含形成區域)無貫通區域時,於 違其他特义區域設置貫通區域而依照與 接真空吸附半導體晶圓。 圖22係本發明之實施型態2之變形例!之另一半導體晶 圓用搬運托盤2 8 $約、ΒΒ ΕΙ ., 以 ^ D 圖。在此,係列舉對應於瞭解無 貫通區域之特定區域之位置’於半導體晶圓用搬運托盤 28設置貫通部4時’使其不與吸引用小孔3之位置對應之 情形之例。在此種情形,由於在基底部25#3之背面側形 成有吸引用小孔3之位置與貫通部4間之路徑,故也可成 型成在半導體晶圓用搬運托盤28形成引導貫通部5。 在上述實施型態中,主要係說明有關3軸加速度感應 器之職S裝置,但並不限定於此,例如也可同樣適; 於未具有貫通區域之MEMS裝置。 在此,例如,說明有關具有隔膜構造之薄膜之可動部 之微小構造體。 圖23係在電子束照射器之照射窗使用隔膜構造之情形 之說明圖。 如圖23所示,顯示由真空管81對大氣中出射電子束 之照射窗80之一部份,如其放大之剖面構造所示,採用 薄膜之隔膜構造。又,在圖23中,雖以單一材料形成隔 膜,且僅圖示1個隔膜構造,但也可採用以複數材料形成 多層膜構造之情形,或也可採用將複數之隔臈構造配置 112534.doc -28- 1309447 成陣列狀之照射窗。 “真空吸附成型有此種薄膜之隔膜構造之MEMs裝置之 半導體晶圓之情形’其吸附力有可能將薄膜吸附至薄骐 之可動區域以上而發生裂痕。 因此,如本發明之實施型態般,以不直接真空吸附薄 膜部份之方式設置托盤時,可穩定地加以保持,且可安 全地搬運半導體晶圓。 在上述實施型態2中,雖說明有關嵌合保持突起部與 孔部而可穩定地搬運晶圓之半導體晶圓用搬運托盤之情 形,但並不限定於此,也可組合上述實施型態丨及其變形 例所說明之方式而採用例如沿著晶圓外周面設置外壁部 之構成’藉此可更穩定地搬運晶圓。 (實施型態3) 在上述實施型態1及2中,雖說明有關將半導體晶圓與 半導體晶圓用搬運托盤之表面沿著大致全區域密接地載 置之構成之情形,但基於成型於半導體晶圓之mems裝 置之構造之需要’有進一步規劃之必要。 圖24係有別於圖8所說明之3軸加速度感應器之3軸加 速度感應器之概略圖。 參照圖24,在此所不之3軸加速度感應器與圖8所說明 之3軸加速度感應器相比,相異之點在於此重錐體之 高度h2係設計成與樑BM連結之重錐體AR之支持構造(半 導體基板)之高度hi相同高度程度。其他部分相同。該構 之3軸加速度感應器之情形,由於將重錐體AR之支持 H25l4.doc -29- 1309447 偁ie之高度與作為可動部 高戶兹/# , ^ ——厂肌度設計成相戶 又程度’故在裁置於半導體曰 作千导體日日圓用搬運托盤之情形, 作為可動部之重錐體AR# 用無 百見接近或接觸於半導體晶圓 用搬運托盤之狀態之 圓用搬運托盤之狀態τ,在上述之==於半導體晶 牡上述之檢查裝置30檢查之情 t,有可能可動部不能正當 月匕正承了動,而不能執行希望之檢Here, the case where the hole portion 嵌合 and the protrusion portion 1〇〇 that are fitted and penetrated is described as an example, but the case where the hole portion 不 is not penetrated may be used. For example, when the hole portion 11 and the protrusion portion 100 which are not penetrated are fitted, the same effect can be expected. Further, the shape of the hole of the hole portion 11 and the shape of the protrusion portion 100 may be formed by forming the circular hole portion 11 and the protrusion portion 100 as an example. For example, the shape of the hole portion 11 and the protrusion portion 100 may be formed. Angled. Fig. 20 is an explanatory view of another semiconductor wafer i # of the embodiment 2 of the present invention. Referring to Fig. 2A, another semiconductor wafer i# of the embodiment 2 of the present invention has a hole portion 11#° where two hole portions 11# are provided as an example. ^ The hole portion is different from the hole portion u described in Fig. 17, and is formed in a shape of a triangle... in the shape of a plurality (four). The m-shaped section is formed into a projection to fit the hole portion u#. Because &, when the starting part and the hole part, compared with the shape of the circular circle, the part can generate a fastening force, so that the rotation/step suppression semiconductor wafer (4) of the relationship of the part 25 can be pushed. The size may also be smaller than the size of the semiconductor wafer 1 is larger than the area where the microstructure is formed = the area, for example, the area of the (four) wafer or the area of the wafer. Therefore, semi-guide alignment adjustment can be utilized. In the above, although the case where the hole portion 11A11# is provided in the outer peripheral region other than the central portion of the molding device, the description will be made regarding the hole portion 11A11#. The position of the 11# and the position of the 11# can also be formed in any area, and the same effect as described above can be obtained by setting the corresponding large lifting portion. Further, it is also possible to design the hole portion and the corresponding projection portion in a portion of the region in which the device is formed. (Modification of the embodiment 2) FIG. 21 is an explanatory view of the semiconductor wafer transfer tray 27 according to the modification 1 of the embodiment 2 of the present invention. Referring to FIG. 21, the semiconductor wafer transfer tray 27 and the semiconductor are used. The wafer transfer tray 26 differs in that the base portion 25 is replaced by the base portion 25 #. The base portion 25 # base portion 25 differs in that a through portion is provided in the special region. The detailed description is not repeated. As described above, 'in the case where there is no penetration region® in a specific region of the wafer in advance', the specific region of the wafer can be attracted by vacuum adsorption. In the first modification of the second embodiment, for example, the penetration portion 4 is provided in the semiconductor wafer transfer tray 27 in accordance with the specific region portion of the wafer in which the Beton region is not provided. Meanwhile, the vacuum pump 18 can pass through the suction small hole. 3 and the through portion 4 directly vacuum-adsorbs the semiconductor wafer 1#. Therefore, it can be held more stably than the above-described embodiment 2, and can be adsorbed in a more stable state. Here, as an example, Understand the crystal Outside 112512.doc -27 - 1309447 When there is no through-region in the area, a through-region is provided in the outer peripheral region, and the semiconductor wafer is directly absorbed by the semiconductor. However, the present invention is not limited thereto, and it is of course possible to understand other specific regions (including In the formation region), when there is no through region, the through-region is provided in the other special region, and the semiconductor wafer is vacuum-adsorbed. FIG. 22 is a modification of the embodiment 2 of the present invention. 2 8 $约,ΒΒ ΕΙ . , ^ ^ 图. Here, the series corresponds to the position of the specific region without the through-region, when the penetration portion 4 is provided in the semiconductor wafer transport tray 28, so that it is not attracted In the case where the position of the small hole 3 corresponds, in this case, since the path between the position of the suction small hole 3 and the penetration portion 4 is formed on the back side of the base portion 25#3, it can be molded into The semiconductor wafer transfer tray 28 is formed with the guide through portion 5. In the above embodiment, the S-device for the three-axis acceleration sensor is mainly described, but the present invention is not limited thereto, and for example, the same can be applied. A MEMS device having a through-region is provided. Here, for example, a minute structure relating to a movable portion of a film having a diaphragm structure will be described. Fig. 23 is an explanatory view showing a case where a diaphragm structure is used in an irradiation window of an electron beam illuminator. As shown, a portion of the illumination window 80 that emits an electron beam from the atmosphere by the vacuum tube 81 is shown, as shown in the enlarged cross-sectional configuration, using a membrane diaphragm structure. Further, in Fig. 23, although the diaphragm is formed of a single material, Only one diaphragm structure is illustrated, but it is also possible to form a multilayer film structure from a plurality of materials, or an irradiation window in which a plurality of barrier structures 112532.doc -28-1309447 are arrayed. In the case of a semiconductor wafer in which a MEMs device having a membrane structure of such a film is adsorbed and formed, the adsorption force may cause the film to be adsorbed to a movable region of the thin crucible to cause cracks. Therefore, as in the embodiment of the present invention, when the tray is provided in such a manner that the film portion is not directly vacuum-adsorbed, it can be stably held, and the semiconductor wafer can be safely handled. In the above-described second embodiment, the case of the semiconductor wafer transfer tray in which the wafer can be stably conveyed while the projection portion and the hole portion are fitted is described. However, the present invention is not limited thereto, and the above-described embodiment may be combined. In the manner described in the ninth and its modifications, for example, the configuration in which the outer wall portion is provided along the outer circumferential surface of the wafer is employed, whereby the wafer can be conveyed more stably. (Embodiment 3) In the above-described Embodiments 1 and 2, the case where the surface of the semiconductor wafer and the semiconductor wafer transfer tray are placed in close contact with each other in substantially the entire area is described. The need for the construction of semiconductor wafer MEMS devices is necessary for further planning. Fig. 24 is a schematic view showing a three-axis acceleration sensor different from the three-axis acceleration sensor illustrated in Fig. 8. Referring to Fig. 24, the difference between the three-axis acceleration sensor and the three-axis acceleration sensor illustrated in Fig. 8 is that the height h2 of the heavy cone is designed as a heavy cone connected to the beam BM. The height of the support structure (semiconductor substrate) of the body AR is the same height level. The other parts are the same. In the case of the 3-axis acceleration sensor of the structure, the height of the support of the heavy cone AR is H25l4.doc -29- 1309447 偁ie and the height of the movable part is used as the movable part of the high-end household /#, ^ - the plant muscle degree is designed to be In the case of the semiconductor carrier, the heavy-duty AR# as the movable part is used for the transportation of the semiconductor wafer carrier tray. In the state τ of the tray, in the above-mentioned inspection = the inspection device 30 of the semiconductor crystal squid, it is possible that the movable portion cannot be properly loaded, and the desired inspection cannot be performed.

圖25係本發明之實施型態3之半導體 # P之說明圖。 圓用搬運托盤2 參照圖25⑷’半導體晶圓用搬運托盤2#p與圖n所說 明之半導體晶圓用搬運托盤2#相比,不同之點在於成型 為對载置半導體晶圓之基底部之表面部分施行柱坑加工 之形狀(柱坑區域)。#他之點與圖u所說明者相同,故 不重複其詳細說明。Figure 25 is an explanatory view of a semiconductor #P of Embodiment 3 of the present invention. Referring to Fig. 25 (4), the semiconductor wafer transfer tray 2#p is different from the semiconductor wafer transfer tray 2# described in Fig. n in that it is formed as a base portion on which the semiconductor wafer is placed. The surface portion is subjected to the shape of the pit processing (column pit area). #他点点 is the same as that illustrated in Figure u, so the detailed description is not repeated.

再參照圖25(a),在本例中,如圖12所說明,在半導體 曰曰圓於中央區域等設有晶片丁p之情形,採用在與其相 向之托盤2#p之表面形成有形成凹型之特定深度之柱坑 區域在朝向未設有晶片TP之外周區域,即周邊區域之 托盤2# p之表面未形成柱坑區域之構成。即,在朝向比 周邊區域更内側之區域之托盤2#p之表面形成柱坑區 域0 藉該構成,如圖25(b)所示,作為一例,3軸加速度感 應器之可動部之重錐體AR由於呈現因在半導體晶圓用搬 運托盤2 # p施行柱坑加工而設有特定間隔空隙之狀態, 112514.doc -30- 1309447 故可避免接觸到半導體晶圓用搬運托盤2#p之表面。是 故,在上述檢查裝置30中也可執行希望之檢查。 又’在該構成中’在朝向未設有半導體晶圓之貫通區 域之外周區域之區域,於半導體晶圓用搬運托盤2 # p設 置貫通部而直接真空吸附半導體晶圓時,可穩定地吸附 半導體晶圓。 (實施型態3之變形例1) 圖26係本發明之實施型態3之變形例1之半導體晶圓用 搬運托盤2# q之說明圖。 參照圖26(a),在此,係表示半導體晶圓用搬運托盤2 # q對載置半導體晶圓之基底部表面部分依照特定圖案施 行柱坑加工之情形。在上述圖25(a)所說明之半導體晶圓 用搬運托盤2# p之構成中,雖採用對載置半導體晶圓之 基底部表面部分,於朝向設有晶片τρ之全區域,例如中 央部分之部分全體施以柱坑加工之構《’但該構成係對 設有晶片TP之區域中,特別對朝向可動部之基底部表面 部分施以柱坑加工。 藉該構成,MEMS裝置為3軸加速度感應器之情形,如 圖26(b)所示,可對朝向重錐體AR之基底部表面部分施 以柱坑加工。因此,在重錐體AR之支持構造之部分,呈 現與基底部表面部分接近或接觸之狀態。是故,與圖乃 之構成相比,可抑制半導體晶圓之自重引起之半導體晶 圓之墜彎而加以搬運。 其他之點與圖25相同。 112514.doc •31 - 1309447 (實施型態3之變形例2) 在上述實施型態3及其變形例中,雖說明有關在半導 • 體晶圓用搬運托盤中利用實施犁態1說明之半導體晶圓用 • 搬運托盤施以柱坑加工之構成,但並不限定於此,當然 也可採用利用實施型態2說明之半導體晶圓用搬運托盤施 以柱坑加工之構成。 ' 圖27係本發明之實施型態3之變形例2之半導體晶圓用 Φ 搬運托盤26#之說明圖。 參照圖27 ’半導體晶圓用搬運托盤26 #係由突起部 1〇〇與基底部25p所構成。在基底部25p上載置圖π所說明 之半導體晶圓1 0作為一例,唯此並未予以圖示。而,此 際’设於基底部25p表面之突起部1〇〇會貫通設於半導體 晶圓10之孔部11而如上所述,固定半導體晶圓1〇與基底 部 25p ° • 而’顯示對載置半導體晶圓之基底部25p之表面部分 依照特定之圖案施以柱坑加工之情形。具體上,如圖 26(b)所說明,對朝向重錐體八尺之基底部之表面部分施 以柱坑加工。因此,在重錐體AR之支持構造之部分,呈 現與基底部表面部分接近或接觸之狀態。是故,如上所 述,可抑制半導體晶圓之自重引起之半導體晶圓之墜彎 而加以搬運。 又、,如圖21及圖22所說明,顯示採用對基底部2外設 置貫通部4而藉真空泵直接真空吸附半導體晶圓1之構成 之隋形。且顯不設置引導貫通部5已形成與貫通部4間之 112514.doc -32、 .1309447 路徑之構成。 同時’藉上述真空系18經由吸引用小孔3真空吸附半 導體晶圓用搬運托盤時’可穩定加以保持,並以穩定狀 態吸附半導體晶圓。Referring to Fig. 25(a), in this example, as shown in Fig. 12, in the case where the wafer is provided in the central region or the like, the wafer is formed on the surface of the tray 2#p facing thereto. The pit region of a specific depth of the concave shape is formed so as not to form a pit region on the surface of the tray 2#p which is not provided with the outer peripheral region of the wafer TP, that is, the peripheral region. In other words, the column region 0 is formed on the surface of the tray 2#p which is located further inward than the peripheral region. As shown in FIG. 25(b), as an example, the weight of the movable portion of the 3-axis acceleration sensor is as shown in FIG. Since the body AR is provided with a specific space gap by performing the pit processing on the semiconductor wafer transfer tray 2 #p, 112514.doc -30- 1309447, it is possible to avoid contact with the semiconductor wafer transfer tray 2#p. surface. Therefore, a desired inspection can be performed in the above-described inspection apparatus 30. In the case where the semiconductor wafer transfer tray 2 #p is provided with a penetration portion and is directly vacuum-adsorbed to the semiconductor wafer in the region of the peripheral region of the through-region where the semiconductor wafer is not provided, the semiconductor wafer can be stably adsorbed. Semiconductor wafers. (Variation 1 of Embodiment 3) FIG. 26 is an explanatory view of a transport tray 2#q for a semiconductor wafer according to a modification 1 of the third embodiment of the present invention. Referring to Fig. 26 (a), the semiconductor wafer transfer tray 2 #q is used to perform the pit processing in accordance with the specific pattern on the surface portion of the base portion on which the semiconductor wafer is placed. In the configuration of the semiconductor wafer transfer tray 2#p described in FIG. 25(a), the surface portion of the base portion on which the semiconductor wafer is placed is applied to the entire region where the wafer τρ is provided, for example, the central portion. In the entire portion, the column processing is performed. However, in the region where the wafer TP is provided, the surface portion of the base portion facing the movable portion is subjected to column processing. With this configuration, in the case where the MEMS device is a 3-axis acceleration sensor, as shown in Fig. 26 (b), the pit portion processing can be applied to the surface portion of the base portion facing the heavy cone AR. Therefore, in the portion of the supporting structure of the heavy cone AR, it is in a state of being close to or in contact with the surface portion of the base portion. Therefore, compared with the configuration of the figure, it is possible to suppress the semiconductor wafer from being bent by the self-weight of the semiconductor wafer and transport it. The other points are the same as in Fig. 25. 112514.doc • 31 - 1309447 (Modification 2 of Embodiment 3) In the above-described Embodiment 3 and its modifications, the description will be made regarding the use of the plow state 1 in the transport tray for semiconductor wafers. For the semiconductor wafer, the transport tray is configured by column pit processing. However, the present invention is not limited thereto, and it is of course possible to adopt a configuration in which the column for the semiconductor wafer described in Embodiment 2 is subjected to column pit processing. Fig. 27 is an explanatory view of the Φ transport tray 26# for the semiconductor wafer according to the second modification of the third embodiment of the present invention. Referring to Fig. 27, the semiconductor wafer transfer tray 26 is composed of a projection 1b and a base portion 25p. The semiconductor wafer 10 described with reference to Fig. π is placed on the base portion 25p as an example, and is not shown. In this case, the protrusion 1 provided on the surface of the base portion 25p penetrates through the hole portion 11 of the semiconductor wafer 10, and as described above, the semiconductor wafer 1 and the base portion 25p are fixed. The surface portion on which the base portion 25p of the semiconductor wafer is placed is subjected to column pit processing in accordance with a specific pattern. Specifically, as described in Fig. 26 (b), the surface portion of the base portion facing the eight-foot heavy cone is subjected to column processing. Therefore, in the portion of the supporting structure of the heavy cone AR, it is in a state of being close to or in contact with the surface portion of the base portion. Therefore, as described above, it is possible to suppress the semiconductor wafer from being bent by the self-weight of the semiconductor wafer and transport it. Further, as shown in Fig. 21 and Fig. 22, a configuration in which the semiconductor wafer 1 is directly vacuum-adsorbed by a vacuum pump to the through portion 4 of the base portion 2 is used. Further, the configuration in which the guide penetration portion 5 has formed a path between the 112514.doc -32 and .1309447 between the penetration portion 4 and the passage portion 4 is not shown. At the same time, when the vacuum system 18 vacuum-adsorbs the transfer tray for the semiconductor wafer through the suction small hole 3, it can be stably held, and the semiconductor wafer is adsorbed in a stable state.

又,在上述實施型態所說明之半導體晶圓用搬運托盤 對於貫通部等之加X,雖也可利用鑽頭之機械加工予以 成型’但也可利用裝置之製程予以成型。 圖28係成型圖27所說明之半導體晶圓用搬運托盤之製 程之概略說明圖。 在此,顯示加工半導體晶圓用搬運托盤之背面側用之 製程。 具體上,參照圖28(a) ’為加工托盤之背面側,對8]基 板(Si-Sub),以2個遮罩保護而執行蝕刻。具體上,利用 形成貫通部4用之遮罩MSK1、與形成引導貫通部用之遮 罩MSK2覆蓋基底部25p。 其次,參照圖28(b),在此,對未被遮罩MSK1及遮罩 MSK2覆蓋之Si基板之基底部251?之區域施行乾式蝕刻而 成型貫通部4。而’除去遮罩MSK1。 其次’參照圖28(c),在此’對未被遮罩MSK2覆蓋之 Si基板之基底部25p之區域施行乾式蝕刻而形成引導貫通 部。作為此等2個遮罩之例,在遮罩MSK1可使用通常之 光抗钱劑。又,作為遮罩MSK2,除了聚醯亞胺等之永 久抗餘劑以外,也可使用Si02、SiN、Ti等之硬遮罩。 而’其次,參照圖28(d),將Si基板熱氧化而以矽氧化 '· U25l4.doc -33- 1309447 膜覆蓋基底部25p全體。而,其次’對基底部25p之表面 執行加工處理。 參照圖28(e),對形成柱坑區域之區域以外,以未圖示 之抗触劑遮罩保護而藉濕式蝕刻法蝕刻矽氧化膜。 其次’參照圖28(f),再以矽氧化膜為遮罩,利用所謂 TMAH水溶液濕式蝕刻Si基板之基底部25?,在朝向可動 部之基底部25p表面成型柱坑區域。 而’其次’參照圖28(g) ’以氫氟酸剝離矽氧化膜,即 可成型圖27所說明之半導體晶圓用搬運托盤之基底部 25p。 而,與基底部25p接著而設置突起部1〇〇時,即可成型 半導體晶圓用搬運托盤26#。 藉該製程成型半導體晶圓用搬運托盤時,可提高加工 精度’且可簡易地成型托盤。 (實施型態4) 本發明之實施型態4之半導體晶圓異於上述實施型態 1〜3所說明之半導體晶圓,具有接合玻璃基板之構造。 在如上述加速度感應器等設置有較多貫通孔之裝置中, 為保持裝置之強度’有需要接合玻璃基板等之情形。 而,在本實施型態4中’ m明搬運具有接合玻璃基板之構 造之半導體晶圓之半導體晶圓用搬運托盤。 圖29係本發明之實施型態4之半導體晶圓用搬運托盤 之說明圖。 參,、、、圖29 ’首先,在半導體晶圓i與半導體晶圓用搬 112514.doc -34· 1309447 運托盤間夾入玻璃基板13,以接合半導體晶圓!與破璃 基板la。又,在此所接合之破璃基板“係使用與半導體 晶圓1相同形狀及相同大小。因此,例如半導體晶圓之: 狀為圓形狀之情形,玻璃基板之形狀也使用同樣形狀, 半導體ΒΘ圓之形狀為定向平面或缺口型之情形,對應之 玻璃基板也使用同樣形狀。 本發明之實施型態4之半導體晶圓用搬運托盤2r與圖6 所s兒明之半導體晶圓用搬運托盤2相比,相異之處在於在 基底部之表面側進一步設有後述多孔質層之構成之點、 以及在基底部之背面側至多孔質層間設有貫通部4 #之構 成之點。而,可經由此多孔質層真空吸附玻璃基板u。 在成型於以上所說明之半導體晶圓1之例如3軸加速度 感應器之MEMS裝置中,設有貫通區域,在成型MEMs 裝置之區域中,難以藉該貫通區域直接真空吸附半導體 晶圓1之點雖已說明’但在接合玻璃基板之本規格中,由 於介著玻璃基板’故被認為可真空吸附,並可解決搬運 上之問題。但,玻璃基板通常使用非常薄玻璃,若介著 玻璃基板而直接將晶圓載置於載置台而加以吸附時,玻 璃基板及晶圓將沿著載置台上之吸引用小孔之圖案而變 形’而有不能獲得裝置之正確之測試之問題。但,介著 具有多孔質層之托盤而施行真空吸附時,即可使依存於 吸引用小孔之圖案之吸附力之差保持均勻。 茲說明有關多孔質層之產生。 圖30係有關多孔質層NCS之產生之說明圖》 112514.doc -35· 1309447 為了在單晶石夕基板之基板部2:之一表面側形成多孔質 層NCS之多孔質奈米結晶紗層,施行陽極氧化處理。 參照圖30,在施行陽極氧化處理之際,在作為基板部 利用密封材 ’而構成使 2r之陽極氧化處理對象之表面之部位周圍, 料設置外壁41,將電解液45注入該外壁内側 該處理對象之表面之部位接觸到電解液45。 其次’在電解液45中,將錄電極44配置成朝向基板部 之表面另外,在基板部2r之背面側安裝通電用電極 42而將與通電用電極42連接之導線連接至電流源剔之正 側,並將翻電極44連接至電流源2〇〇之負側。以通電用電 極42為陽極,以鉑電極44為陰極,由電流源將特定電 洲岔度之電/瓜通至通電用電極42與鉑電極44之間持續特 定之通電時間。 藉此種陽極氧化處理’可在基板部以之表面之部位之 外壁41内側形成厚度大致-定之熱絕緣層NCS。又,作 為使用於陽極氧化處理之電解液45,例如使用Μ wt%之 氟化氫水,合液與乙醇以1比1混合之混合液(HF/乙醇溶 液)。作為密封材料,例如可使用使用含氟樹脂構成之密 封材料。 依據該方式可尤I a . 』在基板部2r之表面側形成多孔質奈米結 晶碎層。 介著此夕孔質奈米結晶矽層真空吸附玻璃基板1 a時, 可均勻地吸住與多孔質層接觸之玻璃基板。即’對破續 基板之與夕孔質層接觸之全面施行真空吸附而非對玻壤 112514.doc -36· 1309447 基板之-點施行真空吸附,故*會因依存於吸盤上之吸 引用小孔之圖案之吸附力之差異而引起對玻璃基板及半 導體晶圓之非刻意造成之位移。因此,形成於半導體晶 圓上之各個微小構造體不會受到非刻意造成之位移之影 s故可在半導體晶圓全面獲得穩定而高可靠性之測試 結果。 _、 在此雖5兒明有關以具有貫通區域之3軸加速度 感應器之MEMS裝置為例之情形,但也可同樣地適用於 別的MEMS裝置。 ^,也可對該實施型態4所說明之構成,既可如實施 型態1所說明般設置外壁部,並更穩定地搬運半導體晶 圓,亦可如實施型態2所說明般設置孔部與突起部而嵌^ 半導體晶圓與半導體晶圓用搬運托盤而加以搬運。又, 此情形,在玻璃基板,也有必要設置與半導體晶圓同樣 之孔部而與設在半導體晶圓㈣運㈣侧之突起部相嵌 合0 本次揭*之實施型態在所有之點均僅係舉例說明而不 應視為具有㈣m。本發明之範圍係由中請專利範圍所 揭示而非由上述之說明所揭示,i包含在與申請專利範 圍均等之意義及範圍内之所有之變更。 【圖式簡單說明】 圖1係本發明之實施型態1之檢查裝置3〇之說明圖。 圖2係說明檢查部3 6之概略構成圖。 圖3⑷、(b)係本發明之實施型態!之半導體晶圓用搬運 1125i4.doc •37· 1309447 托盤之說明圖。 之情 圖4(a)、(b)係被搬運臂32搬運至晶圓保持機構μ 形之說明圖。 圖5係晶圓保持機構35之一部分之說明圖。 圖6係利用真空泵18吸附托盤2之情形之說明圖。 圖7係3軸加速度感應器由裝置上面所見之圖。 圖8係3軸加速度感應器之概略圖。Further, in the transfer tray for a semiconductor wafer described in the above embodiment, the addition of X to the through portion or the like may be performed by machining using a drill. However, it may be molded by a process of the apparatus. Fig. 28 is a schematic explanatory view showing a process of molding the transfer tray for a semiconductor wafer described in Fig. 27. Here, the process for processing the back side of the transfer tray for semiconductor wafers is shown. Specifically, referring to Fig. 28(a)' as the back side of the processing tray, etching is performed on the 8] substrate (Si-Sub) by two masks. Specifically, the base portion 25p is covered by the mask MSK1 for forming the through portion 4 and the mask MSK2 for forming the guide through portion. Next, referring to Fig. 28 (b), the region of the base portion 251 of the Si substrate which is not covered by the mask MSK1 and the mask MSK2 is subjected to dry etching to form the through portion 4. And remove the mask MSK1. Next, referring to Fig. 28(c), the region of the base portion 25p of the Si substrate not covered by the mask MSK2 is subjected to dry etching to form a guiding through portion. As an example of these two masks, a conventional light anti-money agent can be used for the mask MSK1. Further, as the mask MSK2, a hard mask such as SiO 2 , SiN or Ti may be used in addition to the permanent anti-reagent such as polyimide. On the other hand, referring to Fig. 28 (d), the Si substrate was thermally oxidized to cover the entire base portion 25p with a film of ruthenium oxidized '· U25l4.doc - 33 - 1309447 . On the other hand, the processing of the surface of the base portion 25p is performed next. Referring to Fig. 28(e), the tantalum oxide film is etched by wet etching using an anti-contact agent mask protection (not shown) other than the region where the pillar region is formed. Next, referring to Fig. 28 (f), the base portion 25 of the Si substrate is wet-etched by a so-called TMAH aqueous solution using a tantalum oxide film as a mask, and a pillar region is formed on the surface of the base portion 25p facing the movable portion. On the other hand, the base portion 25p of the transfer tray for a semiconductor wafer described in Fig. 27 can be formed by peeling off the tantalum oxide film with hydrofluoric acid with reference to Fig. 28(g)'. On the other hand, when the protrusion portion 1 is provided next to the base portion 25p, the semiconductor wafer transfer tray 26# can be formed. When the transfer tray for a semiconductor wafer is molded by this process, the processing accuracy can be improved and the tray can be easily formed. (Embodiment 4) The semiconductor wafer of Embodiment 4 of the present invention has a structure in which a semiconductor wafer is bonded to the semiconductor wafer described in the above Embodiments 1 to 3. In the device in which a large number of through holes are provided, such as the above-described acceleration sensor, it is necessary to bond the glass substrate or the like in order to maintain the strength of the device. In the fourth embodiment, the semiconductor wafer carrying tray having the semiconductor wafer bonded to the glass substrate is transported. Fig. 29 is an explanatory view showing a transport tray for a semiconductor wafer according to Embodiment 4 of the present invention.参,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, With the broken glass substrate la. Further, the glass substrate to be bonded here is "having the same shape and the same size as the semiconductor wafer 1. Therefore, for example, in the case of a semiconductor wafer, the shape of the glass substrate is the same, and the shape of the glass substrate is also the same shape. In the case where the shape of the circle is an orientation flat or a notch type, the same shape is used for the corresponding glass substrate. The semiconductor wafer transfer tray 2r of the embodiment 4 of the present invention and the semiconductor wafer transfer tray 2 of FIG. The difference is that the structure of the porous layer described later is further provided on the surface side of the base portion, and the configuration of the through portion 4 is provided between the back surface side of the base portion and the porous layer. The glass substrate u can be vacuum-adsorbed through the porous layer. In the MEMS device formed of the three-axis acceleration sensor of the semiconductor wafer 1 described above, a through region is provided, and it is difficult to borrow in the region where the MEMs device is formed. The point where the through-region directly vacuum-adsorbs the semiconductor wafer 1 has been described as 'but in the specification of the bonded glass substrate, it is considered to be true due to the glass substrate. Empty adsorption, and can solve the problem of handling. However, the glass substrate usually uses very thin glass. If the wafer is directly placed on the mounting table and adsorbed through the glass substrate, the glass substrate and the wafer will follow the mounting table. The upper suction is deformed by the pattern of the small holes, and there is a problem that the correct test of the device cannot be obtained. However, when the vacuum adsorption is performed through the tray having the porous layer, the pattern depending on the suction small holes can be made. The difference in the adsorption force is kept uniform. The generation of the porous layer is explained. Fig. 30 is an explanatory diagram of the generation of the porous layer NCS. 112514.doc -35· 1309447 For the substrate portion 2 of the single crystal substrate: On one of the surface sides, a porous nanocrystalline crystal layer of a porous layer NCS is formed and anodized. According to FIG. 30, when anodizing is performed, an anodizing of 2r is performed by using a sealing material as a substrate portion. An outer wall 41 is disposed around the surface of the object to be treated, and the electrolyte 45 is injected into the outer surface of the outer wall to contact the electrolyte 45 at the portion of the surface of the object to be treated. In the case of 45, the recording electrode 44 is disposed so as to face the surface of the substrate portion, and the current-carrying electrode 42 is attached to the back surface side of the substrate portion 2r, and the wire connected to the current-carrying electrode 42 is connected to the positive side of the current source, and will be turned over. The electrode 44 is connected to the negative side of the current source 2A. The electrode 42 for energization is used as the anode, and the platinum electrode 44 is used as the cathode. The electric current of the specific electrical conductivity is passed from the current source to the electrode 42 and the platinum electrode. Between 44, a specific energization time is continued. By this kind of anodizing treatment, a heat insulating layer NCS having a thickness substantially constant can be formed inside the outer wall 41 of the surface of the substrate portion. Further, as an electrolytic solution used for anodizing treatment 45. For example, a mixed liquid (HF/ethanol solution) in which 1:1 wt% of hydrogen fluoride water and a mixture of ethanol and ethanol are mixed in a ratio of 1 to 1. As the sealing material, for example, a sealing material composed of a fluorine-containing resin can be used. According to this embodiment, a porous nanocrystalline crystal layer can be formed on the surface side of the substrate portion 2r. When the glass substrate 1 a is vacuum-adsorbed through the porous nanocrystal crystallization layer, the glass substrate in contact with the porous layer can be uniformly sucked. That is, 'vacuum adsorption is applied to the contact between the substrate and the matte layer, and the vacuum adsorption is not applied to the substrate of the glass substrate 112514.doc -36· 1309447. Therefore, it will be small due to the attraction on the suction cup. The difference in the adsorption force of the pattern of holes causes unintentional displacement of the glass substrate and the semiconductor wafer. Therefore, the respective minute structures formed on the semiconductor wafer are not affected by the unintentional displacement, so that stable and highly reliable test results can be obtained in the semiconductor wafer. _. Although a MEMS device having a three-axis acceleration sensor having a through-region is exemplified here, the same can be applied to other MEMS devices. In the configuration described in the fourth embodiment, the outer wall portion may be provided as described in the first embodiment, and the semiconductor wafer may be conveyed more stably. The hole may be provided as described in the embodiment 2. The semiconductor wafer and the semiconductor wafer transfer tray are transported by the projections and the projections. Further, in this case, it is necessary to provide a hole portion similar to that of the semiconductor wafer in the glass substrate, and to be fitted to the protrusion portion provided on the side of the semiconductor wafer (4) (4). They are for illustrative purposes only and should not be considered to have (iv) m. The scope of the present invention is defined by the scope of the invention, and is not intended to BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is an explanatory view showing an inspection apparatus 3 of an embodiment 1 of the present invention. FIG. 2 is a schematic configuration diagram of the inspection unit 36. Figures 3 (4) and (b) are embodiments of the present invention! Handling of semiconductor wafers 1125i4.doc •37· 1309447 Description of the tray. 4(a) and 4(b) are explanatory views of the conveyance arm 32 being conveyed to the wafer holding mechanism μ shape. FIG. 5 is an explanatory diagram of a portion of the wafer holding mechanism 35. Fig. 6 is an explanatory view showing a state in which the tray 2 is sucked by the vacuum pump 18. Figure 7 is a diagram of the 3-axis acceleration sensor as seen from the device above. Figure 8 is a schematic view of a 3-axis acceleration sensor.

圖9係說明受到各軸方向之 、 %又月形之重錐體盥 樑之變形之概念圖。 一、 圖10⑷、(b)係對各軸所設之惠斯通電橋之電路構 圖。 圖11係本發明之實施型態1之變形例1之半導體晶圓用 搬運托盤2#之說明圖。 圖12係成型於—般的主道辦曰同 奴的牛導體日日圓1之複數晶片Tp之說 明圖。 ° 圖係本發明之實施型態1之變形例1之另一半導體晶 圓用搬運托盤2# a之說明圖。 圖14(3)、(b)係本發明之實施型態1之變形例2之半導體 晶圓用搬運托盤之說明圖。 圖15(a) (b)係對應於定向平面型晶圓之半導體晶圓用 搬運托盤之說明圖。 圖6(a) (b)係對應於本發明之實施型態1之變形例4之 疋向平面里曰曰圓之半導體晶圓用搬運托盤之說明圖。 圖17係本备明之實施型態2之半導體晶圓1 〇之說明 H2514.doc 08- 1309447 圖1 8係本發明之實施型態2之半導體晶圓用搬運托盤 - 之說明圖。 . 圖19(a)〜(d)係成型圖7及圖8所說明之3軸加速度感應器 之際之製程之概略說明圖。 圖20係本發明之實施型態2之另—半導體晶圓1〇 #之 ' .說明圖。 • 圖21係本發明之實施型態2之變形例1之半導體晶圓用 搬運托盤27之說明圖。 圖2 2係本發明之實施型態2之變形例1之別的半導體晶 圓用搬運托盤28之說明圖。 圖23係在電子束照射器之照射窗使用隔膜構造之情形 - 之說明圖。 圖24係有別於圖8所說明之3軸加速度感應器之別的3 軸加速度感應器之概略圖。 馨圖25(a)、(b)係本發明之實施型態3之半導體晶圓用搬 運托盤2 # p之說明圖。 圖26(a) ' (b)係本發明之實施型態3之變形例1之半導體 晶圓用搬運托盤2 # q之說明圖。 圖27係本發明之實施型態3之變形例2之半導體晶圓用 搬運托盤26 #之說明圖。 圖28(a)〜(h)係成型圖27所說明之半導體晶圓用搬運托 盤之製程之概略說明圖。 圖29係本發明之實施型態4之半導體晶圓用搬運托盤 112514.doc -39- 1309447 之說明圖。 圖30係有關多孔質層NCS之產生之說明圖。Fig. 9 is a conceptual view showing the deformation of a heavy pyramidal beam which is subjected to the respective axial directions and %. 1. Figures 10(4) and (b) show the circuit configuration of the Wheatstone bridge for each axis. Fig. 11 is an explanatory view showing a transport tray 2# for a semiconductor wafer according to a first modification of the first embodiment of the present invention. Fig. 12 is an explanatory view of a plurality of wafers Tp formed on the main conductor of the same day. Fig. 1 is an explanatory view of another semiconductor wafer carrying tray 2#a according to the first modification of the first embodiment of the present invention. Fig. 14 (3) and (b) are explanatory views of a transport tray for a semiconductor wafer according to a second modification of the first embodiment of the present invention. Fig. 15 (a) and (b) are explanatory views of a transfer tray for a semiconductor wafer corresponding to an oriented planar wafer. Fig. 6 (a) and (b) are explanatory views of a transport tray for a semiconductor wafer which is rounded in a plane in a modified example 4 of the first embodiment of the present invention. Fig. 17 is a view showing a semiconductor wafer 1 according to the embodiment 2 of the present invention. H2514.doc 08- 1309447 Fig. 1 is an explanatory view of a transfer tray for a semiconductor wafer according to an embodiment 2 of the present invention. 19(a) to (d) are schematic explanatory views showing a process of molding the three-axis acceleration sensor described with reference to Figs. 7 and 8. Figure 20 is an illustration of another embodiment of the semiconductor wafer 1 of the embodiment of the present invention. Fig. 21 is an explanatory view showing a transfer tray 27 for a semiconductor wafer according to a first modification of the second embodiment of the present invention. Fig. 2 is an explanatory view of another semiconductor wafer carrying tray 28 according to the first modification of the second embodiment of the present invention. Fig. 23 is an explanatory view showing a case where a diaphragm structure is used in an irradiation window of an electron beam illuminator. Fig. 24 is a schematic diagram showing another three-axis acceleration sensor different from the three-axis acceleration sensor illustrated in Fig. 8. Figs. 25(a) and (b) are explanatory views of the transport tray 2 #p of the semiconductor wafer according to the third embodiment of the present invention. (b) is an explanatory view of the semiconductor wafer transfer tray 2 #q according to the first modification of the third embodiment of the present invention. Fig. 27 is an explanatory view showing a transfer tray 26 # for a semiconductor wafer according to a second modification of the third embodiment of the present invention. Fig. 28 (a) to (h) are schematic explanatory views showing the process of molding the carrier tray for a semiconductor wafer described with reference to Fig. 27. Fig. 29 is an explanatory view of a transfer tray for a semiconductor wafer of the fourth embodiment of the present invention, 112514.doc - 39 - 1309447. Fig. 30 is an explanatory view showing the generation of the porous layer NCS.

【主要元件符號說明】 1、1 #、10、10# 2、2# 、2#a、2#p、 2 # q 、 2r 、 20 、 21 、 25p 、 26〜28 3 4 、 11 、 11# 17 18 30 32 33 34 35 36 37 50 51 55 80 100 半導體晶圓 半導體晶圓用搬運托盤 吸引用小孔 孔部 管路 真空泵 檢查裝置 搬運臂 轉子部 吸盤 晶圓保持機構 檢查部 對準裝置 探針卡 探針 測試頭 照射窗 突起部 112514.doc -40-[Description of main component symbols] 1, 1 #, 10, 10# 2, 2#, 2#a, 2#p, 2 # q, 2r, 20, 21, 25p, 26~28 3 4 , 11 , 11# 17 18 30 32 33 34 35 36 37 50 51 55 80 100 Semiconductor wafer semiconductor wafer transfer tray suction small hole section line Vacuum pump inspection device Transfer arm rotor part suction cup wafer holding mechanism inspection part alignment device probe Card probe test head illumination window protrusion 112514.doc -40-

Claims (1)

13〇辦23〇3〇4號專利申請案 中文申請專利範圍替換本(98年1月)-—___ 十、申請專利範圍: |背年/月件日修(更)正本 I 種半導體晶圓用搬運托盤,盆俜巷罟石 古,* 八係載置至少成型1個具 有可動部之微小構造體之半導體晶圓者,且包含: ^底部,其係在載置前述半導體晶圓之表面側設有防 止前述半導體晶圓之偏移用之偏移防止機構,在搬運之 際背面側被真空吸附者; 、珂述基底部具有設在未成型前述半導體晶圓之微小構 造體之周邊區域之貫通部; 珂述半導體晶圓係經由前述貫通部而與前述基底部一 起被真空吸附。 2·如請求項1之半導體晶圓用搬運托盤,其中 如述半導體晶圓具有孔部,且進一步包含: 保持突起部,其係設於前述基底部之表面側,構成前 述偏移防止機構並嵌合於前述.孔部者。 3.如請求項2之半導體晶圓用搬運托盤,其中前述孔部設 於未成型前述微小構造體之區域。 4·如請求項2之半導體晶圓用搬運托盤,其中 前述半導體晶圓具有複數之前述孔部; 前述基底部進一步包含: 複數之前述保持突起部’其係分別對應於前述複數之 孔部而被設置者。 5·如請求項2之半導體晶圓用搬運托盤,其中前述孔部及 前述保持突起部之形狀剖面係形成為多角形狀。 6,如請求項1至5中任一項之半導體晶圓用搬運托盤,其中 ^25141-980115^ 1309447 前述基底部之表面側具有特定深度之柱坑區域,其係對 =於比未成型前述微小構造體之前述半導體晶圓之周邊 區域更内側之區域而被設置,II柱坑加工形成為凹型。 7.如請求項6之半導體晶圓用搬運托盤,其中形成於前述 基底部之表面側之柱坑區域係對向於位在前述半導體晶 圓中成型有前述微小構造體之可動部之區域而被設置。 月长項2之半導體晶圓用搬運托盤,其中前述半導體 曰曰圓至少成型1個具有設有成為可動區域之貫通區域之 可動部之微小構造體’前述孔部係藉形成貫通區域之步 驟同時被成型。 9·如凊求項1之半導體晶圓用搬運托盤,其中前述半導體 =用搬運㈣之大小係小於前料㈣晶圓而大於形 成前述微小構造體之區域。 10.如明求項1之半導體晶圓用搬運托盤,其中前述半導體 晶圓用搬運托盤係沿著執行真线附用之真空吸 之形狀而被真空吸附; 如述基底部之背面具有對應於前述真空吸附導件而言; 置之凹部,以擴大在前述真空吸附導件與前述背面間相 真工硬附之吸附面積。 η·如請求項1之半導體晶圓用搬運托盤,其中進—步包含 外壁部,其係與前述基底部連結,構成在裁置前述半導 體晶圓之面沿著前述半導體晶圓之外周端部之至少一部 分區域設置之前述偏移防止機構者。 α如請求項η之半導體晶圓用搬運托盤,其中前述基底部 1125I4J-980jJ5.doc 1309447 之表面侧具有特定深度之柱坑區域,其係對向於比未成 型則述微小構造體之前述半導體晶圓之周邊區域更内側 之區域而被設置,藉柱坑加工形成凹型。 13_如明求項12之半導體晶圓用搬運托盤,其中形成於前述 基底部之表面側之柱坑區域係對向於位在前述半導體晶 圓中成型有前述微小構造體之可動部之區域而被設置。 14. 如明求項丨丨至丨3中任一項之半導體晶圓用搬運托盤, 其中 刖述半導體晶圓具有定向平面(〇rientati〇n 或缺口 (notch)區域; 月|J述外壁部係對應於前述半導體晶圓之前述定向平面 或缺口區域之外周端部之至少一部分而被設置。 15. —種半導體晶圓用搬運托盤,其係載置至少成型1個具 有可動部之微小構造體之半導體晶圓者;且 前述半導體晶圓係與設在與前述半導體晶圓用搬運托 盤之間之玻璃基板接合,並介隔前述玻璃基板被搬運; 刚述半導體晶圓用搬運托盤包含基底部,其係在載置 介隔前述玻璃基板之前述半導體晶圓之表面側設有多孔 質層’在搬運之際背面側被真空吸附者; 鈿述基底部具有達到前述多孔質層之貫通孔; 前述半導體晶圓係經由前述多孔質層而與前述基底部 一起被真空吸附。 16. 如請求項15之半導體晶圓用搬運托盤,其中 前述半導體晶圓用搬運托盤係在載置前述半導體晶圓 1125141-980115.doc 1309447 之表面側設置防止前述半導體晶圓之偏移之偏移防止機 構。 17. 請求項15之半導體晶圓用搬運托盤,其中 前述半導體晶圓及玻璃基板具有孔部; 月’J述基底部具有保持突起部’其係構成前述偏移防止 機構且嵌合於前述孔部者。 18. 如請求項17之半導體晶圓用搬運托盤,其中前述孔部設 於未成型前述微小構造體之區域。 19. 如請求項17之半導體晶圓用搬運托盤,其中 前述半導體晶圓及玻璃基板具有複數之前述孔部; 前述基底部具有複數之前述保持突起部,其係分別對 應於前述複數之孔部而被設置者。 20. 如叫求項17之半導體晶圓用搬運托盤,其中前述孔部及 前述保持突起部之形狀剖面形成為多角形狀。 21. 如請求項17之半導體晶圓用搬運托盤,其中前述半導體 B曰圓至少成型1個具有設有成為可動區域之貫通區域之 可動部之微小構造體,前述孔部係藉形成貫通區域之步 驟同時被形成。 22. 如請求項15至21中任一項之半導體晶圓用搬運托盤,其 中岫述半導體晶圓用搬運托盤係小於前述半導體晶圓及 玻璃基板而大於形成前述微小構造體之區域。 23·如請求項15之半導體晶圓用搬運托盤,其中進一步包含 外壁部,其係與前述基底部連結,構成在介隔前述玻璃 基板而載置則述半導體晶圓之面沿著前述半導體晶圓及 1125141-980115.doc 1309447 玻璃基板之外周端部之至少一部分區域設置之前述偏移 防止機構者。 24. 如請求項23之半導體晶圓用搬運托盤,其中 前述半導體晶圓及玻璃基板具有定向平面或缺口區 域; 前述外壁部係對應於前述半導體晶圓之前述定向平面 或缺口區域之外周端部之至少一部分而被設置。 25. 如請求項15之半導體晶圓用搬運托盤,其中前述多孔質 層係奈米結晶矽。13〇23〇3〇4 Patent Application Chinese Application Patent Renewal (January 1998)--___ X. Patent Application: | Back Year/Monthly Repair (More) Original I Semiconductor Wafer With the handling tray, the basin 俜 罟 古 ,, * 八 载 载 载 载 载 载 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体The side is provided with an offset preventing mechanism for preventing the offset of the semiconductor wafer, and is vacuum-adsorbed on the back side when transporting; and the base portion is provided in a peripheral region of the minute structure in which the semiconductor wafer is not formed. The through-wafer portion; the semiconductor wafer is vacuum-absorbed together with the base portion via the through portion. 2. The semiconductor wafer transfer tray according to claim 1, wherein the semiconductor wafer has a hole portion, and further comprising: a holding protrusion portion that is provided on a surface side of the base portion to constitute the offset preventing mechanism Fitted to the aforementioned hole. 3. The transfer tray for a semiconductor wafer according to claim 2, wherein the hole portion is provided in a region where the minute structure is not formed. 4. The semiconductor wafer transfer tray according to claim 2, wherein the semiconductor wafer has a plurality of the hole portions; and the base portion further includes: the plurality of the holding protrusions ' respectively corresponding to the plurality of holes Set by. 5. The carrier wafer for a semiconductor wafer according to claim 2, wherein the hole portion and the shape of the holding protrusion are formed in a polygonal shape. The carrier tray for a semiconductor wafer according to any one of claims 1 to 5, wherein the surface side of the base portion has a pit region of a specific depth, and the pair is opposite to the unformed The peripheral region of the semiconductor wafer of the microstructure is provided on the inner side of the region, and the II pillar is formed into a concave shape. 7. The carrier tray for a semiconductor wafer according to claim 6, wherein the pillar region formed on the surface side of the base portion faces a region in which the movable portion of the microstructure is formed in the semiconductor wafer. be set to. In the transport tray for a semiconductor wafer of the moon-length item 2, at least one of the semiconductor domes having a movable portion having a movable portion that is a through region of the movable region is formed, and the hole portion is formed by the step of forming the through region. Formed. 9. The carrier wafer for semiconductor wafer according to claim 1, wherein the semiconductor (transport) (four) is smaller in size than the pre-material (four) wafer and larger than the region in which the micro-structure is formed. 10. The transfer tray for a semiconductor wafer according to claim 1, wherein the transfer tray for the semiconductor wafer is vacuum-adsorbed along a shape of vacuum suction for performing a true line; and the back surface of the base portion has a corresponding In the case of the vacuum adsorption guide; a recess is formed to enlarge the adsorption area of the vacuum adsorption guide and the front surface. The semiconductor wafer transfer tray of claim 1, wherein the step further comprises an outer wall portion connected to the base portion, and configured to cut the surface of the semiconductor wafer along an outer peripheral end of the semiconductor wafer The aforementioned offset prevention mechanism of at least a portion of the area is provided. The carrier tray for semiconductor wafer according to claim n, wherein the surface side of the base portion 1125I4J-980jJ5.doc 1309447 has a pit region of a specific depth, which is opposite to the semiconductor of the microstructure described below. The peripheral area of the wafer is disposed on the inner side of the area, and is formed into a concave shape by the column pit processing. The carrier wafer for semiconductor wafer according to claim 12, wherein the pillar region formed on the surface side of the base portion is opposed to a region in which the movable portion of the microstructure is formed in the semiconductor wafer And is set. 14. The semiconductor wafer carrying tray according to any one of the preceding claims, wherein the semiconductor wafer has an orientation plane (〇rientati〇n or a notch region; Provided to at least a part of the outer peripheral end portion of the orientation flat surface or the notch region of the semiconductor wafer. 15. A semiconductor wafer transfer tray in which at least one minute structure having a movable portion is formed The semiconductor wafer is bonded to a glass substrate provided between the semiconductor wafer transfer tray and transported through the glass substrate; the semiconductor wafer transfer tray includes a substrate a portion in which a porous layer is provided on the surface side of the semiconductor wafer on which the glass substrate is interposed, and a vacuum layer is adsorbed on the back side of the semiconductor wafer. The base portion has a through hole that reaches the porous layer. The semiconductor wafer is vacuum-adsorbed together with the base portion via the porous layer. 16. The carrier wafer for a semiconductor wafer according to claim 15 In the above-described semiconductor wafer transfer tray, an offset preventing mechanism for preventing the offset of the semiconductor wafer is provided on the surface side of the semiconductor wafer 1125141-980115.doc 1309447. 17. The semiconductor wafer of claim 15 In the transport tray, the semiconductor wafer and the glass substrate have a hole portion; and the base portion has a holding protrusion portion constituting the offset preventing mechanism and is fitted to the hole portion. 18. In the transport tray for a semiconductor wafer, the hole portion is provided in a region where the microstructure is not formed. 19. The semiconductor wafer transfer tray according to claim 17, wherein the semiconductor wafer and the glass substrate have a plurality of the holes The base portion has a plurality of the holding protrusions, which are respectively provided corresponding to the plurality of holes. The semiconductor wafer carrier tray of claim 17, wherein the hole portion and the holding protrusion are provided. The shape of the portion is formed into a polygonal shape. 21. The carrier tray for a semiconductor wafer according to claim 17, wherein the semiconductor B At least one micro-structure having a movable portion that is a through-region of the movable region is formed in a circle, and the hole portion is formed simultaneously by forming a through-region. 22. The semiconductor according to any one of claims 15 to 21 In the wafer transfer tray, the semiconductor wafer transfer tray is smaller than the semiconductor wafer and the glass substrate, and is larger than the region in which the microstructure is formed. 23. The semiconductor wafer transfer tray according to claim 15, wherein further The outer wall portion is connected to the base portion, and the surface of the semiconductor wafer is placed along the surface of the semiconductor wafer and the outer peripheral end portion of the glass substrate of the 1125141-980115.doc 1309447 glass substrate. The aforementioned offset prevention mechanism of a part of the area setting. 24. The semiconductor wafer carrier tray of claim 23, wherein the semiconductor wafer and the glass substrate have an orientation flat or a notched region; and the outer wall portion corresponds to the outer peripheral end of the orientation plane or the notch region of the semiconductor wafer At least part of it is set. 25. The transfer tray for a semiconductor wafer according to claim 15, wherein the porous layer is a nanocrystalline ruthenium. 1125141-980115.doc 1309447 七、指定代表圖: (一) 本案指定代表圖為:第(3 )圖。 (二) 本代表圖之元件符號簡單說明: 1 半導體晶圓 2 半導體晶圓用搬運托盤 2b 外壁部 2c 基底部1125141-980115.doc 1309447 VII. Designated representative map: (1) The representative representative of the case is: (3). (2) A brief description of the component symbols of this representative diagram: 1 Semiconductor wafer 2 Handling tray for semiconductor wafer 2b Outer wall portion 2c Base bottom 八、本案若有化學式時,請揭示最能顯示發明特徵的化學式: (無)8. If there is a chemical formula in this case, please disclose the chemical formula that best shows the characteristics of the invention: (none) 112514.doc112514.doc
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