JP5434037B2 - Manufacturing method of semiconductor sensor and manufacturing method of piezoresistive element - Google Patents

Description

  The present invention relates to a method for manufacturing a piezoresistive element. The piezoresistive element according to the present invention can be applied to manufacture of a semiconductor sensor or the like that detects a change in physical quantity, and can be applied particularly to manufacture of a semiconductor sensor that detects acceleration or pressure.

  As one method of processing a semiconductor, there is a method of diffusing impurities such as boron (element symbol: B) and phosphorus (element symbol: P) into the semiconductor. By diffusion of impurities, for example, an active element such as a transistor or a resistance element such as a piezoresistive element can be formed. As a result, various semiconductor products can be manufactured. Semiconductor products include semiconductor sensors that apply MEMS (Micro Electro Mechanical Systems) technology (see, for example, Patent Document 1).

  Methods for diffusing impurities into semiconductors are mainly classified into ion implantation methods and thermal diffusion methods. The ion implantation method is a technique in which atoms or molecules of impurities to be diffused are ionized to give energy of several MeV and accelerated to be implanted into a semiconductor. This method can accurately control the amount of ion implantation, the depth of ion implantation, and the like, and can reduce variations in diffusion. However, an apparatus for performing ion implantation is very expensive and causes an increase in manufacturing cost of semiconductor products. Further, since ions having an energy of several MeV are implanted into the semiconductor, the ions collide with the atoms constituting the semiconductor, so that the semiconductor crystal is damaged and crystal defects are caused. For this reason, using an ion implantation method for manufacturing a sensor element that detects acceleration, pressure, and the like by physical displacement causes deterioration in the strength of the sensor element. For this reason, reliability and stability are reduced (for example, see Non-Patent Document 1).

  On the other hand, in the thermal diffusion method, an impurity source containing B, P, or the like is exposed to a semiconductor, a layer in which the impurity is diffused is formed near the surface of the semiconductor, and then a heat treatment is performed to remove the impurity diffused near the surface. In this technique, impurities are further diffused by being moved into the semiconductor to form a diffusion region. The thermal diffusion method is more advantageous than the ion implantation method in terms of manufacturing cost in that an expensive apparatus such as an apparatus for performing ion implantation is not required. However, when the impurity source is exposed to the semiconductor, it has been almost impossible to control the concentration of the impurity diffused on the surface of the semiconductor below the solid solubility limit. For this reason, the concentration of impurities on the surface of the diffusion region formed by the heat treatment has to be high.

For example, Patent Document 3 discloses that when forming a piezoresistive element of a semiconductor acceleration sensor, a semiconductor substrate is placed in a diffusion furnace and B is supplied in an atmosphere of 1000 to 1200 ° C. The impurity concentration in the vicinity of the surface of the diffusion region of the piezoresistive element formed in this way exceeds 1 × 10 ²⁰ atms / cm ³ . However, as disclosed in Patent Document 2, a preferable impurity concentration as a piezoresistive element is 1 × 10 ¹⁸ atms / cm ³ from the viewpoint of a small characteristic change with respect to temperature and a large resistance value. It is known that the value is lower than ²⁰ atms / cm ³ .

U. M. Mescheder, W. Kronast, N. Naychuk, "Reliability investigations in micromechanical devices", Sensors and Actuators A, Volume 110 (2004), pp. 150-156 JP 2003-101033 A JP-A-8-122361 (paragraph 0031) JP-A-1-229976 (page 547, lower left column)

  The present invention provides a method for manufacturing a semiconductor sensor, a method for manufacturing a piezoresistive element, and the like in which the surface concentration of the impurity is controlled to be low after the impurity is diffused into the semiconductor using a thermal diffusion method.

  As one embodiment of the present invention, a mask having an opening is formed on a semiconductor substrate, the semiconductor substrate exposed through the opening is exposed to an impurity source to form an impurity diffusion layer, and the impurity-containing oxide is formed by oxidizing the impurity diffusion layer. A diffusion region for forming a piezoresistive element by forming a layer, removing at least a part of the impurity-containing oxide layer, and diffusing impurities in the impurity diffusion layer after removing the impurity-containing oxide layer into the semiconductor substrate And a flexible part including a piezoresistive element and a frame part connected to the flexible part are formed.

  The impurity diffusion layer is oxidized to form an impurity-containing oxide layer, and after removing the impurity-containing oxide layer, the impurities in the impurity diffusion layer are diffused into the semiconductor substrate. The surface concentration can be controlled to a low concentration.

  The temperature for forming the impurity-containing oxide layer may be lower than the temperature for forming the piezoresistive element. Thereby, when forming an impurity containing oxide layer, it can suppress that the amount of impurities diffused inside a semiconductor substrate increases.

  For example, the temperature for forming the impurity-containing oxide layer can be 750 ° C. or higher and 800 ° C. or lower, and the temperature for forming the diffusion region can be 900 ° C. or higher and 1100 ° C. or lower. When the temperature is lower than 750 ° C., formation of the impurity-containing oxide layer is not promoted, and when the temperature is higher than 800 ° C., the amount of impurities diffused into the semiconductor substrate increases. When the temperature is lower than 900 ° C., the formation of the diffusion region is not promoted. When the temperature is higher than 1100 ° C., the amount of impurities diffused into the semiconductor substrate increases, and the impurity concentration on the surface may be lowered.

  The impurity source may be boron tribromide, and the impurity diffusion layer may be formed at a temperature of 700 ° C. or higher and 900 ° C. or lower. Since boron tribromide is a gas, the impurity diffusion layer and the impurity-containing oxide can be formed continuously by controlling the gas supply to the diffusion furnace. If the temperature is lower than 700 ° C., it takes time to form the impurity diffusion layer. If the temperature is higher than 900 ° C., impurities diffuse into the semiconductor substrate. It is preferable to form the impurity diffusion layer at a temperature not higher than ° C.

The impurity concentration on the surface of the diffusion region may be 1 × 10 ¹⁷ atoms / cm ³ or more and 1 × 10 ¹⁹ atoms / cm ³ or less. Thereby, a piezoresistive element having a good resistance value and temperature change characteristics can be formed using the diffusion region.

  According to the present invention, it is possible to control the surface concentration of impurities diffused into the semiconductor using a thermal diffusion method to a low concentration. Thereby, a piezoresistive element with good temperature characteristics can be manufactured at low cost. As a result, the manufacturing cost of a semiconductor sensor using a piezoresistive element having good temperature characteristics can be reduced. Therefore, it can be suitably used as a sensor element that detects acceleration, pressure, and the like by physical displacement.

  The best mode for carrying out the present invention will be described below as embodiments and examples with reference to the drawings. The present invention is not limited to the following embodiments and examples, and can be expanded and modified. The expanded and modified embodiments and examples are also included in the gist of the present invention.

(Embodiment 1)
FIG. 1 is a flowchart showing an example of a semiconductor processing procedure according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view showing the state of the semiconductor in each step of FIG. 1 when a semiconductor substrate or the like is used as the semiconductor to be processed.

(Preparation of semiconductor)
FIG. 2A shows a cross section of the semiconductor 201. The semiconductor 201 is subjected to the processing according to the first embodiment of the present invention. By performing the processing procedure of FIG. 1, finally, a diffusion region is formed in a region from the upper surface of the semiconductor 201 to a predetermined inside. At least the upper surface of the semiconductor 201 is silicon. The semiconductor 201 may be a single crystal of silicon. Alternatively, the semiconductor may be the uppermost layer of a semiconductor substrate having a stacked structure composed of a plurality of layers. For example, the semiconductor substrate may be an SOI (Silicon on Insulator) substrate in which silicon, silicon oxide, and silicon are stacked from the upper surface. The semiconductor substrate may be one in which silicon is formed on a glass substrate. Note that the thickness and size of the semiconductor 201 are not particularly limited, and can be arbitrarily selected depending on the application, function, and the like. Further, an element such as a transistor may be already formed in the semiconductor 201. The position and range in the semiconductor where the diffusion region should be formed may be determined by a mask or the like (see Embodiments 2 and 3 described later).

(Formation of impurity diffusion layer)
As the processing in step S101, the impurity source is exposed to at least the upper surface of the semiconductor 201 to form an impurity diffusion layer. In this case, the time required for forming the impurity diffusion layer can be shortened by diffusing in a heated environment. In order to expose the impurity source to the surface of the semiconductor 201, a liquid obtained by dissolving a compound containing an impurity in a solvent or the like is applied to the surface of the semiconductor 201 by spin coating or the like and then placed in a diffusion furnace. Then raise the temperature in the diffusion furnace. Alternatively, instead of applying the liquid, a solid containing impurities may be disposed in the vicinity of the semiconductor in contact with the surface of the semiconductor in the diffusion furnace. Further, a gas containing impurities may be supplied to the diffusion furnace without performing processing such as application of impurities on the surface of the semiconductor 201. When boron is used as the impurity, BBr ₃ (boron tribromide) can be used as the gas containing the impurity. In addition, phosphorus, arsenic, or the like can be used as another impurity.

When BBr ₃ is used as the impurity source, the temperature in the diffusion furnace is preferably in the range of 700 ° C. or higher and 900 ° C. or lower. If the temperature is lower than 700 ° C., it takes a long time to form the impurity diffusion layer. If the temperature is higher than 900 ° C., boron diffuses into the semiconductor, and boron is finally formed in the diffusion region. This is because the concentration becomes high. The flow rate of BBr ₃ can be 28 milligrams or more and 110 milligrams or less per minute. If necessary, other gases, for example, may be mixed with any one or more of N 2 and _(nitrogen) O ₂ and _(oxygen). For example, N ₂ is introduced into the diffusion furnace at a flow rate of 5 slm (standard liter per minute) to 20 slm and O ₂ is introduced at a flow rate of 0 sccm (standard cubic centimeter per minute) to 270 sccm. The time for which the semiconductor is exposed to the impurity source can be 5 minutes or longer and 60 minutes or shorter.

Through the above processing, impurities are deposited on the upper surface of the semiconductor. FIG. 2B shows a state in which impurities are deposited on the upper surface of the semiconductor 201 and the layer 202 is formed. Impurities exist exclusively in the layer 202 away from the semiconductor 201, but as the boundary between the layer 202 and the semiconductor 201 is approached, the frequency of bonding of semiconductor atoms and impurities increases. That is, a state in which semiconductor atoms and impurities are diffused is obtained, and an impurity diffusion layer is formed. For example, when boron is used as the impurity, the boron concentration on the upper surface of the layer 202 is about 3.5 × 10 ²² atms / cm ³ , and the boron concentration at the boundary between the layer 202 and the semiconductor 201 is When silicon is used as 201, the solid solution limit is about 2.5 × 10 ²¹ atoms / cm ³ . Note that the silicon concentration at the boundary between the layer 202 and the semiconductor 201 is about 5 × 10 ²² atms / cm ³ . The distance from the boundary between the layer 202 and the semiconductor 201 to the boron concentration of about 3.5 × 10 ²² atms / cm ³ is usually 50 nm or less, although it depends on conditions. Of the portion of the layer 202, the portion from the boundary with the semiconductor 201 until the boron concentration becomes about the above 3.5 × 10 ²² atms / cm ³ is referred to as an impurity diffusion layer.

FIG. 2B is a graph (boron profile) showing a change in impurity concentration according to the depth from the surface of the impurity diffusion layer in the layer 202 in the state shown in FIG. By exposing the semiconductor 201 to impurities in a diffusion furnace, the boron concentration exceeds 1 × 10 ²⁰ atms / cm ³ on the upper surface of the impurity diffusion layer as described above. In addition, as the impurity diffusion layer moves from the upper surface toward the inside of the semiconductor 201, the impurity concentration rapidly decreases.

In the presence of O ₂ , boron silicate glass (B ₂ O ₃ + SiO ₂ ) may be formed on the impurity diffusion layer depending on the conditions of step S101.

(Formation of impurity-containing oxide layer)
As a process of step S102, the impurity diffusion layer is oxidized. For example, O ₂ is supplied at a predetermined flow rate in a heating environment in a diffusion furnace. For example, the flow rate is 5 slm or more and 20 slm or less. If necessary, it may be performed diluted with N _2. In order to prevent the impurities from diffusing into the semiconductor, the temperature in the diffusion furnace is preferably not so high. For example, the temperature is lower than that in step S104, which will be described later, and is set to 750 ° C. or higher and 800 ° C. or lower. The time length of the oxidation treatment is about 30 minutes to 150 minutes. This is because if the temperature is lower than 750 ° C., it takes time to oxidize and impurities diffuse, and if the temperature is higher than 800 ° C., the diffusion proceeds.

The layer 202 is oxidized by the process of step S102. As a result, an impurity-containing oxide layer made of semiconductor oxide and containing impurities is formed in the impurity diffusion layer. In general, the impurity-containing oxide layer is formed on the upper surface of the impurity diffusion layer. The impurity-containing oxide layer contains impurities at a high concentration (generally 1 × 10 ²⁰ atms / cm ³ or more, particularly 1 × 10 ²¹ atms / cm ³ or more). The heat treatment in step S102 may be performed in the same diffusion furnace as in step S101 or in a different diffusion furnace. It is not necessary to move the semiconductor 201 or the like in the same diffusion furnace. Therefore, the time required for the entire processing can be shortened. In the case where the same diffusion furnace is used, the impurity source is not present in the diffusion furnace in the process of step S102. FIG. 2C shows a state in which the impurity-containing oxide layer 203 is formed on the upper surface of the impurity diffusion layer 202. As shown in FIG. 2B, the impurity concentration on the upper surface of the impurity diffusion layer 202 in FIG. 2B is high. Since the upper surface of the impurity diffusion layer 202 in FIG. 2B is oxidized, the impurity concentration of the impurity-containing oxide layer 203 is generally set to an impurity diffusion layer other than the impurity-containing oxide layer 203. It becomes higher than the impurity concentration of 202.

(Removal of impurity-containing oxide layer)
As a process of step S103, at least a part of the impurity-containing oxide layer formed in step S102 is removed. The impurity-containing oxide layer is removed by etching. In order to control the impurity concentration in the final impurity diffusion layer to be low, it is preferable to remove all of the impurity-containing oxide layer. However, part of the impurity-containing oxide layer may remain depending on etching conditions. Etching can be performed by appropriately selecting dry etching or wet etching. For example, if wet etching is performed, the semiconductor is taken out of the diffusion furnace and treated with 3% HF solution for 10 minutes. If HF liquid is used, even if boron silicate glass is formed, it can be removed. FIG. 2D illustrates a cross section of the semiconductor 201 after the impurity-containing oxide layer 203 illustrated in FIG.

(Heat treatment for impurity diffusion)
As the processing in step S104, semiconductor heat treatment (drive-in diffusion processing) is performed. The semiconductor 201 is placed in a diffusion furnace, heated to 900 ° C. or higher and 1100 ° C. or lower, and placed for several hours such as about 3 hours. In this case, the flow rate of O ₂ may be 5 slm or more and 20 slm or less, and dilution may be performed with N ₂ as necessary. Thereby, the diffusion region 204 is formed. The diffusion furnace in this case may be the same diffusion furnace used in steps S101 and S102. Alternatively, a different diffusion furnace may be used. When the same diffusion furnace is used, the process of step S104 is performed without an impurity source. By this heat treatment, impurities are further diffused into the semiconductor 201. Thereby, the impurity concentration on the surface of the semiconductor on which the impurity diffusion layer is formed is reduced. FIG. 2E illustrates a cross section of the semiconductor 201 after the semiconductor 201 in FIG. The thickness of the impurity diffusion layer 202 in FIG. 2D increases and the impurity concentration decreases. Thereby, the diffusion region 204 is formed on the surface of the semiconductor 201. FIG. 2E shows an example of a boron profile in the state shown in FIG. By appropriately setting the formation of the impurity-containing oxide layer 203 in step S102 and the heat treatment conditions in step S104, the impurity concentration on the surface of the diffusion region 204 can be controlled. As a result, as shown in FIG. 2 (e), it can be controlled to 1 × 10 ¹⁹ atms / cm ³ or less and 1 × 10 ¹⁷ atms / cm ³ or more. Therefore, it can be controlled to 1 × 10 ¹⁸ atoms / cm ³ , which is a surface impurity concentration preferable as a piezoresistive element.

(Surface etching)
Note that when the process of step S104 is performed in the presence of oxygen, an oxide is formed on the surface of the impurity diffusion layer. This oxide contains an impurity, and the impurity may further diffuse into the semiconductor after the manufacture of the product or the like, resulting in a change in resistance value or the like. Therefore, this oxide may be removed by etching. For example, the treatment is performed with 3% HF solution for 5 minutes.

  Since the impurity-containing oxide layer 203 contains impurities at a high concentration, the removal of the impurity-containing oxide layer 203 reduces the total amount of impurities contained in the semiconductor substrate 201. Then, since the drive-in diffusion process is performed as the process of step S104, the range in which the impurities diffuse is expanded and the concentration is decreased. Therefore, in the present invention, by appropriately selecting conditions such as the processing time, temperature, and gas flow rate of each step, the thickness of the impurity diffusion layer, the thickness of the impurity-containing oxide layer, and the drive-in diffusion processing The impurity concentration on the surface of the impurity diffusion layer 204 can be adjusted by appropriately selecting the degree of expansion of the impurity diffusion range.

Example 1
FIG. 3 shows an example of conditions when the inventor of the present application processes a semiconductor on the main surface side of the semiconductor substrate according to Embodiment 1 of the present invention using boron as an impurity. In forming the impurity diffusion layer in step S101, the temperature in the diffusion furnace was set to 875 ° C., and the semiconductor substrate was exposed to BBr ₃ as an impurity source for 58 minutes. The flow rate of BBr ₃ was 110 mg / min, the flow rate of O ₂ was 13 sccm, and the flow rate of N ₂ was 6.75 slm. Further, in the formation of the impurity-containing oxide layer in Step S102, the flow rate of O ₂ was set to 10 slm and the temperature of 800 ° C. was maintained for 150 minutes. In the heat treatment for impurity diffusion in step S103, the flow rate of O ₂ was set to 10 slm and the temperature of 1000 ° C. was maintained for 360 minutes.

FIG. 4 shows a result obtained by using a SRP (Spread Resistance Profile) method to obtain a boron profile after removing a surface portion oxidized by a heat treatment for diffusion of impurities under the conditions of FIG. Indicates. As shown in FIG. 4, the concentration of boron on the surface of the semiconductor was 3.93 × 10 ¹⁷ atoms / cm ³ . Therefore, it can be seen that an impurity concentration suitable for a piezoresistive element can be obtained by processing a semiconductor under the conditions in this embodiment. The boron concentration slightly increased from the surface of the semiconductor to the inside, and after reaching a maximum value at about 0.3 μm from the surface, it gradually decreased, then decreased rapidly, and reached a minimum at 1.39 μm. .

(Effect of Embodiment 1)
As described above, in the first embodiment of the present invention, the impurity concentration on the surface of the semiconductor is 1 × 10 ¹⁹ atms / cm ³ or less, 1 × 10 ¹⁷ atms / cm ³ , particularly 1 × 10 ¹⁸ atm using thermal diffusion. It becomes possible to diffuse so as to be about / cm ³ . Conventionally, diffusion of such a concentration requires precise control of the amount of ions implanted using ion implantation. However, in Embodiment 1 of the present invention, it is not necessary to use ion implantation, so that the occurrence of crystal defects can be suppressed. In addition, since a special apparatus for ion implantation is not necessary, the processing cost can be reduced.

(Embodiment 2)
In the first embodiment, no particular mention is made of limiting the range in which the diffusion region is formed. In the second embodiment, a case where a region where a diffusion region is formed is limited and a region where a piezoresistive element or the like is formed is limited will be described.

  FIG. 5 is a diagram for explaining a method of forming a piezoresistive element. The description will be given according to this figure.

(Diffusion mask formation)
FIG. 5A is a view showing a cross section of the semiconductor substrate after the formation of the diffusion mask. A semiconductor substrate 1 such as a silicon single crystal substrate or an SOI substrate is prepared. A diffusion mask 2 having an opening on the main surface side of the semiconductor substrate 1 is formed. Examples of the material of the diffusion mask 2 include SiO ₂ and Si _e N ₄ . These materials are deposited on the entire main surface side of the semiconductor substrate 1 to have a uniform thickness using a CVD (Chemical Vapor Deposition) method or the like to form one layer or a plurality of layers. Thereafter, a photoresist is applied thereon. Then, the pattern is exposed, and after development processing, etching is performed to transfer the pattern to the diffusion mask 2 to perform patterning.

(Formation of impurity diffusion layer)
FIG. 5B is a view showing a cross section of the semiconductor substrate 1 in a state where the main surface side of the semiconductor substrate 1 is exposed to the impurity source and the impurity diffusion layer 3 is formed in the opening of the diffusion mask 2. That is, the state after performing the process of step S101 in FIG. 1 in the presence of the diffusion mask 2 is shown. As in FIG. 2B, in the impurity diffusion layer 3, the impurity concentration with respect to the thickness direction of the semiconductor substrate increases on the surface but rapidly decreases from the surface to the inside.

(Formation of impurity-containing oxide layer)
FIG. 5C shows a semiconductor substrate 1 in which an impurity-containing oxide layer 4 is formed on the surface of the impurity diffusion layer 3 by performing heat treatment while supplying O ₂ to the semiconductor substrate 1 on which the impurity diffusion layer 3 is formed. FIG. That is, the state after performing the process of step S102 of FIG. 1 in the presence of the diffusion mask 2 is shown.

(Removal of impurity-containing oxide layer)
Next, the impurity-containing oxide layer 4 is removed. That is, the process of step S103 in FIG. 1 is performed. For example, the impurity-containing oxide layer 4 is removed by wet etching using an LAL etching solution or the like. Note that the diffusion mask 2 may be removed after removing the impurity-containing oxide layer 4 or before removing the impurity-containing oxide layer 4. Since the impurity-containing oxide layer 4 is formed in the opening portion of the diffusion mask 2, the impurity-containing oxide layer 4 is removed in order to prevent the portion covered with the diffusion mask 2 from being etched. After that, the diffusion mask 2 is preferably removed. Alternatively, the diffusion mask 2 may be removed after “heat treatment for impurity diffusion” described below.

(Heat treatment for impurity diffusion)
After removing the impurity-containing oxide layer 4, heat treatment is performed to further diffuse the impurities into the semiconductor substrate. That is, the process of step S104 in FIG. 1 is performed.

(Surface etching)
FIG. 5D is a view showing a cross section of the semiconductor substrate 1 in a state where the piezoresistive element 5 is formed in a predetermined region on the surface of the semiconductor substrate 1. In this state, if the diffusion mask 2 remains after the heat treatment for impurity diffusion, it is removed. Further, if the surface of the impurity diffusion layer 3 is oxidized by heat treatment, it can be obtained by removing it as necessary. As described in the first embodiment, the impurity concentration in the piezoresistive element 5 can be controlled to 1 × 10 ¹⁹ atms / cm ³ or less and 1 × 10 ¹⁷ atms / cm ³ or more. In particular, it can be set to about 1 × 10 ¹⁸ atoms / cm ³ .

(Effect of Embodiment 2)
As described above, in the second embodiment of the present invention, the impurity is diffused using thermal diffusion, and the impurity concentration is 1 × 10 ¹⁹ atms / cm ³ or less at the surface of the diffusion region, 1 × 10 ¹⁷ atms / cm ^3. A piezoresistive element as described above can be formed. In particular, since it is not necessary to perform ion implantation, a piezoresistive element can be formed at a low cost. In addition, generation of crystal defects can be suppressed, which is suitable for use as an element in the MEMS field.

(Embodiment 3)
The piezoresistive element formed as described in Embodiment 2 of the present invention can be used for various sensors. Examples of such a sensor include an acceleration sensor and a pressure sensor. The third embodiment will be described using an acceleration sensor as an example of sensors using such piezoresistive elements. The acceleration sensor is used, for example, to detect the fall of a hard disk drive, tilt an electronic device such as a mobile phone, detect movement or operation of a game machine stick, detect the acceleration of a car, and activate an airbag. It is done. In particular, when an acceleration sensor is used in a mechanical device such as a car that is exclusively placed outdoors, it is affected by changes in temperature. For this reason, when the temperature characteristics of the piezoresistive element are inferior, temperature compensation is required. On the other hand, in the piezoresistive element manufactured by the manufacturing method according to the second embodiment, since the impurity concentration can be controlled to a low concentration, the temperature characteristics can be improved, and the temperature compensation circuit is not required, The area can be reduced by simplifying the circuit.

(Acceleration sensor structure)
FIG. 6 is an overall perspective view of the acceleration sensor. As shown in FIG. 6, the acceleration sensor 10 is a substantially rectangular parallelepiped. The acceleration sensor 10 includes a sensor body 20 made of a semiconductor substrate and a support substrate 30 made of glass or the like. In FIG. 6, two axes (X axis and Y axis) perpendicular to the plane of the acceleration sensor are set, and a direction perpendicular to the two axes is defined as the Z axis. The sensor body 20 is configured using an SOI substrate 110. The sensor body 20 is configured by sequentially laminating a silicon film 120, a silicon oxide film 130, and a silicon substrate 140. A weight body (weight section 142) is arranged in a frame (frame section 121 and frame section 141) having an opening, and the weight body is supported by a beam (flexible section 123) having flexibility with respect to the frame. It is configured to support. The support substrate 30 has a function as a pedestal for supporting the sensor body 20 and a function as a stopper substrate for restricting excessive displacement of the weight body in the downward direction (Z-axis negative direction). When the sensor body 20 is directly mounted on a package substrate or the like, the support substrate 30 may not be necessary.

  FIG. 7 is an exploded perspective view of the acceleration sensor. The silicon film 120 includes a fixed frame part 121 (the upper part of the frame), a weight joint part 122 disposed in the frame part 121, and two pairs (four in total) that connect the frame part 121 and the weight joint part 122. The flexible part 123 is provided. The frame portion 121, the weight joint portion 122, and the flexible portion 123 are defined by the opening 124. The frame part 121 is joined to the frame part 141 (the lower part of the frame) via the silicon oxide film 130. The weight junction 122 is joined to the substantially clover-shaped weight 142 via the silicon oxide film 130. The weight portion 142 is disposed away from the inner wall of the frame portion 141.

  The support substrate 30 is made of, for example, glass. In the case of glass, it can be bonded to the sensor body 20 by anodic bonding. The supporting substrate is not limited to glass, and a semiconductor such as metal (stainless steel, invar made of Fe-36% Ni alloy, etc.), insulating resin, Si, or the like can be used. The bonding method can be appropriately selected from direct bonding, eutectic bonding, bonding with an adhesive, and the like. Further, the sensor body 20 can be directly mounted on a mounting substrate or a package substrate without providing the support substrate 30.

  FIG. 8 is a plan view and a cross-sectional view of the acceleration sensor. FIG. 8A is a plan view of the acceleration sensor main body, and piezoresistive elements Rx to Rz for detecting acceleration in the three-axis (XYZ) directions are arranged on the four flexible portions 123. . The piezoresistive element is disposed in a region where the flexible portion 123 is connected to the frame portion 121 and the weight joint portion 122. In the drawing, piezoresistive elements Rx1 to Rx4 and Rz1 to Rz4 are arranged in a pair of flexible portions arranged in the direction along the X axis in order to detect acceleration in the X direction and the Z direction. On the other hand, piezoresistive elements Ry1 to Ry4 for detecting acceleration in the Y direction are arranged in a pair of flexible portions arranged in the direction along the Y axis. In addition, you may arrange | position piezoresistive element Rz1-Rz4 to a pair of flexible part arrange | positioned in the direction along the Y-axis.

  FIG. 8B is a cross-sectional view of the sensor main body along the XX cross section. The lower surface of the weight portion 142 is separated from the lower end of the frame portion 141, and a gap is formed between the sensor body and the glass substrate. Thereby, it is set so that a certain amount of displacement is possible in the Z-axis direction by the gap between the glass substrate 3 and the glass substrate 3. FIG. 8C is a cross-sectional view along the YY cross section of the sensor body, and the flexible portion 123 is a self-supporting thin film having flexibility.

  6 to 8 show an acceleration sensor having a structure in which a weight body is supported by a plurality of beam-like flexible portions, such a structure is not essential. For example, the acceleration sensor may have a structure in which the weight body portion is supported by a thin diaphragm-like flexible portion. FIG. 12 shows an example of the structure of the acceleration sensor having such a structure. FIG. 12A is a top view of the acceleration sensor. FIG. 12B is a cross-sectional view of the acceleration sensor, and shows a cross section by an XX cross section, a YY cross section, or a ZZ cross section. As shown in FIG. 12, the weight portion 142 arranged at the center is connected to the frame portion 121 by a thin diaphragm-like flexible portion 123. The piezoresistive element R is disposed in the flexible part 123 on the diaphragm, and the bending of the flexible part 123 due to the displacement of the weight body is detected as a resistance change of the piezoresistive element R.

  FIG. 9 is a diagram for explaining the details of the piezoresistive element. FIG. 9A shows a plan view, and FIG. 9B shows a cross-sectional view (A-A cross section). The piezoresistive element R is a piezoresistive element formed by diffusing impurities such as B (boron) and P (phosphorus) in the silicon film 120. That is, the piezoresistive element formed by the procedure described in the second embodiment. It is arranged near the boundary between the flexible part 123 and the frame part 121 and near the boundary between the flexible part 123 and the weight joint part 122.

  An insulating layer 150 is disposed on the piezoresistive element R. The insulating layer 150 has a contact hole 151 at a connection location with the wiring 152. Note that a total of 12 piezoresistive elements Rx1 to Rx4, Ry1 to Ry4, and Rz1 to Rz4 are connected in each detection direction to form a bridge circuit. Regarding the bridge circuit connection, Japanese Patent Application Laid-Open No. 2007-322297 by the applicant of the present application can be referred to. An electrode pad (not shown) for connecting to an external circuit is provided on the frame portion 121, and an extended portion of the wiring 152 is connected to the electrode pad so that an electrical signal accompanying acceleration is taken out to the external circuit. Can do.

(Acceleration sensor manufacturing method)
Next, a method for manufacturing the acceleration sensor according to the embodiment will be described with reference to FIGS. 10 and 11 are drawings showing a method of manufacturing an acceleration sensor according to an embodiment of the present invention.

(Preparation of SOI substrate (see FIG. 10A))
An SOI substrate 110 in which a silicon film 120, a silicon oxide film 130, and a silicon substrate 140 are stacked is prepared. As described above, the silicon film 120 is a layer constituting the frame part 121, the weight joint part 122, and the flexible part 123. The silicon oxide film 130 is a layer that joins the silicon film 120 and the silicon substrate 140 and functions as an etching stopper layer. The silicon substrate 140 is a layer constituting the frame part 141 and the weight part 142. The SOI substrate 110 is produced by SIMOX or a bonding method. In the SOI substrate 110, the thicknesses of the silicon film 120, the silicon oxide film 130, and the silicon substrate 140 are, for example, 5 μm, 2 μm, and 600 μm, respectively. Note that a plurality of acceleration sensors 10 having an outer circumference of about 1 to 2 mm are arranged on a wafer, which is an SOI substrate having a diameter of 150 mm to 200 mm, in a multifaceted manner.

(Formation of diffusion mask (see FIG. 10B))
A diffusion mask M that is an impurity diffusion mask is formed on the SOI substrate 110 on the silicon film 120 side. As a material of the diffusion mask M, for example, a silicon nitride film (Si ₃ N ₄ ) or a silicon oxide film (SiO ₂ ) can be used. Here, after a silicon oxide film is formed on the entire surface of the silicon film 120 by thermal oxidation or plasma CVD, a silicon nitride film is formed, and a resist pattern (not shown) is formed on the silicon nitride film. Then, an opening corresponding to the piezoresistive element R is formed in the silicon oxide film by wet etching such as RIE (Reactive Ion Etching) and hot phosphoric acid. The diffusion mask M has a two-layer structure of a silicon oxide film and a silicon nitride film from the silicon film 120 side (not particularly distinguished in the drawing). The silicon nitride film is used for preventing the diffusion of impurities described later.

(Formation of a piezoresistive element (see FIG. 10C))
A piezoresistive element is formed by a thermal diffusion method. The piezoresistive element manufacturing procedure described in Embodiment 2 and the like can be used. When diffusing B on the silicon film 120 side, the temperature in the diffusion furnace is set to 700 ° C. or higher and 900 ° C. or lower, and BBr ₃ or the like (sometimes O ₂ is allowed to flow) is provided on at least the diffusion mask M. Expose to. In this way, impurities are deposited to form an impurity diffusion layer. Then, O ₂ is supplied into a furnace at 750 ° C. or higher and 800 ° C. or lower to oxidize the impurity diffusion layer to form an impurity-containing oxide layer. Thereafter, an impurity-containing oxide layer having a high surface impurity concentration (generally 1 × 10 ²⁰ atms / cm ³ or more) is removed with an acid chemical solution such as hydrofluoric acid. Thereafter, heat treatment is performed in a diffusion furnace at a temperature of 900 ° C. or higher and 1100 ° C. or lower. The impurity concentration on the surface of the diffusion region can be adjusted by appropriately adjusting the conditions for forming the piezoresistive element. As a result, the concentration of impurities on the surface can be set to a predetermined concentration (for example, 1 × 10 ¹⁷ to 1 × 10 ¹⁹ atms / cm ³ ).

  According to the thermal diffusion method described above, since no ion implantation method is used, generation of crystal defects in the silicon film 120 constituting the flexible portion 123 can be suppressed, and long-term stability can be realized. In addition, temperature characteristics can be improved by adjusting the impurity concentration.

(Formation of insulating layer and contact hole (see FIG. 10D))
An insulating layer 150 is formed on the silicon film 120. For example, the insulating layer can be formed of a SiO ₂ layer by using the surface of the silicon film 120 by thermal oxidation or plasma CVD. A contact hole 151 is formed on the insulating layer 150 by RIE using a resist as a mask. The SiO ₂ film can be formed using a gas such as TEOS (Si (OC ₂ H ₅ ) ₄ ) / O ₂ or SiH ₄ / N ₂ O. The thickness of the SiO ₂ film is preferably 30 nm to 1 μm. This is because a stress range of −200 MPa to +200 MPa and a film thickness range of 30 nm to 1 μm are preferable in that the influence on the sensitivity and offset voltage of the sensor can be reduced. Then, a contact hole 151 is formed on the insulating layer 150 by RIE using a resist as a mask.

(Creation of wiring (see Fig. 10E))
A wiring 152 is formed. The wiring 152 is obtained by forming a metal material such as Al, Al—Si, or Al—Nd by sputtering or the like and patterning it. In order to form an ohmic contact between the wiring 152 and the piezoresistive element R, heat treatment (380 ° C. to 420 ° C.) is performed. Note that a film such as a silicon nitride film (Si ₃ N ₄ ) may be provided over the wiring 152 as a protective film.

(Processing of silicon film (see FIG. 11F))
The silicon film 120 is etched by RIE or the like until the upper surface of the silicon oxide film 130 is exposed, and an opening 124 is formed to define the frame part 121, the weight joint part 122, and the flexible part 123.

(Gap formation (see FIG. 11G))
The gap 160 is formed by etching the silicon substrate 140 using a mask having an opening along the inner frame of the frame portion 141. The gap 160 is an interval necessary for the weight part 142 to be displaced downward (on the glass substrate 3 side). For example, 5 to 10 μm. The value of the gap 160 can be appropriately set according to the dynamic range of the sensor.

(Processing of silicon substrate (see FIG. 11H))
Next, a mask for defining the frame part 141 and the weight part 142 is formed on the lower surface of the silicon substrate 140. Using this mask, the silicon substrate 140 is etched until the lower surface of the silicon oxide film 130 is exposed. It is preferable to use DRIE (Deep Reactive Ion Etching) for the etching.

In DRIE, an etching step of digging while eroding a material layer in the thickness direction and a deposition step of forming a polymer wall on a side wall formed as the erosion progresses by etching are alternately repeated. Since the side wall of the hole that has been dug is protected by forming a polymer wall in sequence, it is possible to advance erosion almost only in the thickness direction. An ion / radical supply gas such as SF ₆ can be used as an etching gas, and C ₄ F ₈ or the like can be used as a deposition gas.

(Removal of unnecessary silicon oxide film (see FIG. 11I))
The unnecessary silicon oxide film used as an etching stopper is removed by RIE or wet etching. As a result, the silicon oxide film 130 exists between the frame portion 121 and the frame portion 141, and the weight joint portion 122 and the weight portion 142.

(Joining of glass substrates (see FIG. 11J))
The sensor body 20 and the support substrate 30 are joined. When glass is used as the material of the support substrate 30, it is so-called Pyrex (registered trademark) glass containing movable ions such as Na ions, and anodic bonding is used for bonding to the SOI substrate 110. In order to prevent the weight 142 from sticking to the upper surface of the support substrate 30 due to electrostatic attraction during anodic bonding, a sticking prevention film (not shown) such as Cr is formed on the upper surface of the glass substrate 3 by sputtering. You may keep it. Thereby, the sensor main body 20 and the glass substrate 3 are joined, and the acceleration sensor 10 is comprised.

(Individualization)
The wafer on which the acceleration sensor 10 is formed is diced with a dicing saw or the like and separated into individual acceleration sensors 10. In this specification, the “acceleration sensor” arranged on the wafer in a multifaceted manner and the “acceleration sensor” separated into pieces are called the acceleration sensor 10 without any particular distinction. The above is an example of the method of manufacturing the acceleration sensor, and the order can be changed as appropriate, and is not limited to the above order.

(Example 2)
An SOI substrate having a thickness of 5 μm / 2 μm / 600 μm is prepared for each layer, a diffusion mask made of SiO ₂ is formed with a thickness of 1 μm, and then BBr ₃ is flown into a furnace at 800 ° C. at a flow rate of 55 mg / min. Feeded and exposed to impurity source for 10 minutes. At that time, O ₂ was supplied at a flow rate of 13 slm diluted with 15.75 slm N ₂ . Thereafter, the supply of the impurity source was stopped, and oxidation was performed at 800 ° C. with an oxygen flow rate of 5 slm. The oxidized oxide was removed by buffered hydrofluoric acid, and the SOI substrate was heat-treated while supplying O ₂ at a flow rate of 10 slm for 30 minutes in a 1000 ° C. furnace to diffuse impurities into the semiconductor. And processing for 1.5 minutes was performed by LAL. Thereafter, an acceleration sensor using the piezoresistive element as a detection element was produced. The impurity concentration distribution in the piezoresistance thus obtained was analyzed by the SIMS (secondary ion mass spectrometer) method. As a result, the impurity concentration on the surface was 1.24 × 10 ¹⁸ atoms / cm ³ . Therefore, an acceleration sensor with good temperature characteristics was obtained.

(Comparative example)
On the other hand, among the processes in Example 2, the temperature is set to 800 ° C., the process of oxidizing the surface while supplying O ₂ at a flow rate of ₅ to ₂₀ slm and the process of removing the oxide with buffered hydrofluoric acid are omitted. It was created. Specifically, an SOI substrate having a thickness of 5 μm / 2 μm / 600 μm is prepared for each layer, a diffusion mask made of SiO 2 is formed with a thickness of 1 μm, and then BBr 3 is introduced into a furnace at 800 ° C. at a flow rate of 55 mg / min. Feeded and exposed to impurity source for 10 minutes. At that time, O 2 was supplied at a flow rate of 13 slm diluted with 15.75 slm N 2. Thereafter, the supply of the impurity source was stopped, and the SOI substrate was heat-treated while supplying O 2 at a flow rate of 10 slm for 30 minutes in a furnace at 1000 ° C. to diffuse the impurities into the semiconductor. And processing for 1.5 minutes was performed by LAL. Thereafter, an acceleration sensor using the piezoresistive element as a detection element was produced. When the impurity concentration distribution in the piezoresistance thus obtained was analyzed by the SIMS method, the impurity concentration on the surface was 1.0 × 10 ²⁰ atms / cm ³ . Accordingly, the temperature characteristics are inferior to those of the acceleration sensor created in the second embodiment.

  As described above, according to the present invention, the manufacturing cost can be reduced by not using the ion implantation apparatus for forming the piezoresistive element. Moreover, even if the thermal diffusion method is used, a piezoresistive element having a small temperature change characteristic can be manufactured.

(Application examples)
Although the acceleration sensor 10 is distributed as a single chip, it is also distributed as an electronic component by being modularized in combination with an active element such as an IC. The acceleration sensor 10 can be used in various applications such as game machines and mobile terminals (for example, mobile phones). The acceleration sensor 10 and the package substrate / circuit substrate are electrically connected by a method such as wire bonding or flip chip.

  FIG. 13 is a diagram showing an example of a sensor module 400 on which the acceleration sensor 10 and a processing circuit are mounted. In FIG. 13, a sensor module 400 includes a signal processing chip 401 including a processing circuit, a memory chip 402, and a sensor chip 403 including the acceleration sensor 10 mounted on a substrate 404. Each chip 401, 402, 403 is connected by a bonding wire 405. The memory chip 402 is a memory that stores a control program, parameters, and the like for the signal processing chip 401.

  FIG. 14 is a schematic diagram of the processing circuit. Sensor X1402, sensor SensorY1403, and sensor SensorZ1404, which are sensors of each axis constituting the acceleration sensor 10, are amplified by an amplifier circuit (Amplifier 1401) and pass through circuits (S / H 1405, 1406, 1407) having a sample / hold function. . Thereafter, acceleration detection signals (Xout, Yout, Zout) are output through the output resistors (Rout 1408, 1409, 1410) and the capacitors (Cx1411, Cy1412, Cz1413). The output resistor and the capacitor function as a low-pass filter.

  An application example of the acceleration sensor 10 will be described with reference to FIG. 15 using a semiconductor device as an example. Note that in this specification, a semiconductor device refers to all devices that can function using semiconductor technology, and electronic devices are also included in the scope of semiconductor devices. The semiconductor device 1501 is a portable information terminal on which a sensor module is mounted, and includes a main body 1502. The main body 1502 has a display unit 1503 and a keyboard unit 1504 connected via a hinge. For example, the acceleration sensor 10 is used in a hard disk device installed under the keyboard unit 1504. Thus, the acceleration applied to the semiconductor device 1501 is detected, and when an acceleration greater than a predetermined value is detected, the head can be retracted and damage due to contact between the head and the disk surface can be prevented. Note that a hard disk is not essential for the semiconductor device 1501. For example, the semiconductor device 1501 may be a mobile phone using a nonvolatile semiconductor memory element. In this case, for example, it is possible to detect the acceleration applied to the mobile phone when a person carrying the mobile phone walks and measure the number of steps.

It is a flowchart of the process of the semiconductor in Embodiment 1 of this invention. It is sectional drawing showing the state of the semiconductor in each step of the process in Embodiment 1 of this invention. It is an example figure of the conditions of processing of a semiconductor in Embodiment 1 of the present invention. The boron profile of the semiconductor after the process of Embodiment 1 of this invention was performed on the conditions of FIG. 3 is shown. It is a figure for demonstrating the method to form the piezoresistive element which concerns on Embodiment 2 of this invention. It is a whole perspective view of the acceleration sensor which concerns on Embodiment 3 of this invention. It is a disassembled perspective view of the acceleration sensor which concerns on Embodiment 3 of this invention. It is the top view and sectional drawing of an acceleration sensor main body which concern on Embodiment 3 of this invention. It is drawing explaining the detail of the piezoresistive element used for the acceleration sensor which concerns on Embodiment 3 of this invention. It is a figure explaining the manufacturing method of the acceleration sensor which concerns on Embodiment 3 of this invention. It is a figure explaining the manufacturing method of the acceleration sensor which concerns on Embodiment 3 of this invention. It is the top view and sectional drawing of an acceleration sensor main body which concern on Embodiment 3 of this invention. It is an example figure of the module using the acceleration sensor which concerns on Embodiment 3 of this invention. It is a schematic diagram of the processing circuit which processes the signal of the acceleration sensor which concerns on Embodiment 3 of this invention. It is an example figure of the external appearance of the semiconductor device using the acceleration sensor which concerns on Embodiment 3 of this invention.

Explanation of symbols

201 semiconductor
202 Impurity diffusion layer
203 Impurity-containing oxide layer
204 Impurity diffusion layer

Claims (4)

A method of manufacturing a semiconductor sensor, wherein a surface concentration of impurities diffused inside a semiconductor is controlled to a low concentration on the semiconductor surface,
Forming a mask having an opening on a semiconductor substrate;
Exposing the semiconductor substrate exposed through the opening to an impurity source to form an impurity diffusion layer;
By oxidizing the impurity diffusion layer, an impurity-containing oxide layer containing the impurity at a high concentration is formed so that the surface concentration of the impurity on the semiconductor surface is 1 × 10 ²⁰ atoms / cm ³ or more,
Removing at least a part of the impurity-containing oxide layer containing impurities at a high concentration;
By diffusing the impurities in the impurity diffusion layer after the removal of the impurity-containing oxide layer into the semiconductor substrate, the surface concentration of impurities on the semiconductor surface is 1 × 10 ¹⁷ atoms / cm ³ or more and 1 × 10 ^19. forming a diffusion region for forming a piezoresistive element in which impurities are controlled to a low concentration so as to be atms / cm ³ or less;
Forming a flexible part including the piezoresistive element and a frame part connected to the flexible part,
The temperature for forming the impurity-containing oxide layer is set lower than the temperature for forming the piezoresistive element so that impurities do not diffuse into the semiconductor ,
A method of manufacturing a semiconductor sensor, wherein a region having a concentration higher than a surface concentration of the impurity on the semiconductor surface exists in the semiconductor. Forming a mask having an opening on a silicon substrate;
Exposing the silicon substrate exposed by the opening to boron tribromide at a flow rate of 28 to 110 milligrams per minute at a temperature of 700 to 900 ° C. to form an impurity diffusion layer;
Forming an impurity-containing oxide layer by oxidation of the impurity diffusion layer at a temperature of 750 ° C. or higher and 800 ° C. or lower;
Removing at least part of the impurity-containing oxide layer;
A diffusion region for forming a piezoresistive element by diffusing impurities in the impurity diffusion layer after removing the impurity-containing oxide layer into the silicon substrate at a temperature of 900 ° C. to 1100 ° C .;
The impurity concentration on the surface of the diffusion region is set to 1 × 10 ¹⁷ atoms / cm ³ or more and 1 × 10 ¹⁹ atoms / cm ³ or less,
Forming a flexible part including the piezoresistive element, and a frame part connected to the flexible part ,
A method of manufacturing a semiconductor sensor, wherein a region having a concentration higher than a surface concentration of the impurity on the surface of the silicon substrate is present in the silicon substrate . 3. The method of manufacturing a semiconductor sensor according to claim 2 , wherein a temperature at which the impurity-containing oxide layer is formed is lower than a temperature at which the piezoresistive element is formed. Forming a mask having an opening in a silicon substrate;
The opening is exposed to boron tribromide at a flow rate of 28 to 110 milligrams per minute at a temperature of 700 to 900 ° C. to form an impurity diffusion layer,
Forming an impurity-containing oxide layer by oxidation of the impurity diffusion layer at a temperature of 750 ° C. or higher and 800 ° C. or lower;
Removing at least part of the impurity-containing oxide layer;
Diffusing impurities in the impurity diffusion layer after removal of the impurity-containing oxide layer at a temperature of 900 ° C. or higher and 1100 ° C. or lower to form a diffusion region inside the silicon substrate;
The impurity concentration on the surface of the diffusion region is set to 1 × 10 ¹⁷ atoms / cm ³ or more and 1 × 10 ¹⁹ atoms / cm ³ or less.
Only contains the
A method of manufacturing a piezoresistive element, wherein a region having a concentration higher than a surface concentration of the impurity on the surface of the silicon substrate is present in the silicon substrate .

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