TWI304630B - - Google Patents

Download PDF

Info

Publication number
TWI304630B
TWI304630B TW91121990A TW91121990A TWI304630B TW I304630 B TWI304630 B TW I304630B TW 91121990 A TW91121990 A TW 91121990A TW 91121990 A TW91121990 A TW 91121990A TW I304630 B TWI304630 B TW I304630B
Authority
TW
Taiwan
Prior art keywords
layer
substrate
fabricating
gate dielectric
insulating layer
Prior art date
Application number
TW91121990A
Other languages
English (en)
Chinese (zh)
Inventor
Chi Chun Chen
Tze Liang Lee
Shih Chang Chen
Original Assignee
Taiwan Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Priority to TW91121990A priority Critical patent/TWI304630B/zh
Application granted granted Critical
Publication of TWI304630B publication Critical patent/TWI304630B/zh

Links

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
TW91121990A 2002-09-25 2002-09-25 TWI304630B (enrdf_load_stackoverflow)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW91121990A TWI304630B (enrdf_load_stackoverflow) 2002-09-25 2002-09-25

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW91121990A TWI304630B (enrdf_load_stackoverflow) 2002-09-25 2002-09-25

Publications (1)

Publication Number Publication Date
TWI304630B true TWI304630B (enrdf_load_stackoverflow) 2008-12-21

Family

ID=45070976

Family Applications (1)

Application Number Title Priority Date Filing Date
TW91121990A TWI304630B (enrdf_load_stackoverflow) 2002-09-25 2002-09-25

Country Status (1)

Country Link
TW (1) TWI304630B (enrdf_load_stackoverflow)

Similar Documents

Publication Publication Date Title
CN100550340C (zh) 制造半导体器件的方法
US20060128123A1 (en) Methods of forming integrated circuits structures including epitaxial silicon layers in a active regions
US6265267B1 (en) Fabricating method for a semiconductor device comprising gate oxide layers of various thicknesses
JP2003332416A (ja) 半導体集積回路及びその製造方法
JP2009164566A (ja) 半導体メモリ素子の素子分離膜形成方法
JP2006216854A (ja) 半導体装置の製造方法
US7611950B2 (en) Method for forming shallow trench isolation in semiconductor device
JP3993820B2 (ja) 半導体素子の素子分離膜の形成方法
TWI236065B (en) Method for providing an integrated active region on silicon-on-insulator devices
US10566203B1 (en) Method for alleviating etching defect of salicide barrier layer
JP2004172325A (ja) 半導体装置の製造方法
JP4472434B2 (ja) 半導体装置の製造方法
JP2002043435A (ja) システムオンチップの製造方法、半導体装置の製造方法
TWI304630B (enrdf_load_stackoverflow)
US7271066B2 (en) Semiconductor device and a method of manufacturing the same
JP3844896B2 (ja) 半導体素子の隔離構造及びその形成方法
JP2000100927A (ja) トレンチ素子分離領域を有する半導体素子の製造方法
TWI488224B (zh) 硬罩幕去除方法
JP4511101B2 (ja) 半導体装置の製造方法
JP2013048161A (ja) 半導体装置の製造方法
JP2010098152A (ja) 半導体装置の製造方法
KR20040001224A (ko) 반도체 소자의 소자분리막 제조방법
JP2006245433A (ja) 半導体素子の製造方法
KR100618692B1 (ko) 게이트산화막 제조방법
KR101204662B1 (ko) 반도체 소자의 트랜지스터 형성방법

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees