TWI304630B - - Google Patents

Description

1304630 _ Case No. 91121卯0_年月曰 Revision__ V. INSTRUCTION DESCRIPTION (1) [Invention Field] The present invention relates to a semiconductor integrated circuit (1C) process, and more particularly to a double gate A method of fabricating dual gate dielectric layers. [Explanation of the prior art] In order to increase the operating speed of the component, a logic component (1 〇gic device) and a peripheral device are often mixed on the same wafer (chi p), and such a mixed component is called an embedding. An embedded semiconductor device. Generally, the gate oxide layer of the transistor of the logic element region needs a thinner thickness to enhance the driving ability of the transistor; while the peripheral component region, such as the I/〇 transistor of the memory device region, requires a thicker gate. Oxide layer to avoid an electrical breakdown phenomenon caused by a supply voltage of, for example, 5.5 volts. Therefore, the conventional process is applied to the embedded semiconductor device by a dual gate oxide process (DGO process), that is, gate oxide layers of different thicknesses are formed on the same substrate. The conventional double gate oxide process will be described below using Figs. 1A to 1E. First, referring to FIG. 1A, a substrate 1 is provided having a first active region 1 1 〇 (eg, a peripheral element region) and a second active region 1 2 0 (eg, a logic element region). Between the first active region 1 1 〇 and the first active & field 120 with a shallow trench isolation layer (STI) 130, such active regions iio, i2〇 Separate from each other. Then, a thick oxide layer 140 is formed on the substrate 100 by thermal oxidation (t h e r m a 1 ο x i d a t i ο η).

0503-8124TWF2(N);1 ini in;20080403.ptc Page 4 1304630 Correction = After 'Please refer to FIG. 1B to form a patterned photoresist layer 150 in the thick oxide layer 140 of the first active region 110. on. Then, please refer to Figure 1 C, using the photoresist layer 150 as an etch mask.

Cmask) </ RTI> removes the thick oxide layer 140 located in the second active region 120 to form a remaining thick oxide layer 140 on the substrate 100 of the first active region 11 。. Thereafter, please refer to FIG. 1D to remove the photoresist layer 150. Then, after removing the photoresist layer 15 5 , it will be cleaned by a standard cleaning procedure (STI), but the surface of the substrate 1 〇 () located in the second active region 12 will be cleaned. A chemical oxide film (chemical oxide fi lm) is formed in the process, and an oxide film is naturally grown in contact with the atmosphere, and is collectively referred to herein as a native oxide layer (160). It should be emphasized here that if the original oxide layer 160 is removed by a solution of hydrofluoric acid at this time, the remaining thick oxide layer 14 4 located in the first active region 11 会 can be easily simultaneously It is removed or destroyed, so that the original oxide layer 16 can not be removed by a hydrofluoric acid solution, so that the conventional double gate dielectric layer has a native oxide 160. Next, referring to FIG. 1E, a thin oxide layer 170 is formed by thermal oxidation on the substrate 1000 of the second active region (2〇 (ie, the original oxide layer 160). . However, since the structure of the original oxide layer 160 is not dense, the quality of the thin oxide layer 1 7 会 is affected, and the existence of the original oxide layer 160 also hinders the development of the thin layer size of the dielectric layer (sea 1 i ng limitation) 〇 者 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国 美国

0503-8124TWF2(N);1 ini in;20080403.ptc Page 5 1304630 __Case No. 91121990_年月 a Correction _ V. Description of the invention (3) Process, however, the process must be after the formation of the gate oxide layer, A protective layer (nitriding layer) is additionally formed on the gate oxide layer to protect the gate oxide layer. Further, although U.S. Patent No. 6,1,0842 discloses a DG0 process, since the process requires the use of a plasma nitriding method, the process requires an expensive plasma nitriding device in addition to the plasma. How much of the bombardment process will also have problems with substrate defects that affect product reliability. SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a method of fabricating a dual gate dielectric layer that successfully removes the original oxide layer while ensuring the quality of the dual gate dielectric layer. In accordance with the purpose, the present invention provides a method of fabricating a dual gate dielectric layer comprising the steps of: (a) providing a semiconductor substrate having at least one peripheral component region and at least one logic component region, wherein the peripheral component region And the logic element region is isolated from each other by an insulating layer; (b) forming a thin nitride layer on the substrate; (c) forming a photoresist to be in position in the logic element region (d) using the photoresist layer as an etch mask to remove the thin nitride layer located in the peripheral device region to expose the substrate, thereby forming a remaining thin nitride layer in the logic element region (e) removing the photoresist layer, at this time, a base oxide layer is formed on the base 3 of the peripheral element region, and (f) the original oxide layer is removed by using a solution containing hydrogen peroxide (HF). And (g) performing a thermal oxidation treatment to form a thick oxide layer on the substrate in the peripheral element region, and simultaneously forming and annealing the remaining thin nitride layer by the thermal oxidation treatment Nitrogen oxidation The bit in the logic element region of the substrate

0503 -8124TWF2(N); 1i η 1i η; 20080403.p t c 1304630

The thickness of the thick oxide layer which is followed by the thickness of the thin nitride layer in the 'step (8) is exemplified. Embodiments: The preferred embodiment of the present invention will be described. The process profile of the wide head A, please refer to FIG. 2, to provide a substrate 200 such as a stone substrate having at least one peripheral element region 21 2 2 V - logic element region 220, wherein the peripheral components The area 21A and the logic area 220 are isolated from each other by an insulating layer 23〇. Wherein, the piece area 210 is, for example, a peripheral component area, and the logic element area 22 is an area. Further, the insulating layer 23 is a shallow trench insulating layer (7) '% germanium layer (F0X), and a shallow trench insulating layer is used in Figs. 2 to 6, but the present invention is not limited thereto. 〇 Still referring to Figure 2, a thin nitride layer 240 is formed on the substrate after a standard cleaning procedure (such as RCA cleaning private sequence) and a cleaning procedure including a hydrofluoric acid solution (eg, after the MF cleaning process). 2, wherein the thickness of the thin nitride layer 240 is, for example, between 1 〇 and 2 〇 A, and the thin nitride layer / 240 is, for example, deposited by a method (^ ep 〇sm 〇n) The formed 丨n layer. Next, referring to FIG. 3, a patterned photoresist layer 310 is formed on the thin nitride layer 240 of the logic element region 220. Next, please refer to FIG. Using the photoresist layer 3 1 〇 as an etching mask, the thin nitride layer 240 located in the peripheral device region 210 is removed by dry etching or wet etching to expose the surface of the substrate 200 to form a remaining thin film.

1304630

The nitride layer 240' is on the substrate 2A of the logic element region 22A. Next, please refer to Figure 5, remove the photoresist layer 3丨〇, and then remove the contaminants on the substrate 2 by a standard cleaning procedure (such as RC A cleaning procedure). The 21 〇 of the substrate 2 形成 will form a raw oxide layer 51 厚度 (native ox) having a thickness of about 1 〇A due to reaction with an oxidizing agent (for example, H 2 〇 2) in the standard cleaning procedure and reaction with the atmosphere. i de ) on the substrate 200. Therefore, the original oxide layer 51 is removed by reusing the solution HF containing HF (e.g., D H F). It is emphasized here that since the remaining thin nitride layer 240 of the present invention is hardly eroded by the HF solution 520, the present invention can successfully remove the original oxide layer 5 without damaging the remaining thin nitride. Layer 240'. ' Next, please refer to Figure 6, for a temperature of about 80 〇 ~; [〇〇〇t, a thermal oxidation of about 2 minutes, forming a thick oxide layer 610 in the peripheral component area 21 〇 of the substrate 2 ,, and simultaneously anneal and oxidize the remaining thin nitride layer 240 ′ by the thermal oxidation treatment to form an oxynitride layer 6 20 in place On the substrate 200 of the logic cell region 220. The thick oxide layer 61 0 is, for example, a layer S 1 02 between 5 〇 and 80 Å, and the oxynitride layer 6 2 0 is, for example, a layer of S i 0 N. Further, the effect of the annealing is to reduce the defect density in the remaining thin nitride layer 240', and to improve the quality of the formed nitrogen oxide layer 62 (for example, to reduce the occurrence of leakage current, etc.) Wait). Further, since the oxynitride layer 6 2 〇 is very close to the thickness of the remaining thin nitride layer 2 4 ′, the development of thinning of the dielectric layer is not affected. Therefore, through the above process, the product can be formed on the same substrate 2〇

0503-8124TWF2(N); 1i η1i η; 20080403.p t c 1304630

曰Correcting the double gate dielectric layers 61 G, 6 2 0 having different thicknesses. [Features and Effects of the Invention] The process of the present invention is characterized by a cross-sectional view as shown in FIG. 5, in the present invention. The remaining thin nitride layer 240' can be eroded by the HF solution 520. Therefore, the present invention can successfully remove the original oxide layer located on the substrate 2 5 5 0 此 此 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' The growth of the thick oxygen a 61 〇 σσ negative' further enhances the reliability of the double gate dielectric layer. Moreover, since the remaining thin nitride layer 24 〇' of the present invention has no original rolled layer, the dielectric layer can be improved. ScaUn development 6] fi ^ In this invention, only one hot process (simultaneous growth of oxide layer, ', rat #L b layer 6 2 0 annealing), compared with the conventional method (less, so this The invention is more than the Xizhi 4~+ madness "budget". "Method (4) Thermal Prediction ennai ei〇^^^ Although the present invention has been disclosed above in the preferred embodiment, it is limited to the present invention, and any one of the ",", ", and " The scope of the claims of the present invention is defined by the scope of the claims of the present invention. I 固固第9页 0503-8124TW2(N); 3inlin; 20080403.ptc 1304630 Case No. 91121990 曰 Revisions BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be described in more detail below with reference to the drawings and preferred embodiments. 1A to 1E are schematic cross-sectional views showing a conventional double gate oxide layer; and Figs. 2 to 6 are schematic cross-sectional views showing a process of a double gate dielectric layer member in accordance with a preferred embodiment of the present invention. DESCRIPTION OF REFERENCE NUMERALS 11 0~first active region 1 3 0~ shallow trench insulating layer 1 4 0 '~ remaining thick oxide layer 160~ original oxide layer; conventional portion (1A to 1E) 1 0 0~ semiconductor substrate; 1 2 0 ~ second active region; 1 4 0 ~ thick oxide layer; 1 5 0 ~ photoresist layer; 1 7 0 ~ thin oxide layer. Part of this case (Fig. 2~6) 2 0 0~ semiconductor substrate; 2 2 0~ logic element region; 240~ thin nitride layer; 3 1 0~ photoresist layer; 5 2 0~ hydrofluoric acid solution; 620~ Nitrogen oxide layer. 2 1 0 ~ peripheral element region 2 3 0 ~ insulating layer; 240' ~ remaining thin nitride layer 5 1 0 ~ original oxide layer; 6 1 0 ~ thick oxide layer;

0503-8124TWF2(N); 1i η1i η;20080403.ρ t c Page 10

Claims (1)

1304630 __Case No. 91121990 Ql Y U 曰 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Having at least one peripheral element region and at least one logic element region, wherein the peripheral device region is insulated from the logic device region; (b) forming a first insulating layer on the substrate; (c) removing the bit The first insulating layer of the peripheral element region exposes the substrate; (d) removing a raw oxide layer of the substrate in the peripheral element region by using a solution containing hydrofluoric acid; and (e) selectively forming a A thick oxide layer is on the substrate of the peripheral element region, and the step of forming a thick oxide layer simultaneously converts the first insulating layer into a second insulating layer on the substrate of the logic element region. 2. The method of fabricating a double gate dielectric layer according to claim 1, wherein the insulating isolation in step (a) is shallow trench isolation or field oxide insulation. 3. The method of fabricating a double gate dielectric layer according to claim 1, wherein the first insulating layer in the step (b) is a thin nitride layer. 4. The method for fabricating a double gate dielectric layer according to claim 1, wherein in the step (c), the method of removing the first insulating layer in the peripheral element region exposes the substrate, and further The method includes the following steps: (c1) forming a photoresist layer on the first insulating layer of the logic element region; (c2) using the photoresist layer as an etching mask to remove the peripheral element 1304630 ___Case No. 91121990___年月_0__—Correction 6. The first insulating layer of the patented component area exposes the substrate to form a remaining first insulating layer on the substrate of the logic element region And (c 3 ) removing the photoresist layer. 5. The method of fabricating a double gate dielectric layer according to claim 1, wherein the thickness of the first insulating layer in the step (b) is between 1 〇 and 2 〇 a. 6. The method of fabricating a double gate dielectric layer according to claim 1, wherein the first insulating layer in the step (b) is a SiN layer formed by a deposition method. 7. The method of fabricating a double gate dielectric layer according to claim 1, wherein the hydrofluoric acid-containing solution in the step (d) is diluted hydrofluoric acid (DHF). 8. The method of fabricating a double gate dielectric layer according to the invention of claim 2, wherein the method of forming a thick oxide layer in the step (e) is performing a ruthenium oxidation treatment. 9. The method of fabricating the double gate dielectric layer of claim 2, wherein the second insulating layer in the step (e) is an oxynitride layer. A method of fabricating a double gate dielectric layer as described in claim 2, wherein the second insulating layer in the step (e) is a Si〇N layer. The method for fabricating the double gate dielectric layer according to claim 1, wherein the thickness of the thick oxide layer in the step (e) is between 5 〇 and 8 〇 A.