JP2010098152A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device wherein plasma damage to a gate insulating film is eliminated to improve the reliability of the gate insulating film. <P>SOLUTION: The method of manufacturing a semiconductor device includes: a process where, when a MONOS type memory transistor region 101 and a transistor region 100 are provided on one semiconductor substrate, a tunnel oxide film 7 is formed in the MONOS type memory transistor region 101, and a nitride silicon film 8 is formed on the tunnel oxide film 7 and on a gate insulating film 5 in the transistor region, and an oxide silicon film 9 is formed on the nitride silicon film; a process for forming a mask film 10 in the MONOS memory transistor region 101 and removing the oxide silicon film 9 using the mask film 10 as a mask; and a process for removing the nitride silicon film 8 by wet etching by a hot phosphoric acid using the mask film 10 as a mask. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device that can improve the reliability of a gate insulating film by eliminating plasma damage to the gate insulating film.

  Conventionally, there is a semiconductor device having a plurality of different transistors such as a high breakdown voltage transistor, a low breakdown voltage transistor, and a MONOS type memory transistor in the same semiconductor chip.

  In this case, the formation flow in the mixed mounting process of the high breakdown voltage transistor, the low breakdown voltage transistor, and the MONOS type memory transistor is as follows. After the MONOS region is covered with a resist, the NO film is removed in regions other than the MONOS region.

  The NO film has a laminated structure of, for example, a tunnel oxide film, a silicon nitride film, and a silicon oxide film. When removing the NO film in a region other than the MONOS region, a photolithography method and a dry etching method are used. (See, for example, Patent Document 1).

JP-A-2005-116974 (0018-0067)

  As described above, in the conventional method for manufacturing a semiconductor device, after the NO film is formed on the gate insulating film of the high voltage transistor which is a transistor other than the MONOS type memory transistor, the NO film is removed by dry etching. At this time, plasma damage due to dry etching is applied to the gate insulating film of the high voltage transistor. As a result, the reliability of the gate insulating film in the high breakdown voltage transistor is impaired.

  An aspect according to the present invention is a method for manufacturing a semiconductor device that can improve the reliability of a gate insulating film by eliminating plasma damage to the gate insulating film by employing wet etching instead of dry etching.

In order to solve the above problems, a method for manufacturing a semiconductor device according to one embodiment of the present invention includes a method for manufacturing a semiconductor device having a MONOS memory transistor region and a transistor region over the same semiconductor substrate.
Forming a gate insulating film on the semiconductor substrate in the transistor region;
Forming a tunnel oxide film on the semiconductor substrate in the MONOS type memory transistor region, forming a silicon nitride film on the tunnel oxide film in the MONOS type memory transistor region and on the gate insulating film in the transistor region; Forming a silicon oxide film on the silicon nitride film;
Forming a mask film on the silicon oxide film in the MONOS type memory transistor region, and removing the silicon oxide film in the transistor region using the mask film as a mask;
Removing the silicon nitride film in the transistor region by wet etching with hot phosphoric acid using the mask film as a mask;
It is characterized by comprising.

  According to the method for manufacturing a semiconductor device, the silicon nitride film in the transistor region is removed by wet etching using hot phosphoric acid. Thus, unlike the case of removing by dry etching, plasma damage does not occur in the transistor region. As a result, the reliability of the gate insulating film in the transistor region is improved.

A method for manufacturing a semiconductor device according to an aspect of the present invention includes a method for manufacturing a semiconductor device having a MONOS memory transistor region, a high breakdown voltage transistor region, and a low breakdown voltage transistor region on the same semiconductor substrate.
Forming a gate insulating film on the semiconductor substrate in the high breakdown voltage transistor region;
A tunnel oxide film is formed on the semiconductor substrate in the MONOS type memory transistor region and on the semiconductor substrate in the low breakdown voltage transistor region, and silicon nitride is formed on the tunnel oxide film and the gate insulating film in the high breakdown voltage transistor region. Forming a film and forming a silicon oxide film on the silicon nitride film;
Forming a mask film on the silicon oxide film in the MONOS type memory transistor region, and removing the silicon oxide film in each of the high breakdown voltage transistor region and the low breakdown voltage transistor region using the mask film as a mask;
Removing the silicon nitride film in each of the high breakdown voltage transistor region and the low breakdown voltage transistor region by wet etching with hot phosphoric acid using the mask film as a mask;
It is characterized by comprising.

  In the method for manufacturing a semiconductor device according to one embodiment of the present invention, the step of removing the silicon oxide film is preferably a step of removing the silicon oxide film by wet etching using hydrofluoric acid.

A method for manufacturing a semiconductor device according to an aspect of the present invention includes a method for manufacturing a semiconductor device having a MONOS memory transistor region, a high breakdown voltage transistor region, and a low breakdown voltage transistor region on the same semiconductor substrate.
A first silicon oxide film is formed on the semiconductor substrate in each of the MONOS type memory transistor region, the high breakdown voltage transistor region, and the low breakdown voltage transistor region, and a first silicon nitride film is formed on the first silicon oxide film. Forming a step;
Removing the first silicon nitride film and the first silicon oxide film in the high breakdown voltage transistor region;
Forming a gate insulating film on the semiconductor substrate in the high breakdown voltage transistor region by a selective oxidation method using the first silicon nitride film in each of the MONOS type memory transistor region and the low breakdown voltage transistor region as a mask;
Removing the first silicon nitride film in each of the MONOS type memory transistor region and the low breakdown voltage transistor region;
Covering each of the high breakdown voltage transistor region and the low breakdown voltage transistor region with a first mask film, and removing the first silicon oxide film in the MONOS type memory transistor region using the first mask film as a mask;
Removing the second mask film;
A tunnel oxide film is formed on the semiconductor substrate in the MONOS type memory transistor region, and the first silicon oxide film in the tunnel oxide film, on the gate insulating film in the high breakdown voltage transistor region, and in the low breakdown voltage transistor region. Forming a second silicon nitride film thereon, and forming a second silicon oxide film on the second silicon nitride film;
A second mask film is formed on the second silicon oxide film in the MONOS type memory transistor region, and the second withstand voltage transistor region and the second withstand voltage transistor region are respectively used as the mask with the second mask film as a mask. Removing the silicon oxide film,
Removing the second silicon nitride film in each of the high breakdown voltage transistor region and the low breakdown voltage transistor region by wet etching with hot phosphoric acid using the second mask film as a mask;
It is characterized by comprising.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
1 to 4 are sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. 1 to 4 includes a high breakdown voltage (HV) transistor region 100, a MONOS region 101, and a low breakdown voltage (LV) transistor region 102 mounted on the same substrate.

  First, as shown in FIG. 1A, a LOCOS oxide film 2 and an offset film 2a are formed on the surface of a silicon substrate 1 as element isolation films. Next, a resist pattern (not shown) is formed on the silicon substrate 1, and N-type impurity ions are implanted into the silicon substrate 1 using the resist pattern as a mask. As a result, the N-type well region 19 is formed in the high breakdown voltage transistor region 100. Thereafter, the resist pattern is peeled off.

  Next, a resist pattern (not shown) is formed on the silicon substrate 1, and N-type impurity ions are implanted into the silicon substrate 1 using the resist pattern as a mask, thereby forming an N-type impurity layer (not shown) in the high breakdown voltage transistor region 100. Form. Thereafter, by subjecting the silicon substrate 1 to heat treatment, an N-type impurity layer (not shown) in the high breakdown voltage transistor region 100 is diffused, and an N-type offset region 20 is formed. Thereafter, a silicon oxide film 3 is formed on the entire surface of the silicon substrate 1 by a thermal oxidation method. As a result, an oxide film of 10 nm is deposited on the silicon substrate 1 in the high breakdown voltage transistor region 100.

  Next, as shown in FIG. 1B, a silicon nitride film 4 is formed on the silicon oxide film 3 by a CVD (Chemical Vapor Deposition) method.

  Thereafter, as shown in FIG. 1C, a resist pattern (not shown) is formed so that the silicon nitride film 4 in the high breakdown voltage transistor region 100 is exposed. Using this resist pattern as a mask, the silicon nitride film 4 in the high breakdown voltage transistor region 100 is removed by etching. As a result, an oxide film of 7 nm is formed on the silicon substrate 1 in the high breakdown voltage transistor region 100. Thereafter, the resist pattern (not shown) is removed, and wet etching with hydrofluoric acid is performed using the silicon nitride film 4 as a mask, thereby removing the silicon oxide film 3 in the high breakdown voltage transistor region 100. Thereby, the oxide film formed on the silicon substrate 1 in the high breakdown voltage transistor region 100 is removed.

  Next, as shown in FIG. 1D, a first gate insulating film 5 is formed in the high breakdown voltage transistor region 100 by a selective thermal oxidation method. At this time, the silicon oxide film 3 and the silicon nitride film 4 formed in the MONOS region 101 and the low breakdown voltage transistor region 102 are used as a mask for selective thermal oxidation. As a result, a 67 nm first gate insulating film 5 is deposited on the silicon substrate 1 in the high breakdown voltage transistor region 100.

  Next, as shown in FIG. 2A, the silicon nitride film 4 formed on the silicon oxide film 3 in the MONOS region 101 and the low breakdown voltage transistor region 102 is removed. At this time, the silicon nitride film 4 is removed by wet etching using hydrofluoric acid and hot phosphoric acid. As a result, the first gate insulating film 5 of 62 nm is deposited on the silicon substrate 1 in the high breakdown voltage transistor region 100.

  Next, a resist pattern (not shown) is formed on the silicon substrate 1, and N-type impurity ions are implanted into the silicon substrate 1 using the resist pattern as a mask. As a result, the N-type well region 22 is formed in the MONOS region 101 and the N-type well region 24 is formed in the low breakdown voltage transistor region 102. Thereafter, the resist pattern is peeled off.

  Next, as shown in FIG. 2B, a first resist pattern 6 is formed so as to cover the high breakdown voltage transistor region 100 and the low breakdown voltage transistor region 102. Next, the silicon oxide film 3 in the MONOS region 101 is removed with hydrofluoric acid using the first resist pattern 6 as a mask. Thereafter, the first resist pattern 6 is peeled off.

  Next, as shown in FIG. 2C, a tunnel oxide film 7 is formed to a thickness of 3.8 nm on the entire surface of the substrate including the high breakdown voltage transistor region 100, the MONOS region 101, and the low breakdown voltage transistor region 102 by thermal oxidation. To do. Further, since the tunnel oxide film 7 formed by the thermal oxidation method has the same film quality as the silicon oxide film 3 and the first gate insulating film 5, in the high breakdown voltage transistor region 100 and the low breakdown voltage transistor region 102, Reference numeral 7 is not attached. As a result, a 63 nm first gate insulating film 5 is formed on the silicon substrate 1 in the high breakdown voltage transistor region 100. Next, a silicon nitride film 8 is formed to a thickness of 4.5 nm on the tunnel oxide film 7 by a CVD method, a silicon oxide film 9 is formed to a thickness of 8.5 nm on the silicon nitride film 8, and the respective films are laminated. Form.

  Next, as shown in FIG. 2D, a second resist pattern 10 is formed so as to cover the MONOS region 101.

  Next, as shown in FIG. 3A, using the second resist pattern 10 as a mask, the exposed silicon oxide film 9 in the high breakdown voltage transistor region 100 and the low breakdown voltage transistor region 102 is wet etched with hydrofluoric acid. To remove. Although the silicon oxide film 9 is removed here by wet etching using hydrofluoric acid, the silicon oxide film 9 may be removed by dry etching.

  Next, as shown in FIG. 3B, after the second resist pattern 10 is removed, the silicon nitride film 8 in the high breakdown voltage transistor region 100 and the low breakdown voltage transistor region 102 is removed by wet etching with hot phosphoric acid. Since wet etching with hot phosphoric acid has a high selection ratio between a silicon nitride film and a silicon oxide film, the silicon oxide film 9 in the MONOS region 101 is not etched, and the high breakdown voltage transistor region 100 and the low breakdown voltage transistor region 102 are nitrided. The silicon film 8 can be removed. In the high breakdown voltage transistor region 100, the first gate insulating film 5 formed under the silicon nitride film 8 is hardly reduced.

  Next, as shown in FIG. 3C, a third resist pattern 11 is formed so as to cover the high voltage transistor region 100 and the MONOS region 101. Thereafter, using the third resist pattern 11 as a mask, the exposed silicon oxide film 3 in the low breakdown voltage transistor region 102 is removed by wet etching using hydrofluoric acid.

  Next, as shown in FIG. 4A, after the third resist pattern 11 is removed, a second gate insulating film 12 in the low breakdown voltage transistor region 102 is formed by a thermal oxidation method. As a result, the first gate insulating film 5 of 70 nm is formed on the silicon substrate 1 in the high breakdown voltage transistor region 100.

  Next, as shown in FIG. 4B, a polysilicon film 14 is formed on the entire surface of the substrate including the high breakdown voltage transistor region 100, the MONOS region 101, and the low breakdown voltage transistor region 102 by the CVD method. Thereafter, a fourth resist pattern 13 is formed on the polysilicon film 14.

  Next, as shown in FIG. 4C, the high-voltage transistor region 100, the MONOS region 101, and the low-voltage transistor region are formed by processing the polysilicon film 14 by dry etching using the fourth resist pattern 13 as a mask. Each of the gate electrodes 14 is formed at 102.

  Next, as shown in FIG. 4D, after the fourth resist pattern 13 is peeled off, in the MONOS region 101 and the low breakdown voltage transistor region 102, an LDD (Lightly Doped Drain) region 16 formed of a low concentration impurity layer on the silicon substrate 1. , 17 are formed. Next, sidewalls 15 are formed on the sidewalls of the gate electrode 14. Thereafter, in the high breakdown voltage transistor region 100, the MONOS region 101, and the low breakdown voltage transistor region 102, diffusion layers 18, 21, 23 of source / drain regions are formed on the silicon substrate 1 by impurity layers. Further, the silicon oxide film 3 formed in the high breakdown voltage transistor region 100 is removed during the transistor formation process.

  As described above, according to the embodiment of the present invention, in the high voltage transistor region 100 and the low voltage transistor region 102, the second silicon oxide film 9 is wetted with hydrofluoric acid as shown in FIGS. The silicon nitride film 8 is removed by wet etching using hot phosphoric acid. Therefore, unlike in the case of removing by dry etching, plasma damage does not occur in the high breakdown voltage transistor region 100 and the low breakdown voltage transistor region 102. As a result, the reliability of the gate insulating film in the high breakdown voltage transistor is improved.

  If the second silicon oxide film 9 and the silicon nitride film 8 on the first gate insulating film 5 in the high breakdown voltage transistor region 100 are removed by dry etching as in the prior art, the first gate insulating film 5 is reached. Whereas the film is reduced, the first gate insulating film 5 is hardly reduced when removed by wet etching as in the present embodiment. Therefore, the oxidation time for thermally oxidizing the first gate insulating film in the step shown in FIG. 1D can be shortened as compared with the prior art.

  2C, when the silicon nitride film 8 and the second silicon oxide film 9 are formed by the batch type CVD method, the silicon nitride film and the second silicon oxide film 9 are also formed on the back surface of the silicon substrate 1. A silicon oxide film is deposited (not shown). When the second silicon oxide film 9 and the silicon nitride film 8 are removed by dry etching as in the prior art, the silicon nitride film and the second silicon oxide film deposited on the back surface are not removed, and as a result, the film This may cause warpage of the silicon substrate (wafer) 1 due to stress. On the other hand, in this embodiment, the silicon nitride film 8 and the second silicon oxide film 9 are removed by wet etching using a method in which the silicon nitride film 8 and the second silicon oxide film 9 are immersed in an etching tank. The silicon oxide film is removed, and as a result, generation of warpage of the wafer 1 due to film stress can be suppressed.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.

(A), (b), (c) and (d) is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention. (A), (b), (c) and (d) is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention. (A), (b) and (c) is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention. (A), (b), (c) and (d) is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... LOCOS oxide film, 2a ... Offset film, 3, 9 ... Silicon oxide film, 4, 8 ... Silicon nitride film, 5 ... 1st gate Insulating film, 6 ... first resist pattern, 7 ... tunnel oxide film, 10 ... second resist pattern, 11 ... third resist pattern, 12 ... second gate insulation Film, 13 ... fourth resist pattern, 14 ... gate electrode (polysilicon film), 15 ... sidewall, 16, 17 ... LDD region, 18, 21, 23 ... source Drain region, 19, 22 ... N-type well region, 20 ... N-type offset region, 100 ... High breakdown voltage transistor region, 101 ... MONOS region, 102 ... Low breakdown voltage transistor region

Claims (4)

In a method of manufacturing a semiconductor device having a MONOS type memory transistor region and a transistor region on the same semiconductor substrate,
Forming a gate insulating film on the semiconductor substrate in the transistor region;
Forming a tunnel oxide film on the semiconductor substrate in the MONOS type memory transistor region, forming a silicon nitride film on the tunnel oxide film in the MONOS type memory transistor region and on the gate insulating film in the transistor region; Forming a silicon oxide film on the silicon nitride film;
Forming a mask film on the silicon oxide film in the MONOS type memory transistor region, and removing the silicon oxide film in the transistor region using the mask film as a mask;
Removing the silicon nitride film in the transistor region by wet etching with hot phosphoric acid using the mask film as a mask;
A method for manufacturing a semiconductor device, comprising: In a method for manufacturing a semiconductor device having a MONOS type memory transistor region, a high breakdown voltage transistor region, and a low breakdown voltage transistor region on the same semiconductor substrate,
Forming a gate insulating film on the semiconductor substrate in the high breakdown voltage transistor region;
A tunnel oxide film is formed on the semiconductor substrate in the MONOS type memory transistor region and on the semiconductor substrate in the low breakdown voltage transistor region, and silicon nitride is formed on the tunnel oxide film and the gate insulating film in the high breakdown voltage transistor region. Forming a film and forming a silicon oxide film on the silicon nitride film;
Forming a mask film on the silicon oxide film in the MONOS type memory transistor region, and removing the silicon oxide film in each of the high breakdown voltage transistor region and the low breakdown voltage transistor region using the mask film as a mask;
Removing the silicon nitride film in each of the high breakdown voltage transistor region and the low breakdown voltage transistor region by wet etching with hot phosphoric acid using the mask film as a mask;
A method for manufacturing a semiconductor device, comprising:   3. The method for manufacturing a semiconductor device according to claim 1, wherein the step of removing the silicon oxide film is a step of removing the silicon oxide film by wet etching using hydrofluoric acid. In a method for manufacturing a semiconductor device having a MONOS type memory transistor region, a high breakdown voltage transistor region, and a low breakdown voltage transistor region on the same semiconductor substrate,
A first silicon oxide film is formed on the semiconductor substrate in each of the MONOS type memory transistor region, the high breakdown voltage transistor region, and the low breakdown voltage transistor region, and a first silicon nitride film is formed on the first silicon oxide film. Forming a step;
Removing the first silicon nitride film and the first silicon oxide film in the high breakdown voltage transistor region;
Forming a gate insulating film on the semiconductor substrate in the high breakdown voltage transistor region by a selective oxidation method using the first silicon nitride film in each of the MONOS type memory transistor region and the low breakdown voltage transistor region as a mask;
Removing the first silicon nitride film in each of the MONOS type memory transistor region and the low breakdown voltage transistor region;
Covering each of the high breakdown voltage transistor region and the low breakdown voltage transistor region with a first mask film, and removing the first silicon oxide film in the MONOS type memory transistor region using the first mask film as a mask;
Removing the second mask film;
A tunnel oxide film is formed on the semiconductor substrate in the MONOS type memory transistor region, and the first silicon oxide film in the tunnel oxide film, on the gate insulating film in the high breakdown voltage transistor region, and in the low breakdown voltage transistor region. Forming a second silicon nitride film thereon, and forming a second silicon oxide film on the second silicon nitride film;
A second mask film is formed on the second silicon oxide film in the MONOS type memory transistor region, and the second withstand voltage transistor region and the second withstand voltage transistor region are respectively used as the mask with the second mask film as a mask. Removing the silicon oxide film,
Removing the second silicon nitride film in each of the high breakdown voltage transistor region and the low breakdown voltage transistor region by wet etching with hot phosphoric acid using the second mask film as a mask;
A method for manufacturing a semiconductor device, comprising:

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