TWI303538B - Method of fabricating printed circuit board for mounting light emitting diode chip and light emitting diode package having the circuit board - Google Patents

Method of fabricating printed circuit board for mounting light emitting diode chip and light emitting diode package having the circuit board Download PDF

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Publication number
TWI303538B
TWI303538B TW95150038A TW95150038A TWI303538B TW I303538 B TWI303538 B TW I303538B TW 95150038 A TW95150038 A TW 95150038A TW 95150038 A TW95150038 A TW 95150038A TW I303538 B TWI303538 B TW I303538B
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Taiwan
Prior art keywords
substrate
circuit board
emitting diode
printed circuit
light
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TW95150038A
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English (en)
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TW200803646A (en
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Tae Kwang Kim
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Seoul Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09645—Patterning on via walls; Plural lands around one hole
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10106—Light emitting diode [LED]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
    • H05K3/182—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
    • H05K3/184—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method using masks

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Led Device Packages (AREA)

Description

九、發明說明： 【聲明所屬之技術領域】 本發明關於载置發光二極體晶片之 去以及使用此丨則％路板的製造 < 便用此兒路板的發光二極體封裝士 電法以及具有印 心刷電路板的上部以及 卜二極體晶片之;刷=5之情況下電連接載 【先騎技術】 卩刷⑨路板的頂表面及底表面。 ，著電子設備變得輕便、薄、短 4減重、高整合、封装且由個人可經 :圖案化、小型化及封 :刷琶路板 、亦即，用作建構苴 日日月之印刷電路 ^封裝之基板的印刷電::f:備内之小部分之發光二極 7面，雖然形成載== 的方法可句括佶爾、s 、LED日日片之印刷電路板之带 之情況下，多個電極應形成:月待載置於印刷電路极上 動各別發光二極體晶:路板之—側以個別地 法以糊於印刷電 使用通孔而使電極形成;^電極之印刷電路板， 〜路板之-側。圖I至圖3 刀別為說明習知發光二極 :見圖、俯视圖以及仰視圖：：至0電路板之實例的剖 二電極之基板，其中兩個電=二f例展示具有四 陰極。 栓運接至發光二極體之陽極與 如圖1中所說明，電極 成於印刷電路板u之兩端，且 =_epattem) 12形 案12中。發光晶片（未圖亍丄刀別形成於電極圖 相II i r 樹脂部分14形成於發光晶片上。 相關技術之印刷上 十至數百晶片基板（如圖;j態使得首先製備數 設計單元之圖案，經由鑽孔處===板上 定位置對多個涓力、公> 上 仕设幻v白層昼板上之預 鍍電極圖荦12及通孔13 2理讀由^案錢處理而電 底表面 通孔13之内壁以電連接基板之頂表面與 接著，藉由鋸切處理沿通孔13 至數百基板單元形成於苴J L面板（數十 ==置Μ二極體晶片之印刷電路板單元。如圖2以 0所不’猎域切處理卿成於電 13切割為兩個半圓。 口木u上之逋孔 形成處理完成之後，發光二極體晶以未圖示） 、'&載置於基板上且u由諸如導雜合（_ 接方法而電連接至美柘，θ蛀輩々於， g; a^ 在發光二鋪^上形成 由。者口衣减月曰或聚石夕氧樹脂之材料製成之樹脂部分 工3〇3以為 14，如圖1所示。因此，完成發光二極體封裝。 —其後，將成品發光二極體封裝載置於主印刷電路 預定位置上以用於最終成品，且封裝之兩端（亦即壯 之形成電極襯墊（electrocjepacj)的部分）經 、衣 主印刷電職。 、、_且連接至 =上文所述，為了在載置發光二極體晶片之印刷電路 、>成電極，通孔按照慣例應如圖丨所示鐵穿電極 以使頂側與底側上之電路彼此連接。 木 鑽孔述相關技術之方法，通孔應鑽穿印刷電路板且 a孔亦應經電鍍以電連接印刷電路板之頂侧* =因此1要邊緣寬度及形成孔洞所需之空間而導= =小之增加。因此，不能完成諸如產品之小型及 a的近來產品趨勢。 问支 此外，在製造印刷電路板之製程中必要地 孔之製程，且存在較高概率在電鍍處理 通孔之内部部分。 犯充分電鍍 ，外’由於在載置發光晶片之後的樹脂部分1 =:=_漏至通孔中或一 =或執行其他處理製程時封裝失效發 之區=i由於電極騎12之預定區由於通孔13所佔據 職;光:極體频^ τ不此保§豆區上之充足量的焊料。另外，歸因於 13簡 電極圖案上之凹陷通孔， 性。 枓了属性退化而導致較差可焊 【發明内容】 【技術問題】 本每明之目標為提供根據電 近來趨勢的载置發光二極體晶片之型化及高整合之 以及具有印刷電路板之發光二極體=稱板之製造方法 可消供印，板之製造方法q 缺陷的可能性且可簡印之製程期間產生之 二極體封裝。 ）及具有印刷電路板之發光 本發明之又—目標為提 可解決歸因於印刷電路板 之製造方法（其 時產生之可焊性問題） L而在载置主印刷電路板 封裝。 _以及具有印刷電路板之發光二極體 【技術解決方案】 根據本發明之態樣，提供載置發 电路板之製造方法，包含以 —木版曰日片之印刷 墊之基板，乂’卞·衣備具有多個電極襯 頂表面及底表面上=域以形成槽從而允許形成於基板之 暴露側面選擇性地電鍵基c 各別暴露電極襯塾成表面與底表面上的 及將基板則為個別單元用於載置 ^03¾ 發光二極體晶片。 J據本發明之另一態樣’提供載置發光二極體晶片之 極體as片之基板；切割基板之所選區域以形成槽 吹允許基板之侧面得以暴露；在基板之頂表面與底 =對形成多個電極襯墊且選擇性地電鑛基板之頂表面鱼 座=以及基板之側面以電連接成對形成於基板之頂表面 個上的各別電極襯墊；以及將基板切割為足以载置 個別發光二極體晶片之單位大小。 尺直 勺人根據本發明之又—態樣，提供—種發光二極體封裝， 其:=極:晶片》:ϋ載置具有直侧之基板;電極圖 頂^ ; 形狀覆盍基板之兩端且電連接基板之 以連：if面；多個發光二極趣，其載置於基板上 極體曰^圖案，以及樹脂部分，其用於使多個發光二 安:成形。此外’四個或四個以上的偶數數目電極圖 木一半配置於基板之兩端中之每一者上。 【有利效應】 近來發明’可製造根據電子設備小型化及高整合之 此=的用於载置發光二極體晶片之印刷電路板。 期 卜可/肖除歸因於通孔而在製造印刷電路板之製程 /、曰生之缺陷的可能性且亦可簡化製程。 而 可解决歸因於相關技術之印刷電路板上之通孔 置主印刷電路板時產生之可焊性問題。 I303_ 【實施方式】 【最佳模式】 圖4為說明根據本夢 圖，電極襯#22形成於^刷^電路板之部分的平面 所不之箭頭的方向所見之剖視^。板21上。圖5為自圖4 如圖4以及圖5所示，:二 ，板21上圖案化電極襯墊土 1 極體晶片之印刷 鍍圖案以及H由在上㈣以了猎由在絕緣基板上電 層屡板）上形成抗钱刻圖宰^^基板（例如，覆銅箔 處理。 ，、y成电極襯墊22以執行蝕刻 圖4 r祝明將四個電極襯墊 ，發光日_砂此單位基板上。單位為早且將兩 電極襯塾之數目秘細，=基板23巾所包括之 至單位基板之發光晶片之數目—可切I _地待載置 干f—了，電錢基板21之形成電極襯墊的側面，如圈6所 二單峨r的包括單位基板心 ,," 之上°卩之部分基板，使得可形成槽24。芮口 化切塊機可用於形成槽24。 商口口 、、圖7為自圖6所示之箭頭的方向所見之剖視圖 上述切副處理而暴露單位基板之兩個侧面。 經由 =’如圖8及圖9中所示，選擇性地電鑛電極概塾 土板21之槽24内的侧面以形成電鍍層25,使得基板 21之頂表面與底表面上之電極襯墊22可彼此連接。 為了僅選擇性地電鍍電極襯墊22在槽24内之侧面， 10 1303 縱 表面彼此電連接。 概塾雖實施例中解釋4電極基板之電極 板。可根據電=:::= 有各種電極襯塾的基 片。提供偶數數目之電極概塾===光晶 中的每一者上。 干配置於基板之兩側 觀塾=板在中施T，可能同時在上面未形成電極 之頂表面與底表面上形成抗電鍍圖 面與底表面上形= 樹脂部分27使發光㈣未，）載置於基板21上且以 由導線電連接至電極襯墊2 置處且接著經 成形處理而形成樹脂部分27二線i合f理之後，經由 脂可_脂物以用於二 ^^^.#,^Mtransfer mold:;} 27 〇 卜树月曰口p分27中可含有碟 片之光，使得可產生具有不同波長之光。Μ自毛先曰曰 表面:=電= 技術之發光二成通孔之狀態連接，此與相關 1303^¾ 【主要元件符號說明】 11 :印刷電路板 12 :電極圖案 13 :通孔 14 :樹脂部分 21 :印刷電路板/基板 22 :電極襯墊/電極圖案 22a:電極圖案 22b :電極圖案 22c ··電極圖案 22d :電極圖案 23 :單位基板 23a :單位基板 23b :單位基板 24 槽 25 電鍍層 26 槽 27 樹脂部分 29 主印刷電路板 30 電極 31 焊料 14

Claims (1)

13〇3織 十、申請專利範圍： 之印刷電路板之方 1.一種製造載置發光二極體晶片 法，包含·· (a) 製備具有多個電極補執 ,、、 位观墊之基板，所述電極襯墊 成對地形成於所述基板之頂表面與底表面上，· (b) 切割所述基板之所選區域以形成槽從而允許形 成於所述基板讀_表面麵述絲面上之所述各別 電極襯墊關面以及置放於所述各別電極襯墊之間 述基板之侧面得以暴露； 、（c)選擇性地電鍍所述基板之所述暴露侧面以電 接成對形成於所述基板之所述頂表面與所述底表面上 所述各別暴露電極襯墊；以及 、 (d)將所述基板切割為個別單元用於载置夢 體晶片。 又—蚀 2.如申凊專利範圍第1項所述之製造载置發光二極徵 晶片之印刷電路板之方法，其中步驟（a)包含圖案化與^ φ 鍍所述基板上之所述電極襯墊的步驟。 3·如申請專利範圍第1項所述之製造載置發光二極趲 晶片之印刷電路板之方法，其中步驟（c)包含以下步驟： 在所述基板之所述暴露側面之除了待電鍍之部分的 剩备、邛分上形成抗電鍍圖案；以及 對所述基板執行電鍍處理。 曰4·如申請專利範圍第丨項所述之製造載置發光二極體 晶片之印刷電路板之方法，其中在步驟（b)中，所述槽^ 15 I3〇3m 使得所述多個電極襯墊之所述側面藉由單一槽而暴霞 式形成。 Ό刁方 5. 如申請專利範圍第1項所述之製造載置發光二 晶片之印刷電路板之方法，其中在步驟（b)中，對二= 電極襯墊中之每一者形成槽。 、斤述 6. 如申請專利範圍第1項所述之製造載置發 晶片之印刷電路板之方法，其中所述多個電極有見細夕續 列而配置於所述基板上，且步驟（b)包含形成槽使：固 個鄰近列而配置之電極襯墊之侧面藉由單一 二兩 驟。 *路的步 7·種製造載置發光二極體晶片之印刷電路拓 法，包含以下步驟： '^方 (a) 製備用於載置多個發光二極體晶片之基 (b) 切割所述基板之所選區域以形成槽從而土 ’ 述基板之側面得以暴露； 千所 ㈦在所縣板之頂表面與絲面上成 笔極襯墊且選擇性地電觀述餘之所述 ^個 =面以及所述基板之所述側面以電連接成二斤述 Ϊ基::所述頂表面與所述底表面上的所述各別ί:: 片之單述基板切割為足以載置個別發光二極體晶 8.如申請專利顧第7項所述之製 “之印刷電路板之方法，其中步驟“)包含圖 16 鍍所述電極襯塾的步驟。 义如申凊專利範園第7 、 晶片之印刷電路板之方法，其製造载置發光二極體 在所述基板之所诚異命乂 “（c)包含以下步驟·· 剩餘部分上形成抗電鍍圖案：：：除了待電鍍之部分的 對所述基域行電鍍處理。 ΐ〇·如申請專利範圍第7 體晶片之印刷電路板之方法，苴 衣造截置發光二極 以使得所述多個電極概塾之侧面=驟（b)中，所述槽 形成。 3由早一槽而暴露的方式 U.如申請專利範圍第7項所述之制、生 晶片之印刷電路板之方法，：，載置發光二極體 電極襯墊中之每一者形成槽/。、 乂恥（b)中，對於所述 個列而配置於所述基板上，且步驟電極襯塾以多 ;r列而配置之電極《之側=== I3·一種發光二極體封裝，包含： ^光二極體晶片，其載置具有直側之基板； 伽曰，翻独“[，，形狀覆蓋所述基板之兩 =連接所述基板之頂表面與底表面； 夕個务光二極體晶月，其經載置於所述基板上以連 接至所述電極圖案；以及 17 1303 娜 樹脂部分，其用於使所述多個發光二極體晶片成形， 其中四個或四個以上的偶數數目電極圖案之一半配 置於所述基板之兩侧中之每一者上。 18
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