TWI300622B - Method of forming gate electrode in semiconductor device - Google Patents

Method of forming gate electrode in semiconductor device Download PDF

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Publication number
TWI300622B
TWI300622B TW092133188A TW92133188A TWI300622B TW I300622 B TWI300622 B TW I300622B TW 092133188 A TW092133188 A TW 092133188A TW 92133188 A TW92133188 A TW 92133188A TW I300622 B TWI300622 B TW I300622B
Authority
TW
Taiwan
Prior art keywords
film
gate electrode
forming
gas
annealing process
Prior art date
Application number
TW092133188A
Other languages
English (en)
Other versions
TW200501410A (en
Inventor
Cha Deok Dong
Ho Min Son
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200501410A publication Critical patent/TW200501410A/zh
Application granted granted Critical
Publication of TWI300622B publication Critical patent/TWI300622B/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • General Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Drying Of Semiconductors (AREA)

Description

1300622 玖、發明說明： 【發明所屬之技術領域】 本發明係關於一種在一半導體元件中形成一閘電極之方 法，且詳言之，本發明係關於一種在一半導體元件中形成 以一多晶金屬矽化物結構構成之一閘電極之方法。 【先$技術】 由於半導體元件係高度集成者，因此閘電極主要以多晶 金屬矽化物結構構成，在該結構中，為了改良構成該閘電 極之多晶矽膜之低阻抗之標的，會將一金屬矽化物膜沈積 在一多晶矽膜之上表面上，藉此形成該閘電極。在以多晶 金屬矽化物結構形成閘電極之過程中，蝕刻該多晶矽膜及 一矽化鎢膜，即一金屬矽化物膜，藉此形成一具有垂直輪 廓之閘電極圖樣。 在蝕刻該矽化鎢膜之後，蝕刻該多晶矽膜。在蝕刻該矽 化鎢膜之％ ’使該多晶矽膜之多個部分產生了凹痕。然後 進行另蝕刻製程，藉此在產生了凹痕之多晶矽膜上圖 樣化該閘電極。結果，針對該多晶矽膜進行了二次蝕刻製 程。由於該二次蝕刻製程，造成該多晶矽膜之輪廓具有一 凹形狀’此處該多晶矽較之其他膜更加凹陷。 由於該多晶石夕獏具有前述之輪廟，因此難於以-垂直輪 郛形成4閘包極’從而可能劣化該元件特性。 【發明内容】 為解決前述問, ’本發明針對一種在半導體元件中形成 O:\89\895l7.DOC4 1300622 一問電極之方法，該方法透過構成該閘電極之垂直輪廓， 俾能防止該元件特性之劣化。 本發明提供一種在一半導體内形成一閘電極之方法，該 方法包括下述步驟：在一半導體基底之上部上依次形成一 多晶矽膜及一金屬矽化物膜；進行一退火製程，藉此結晶 化該金屬矽化物膜，促使該經結晶化之金屬矽化物膜之姓 刻率相似於該多晶矽膜之蝕刻率；以及藉由使用該經結晶 化之金屬矽化物膜和該多晶矽膜的相似蝕刻率，同時針對 該金屬矽化物膜和該多晶矽膜進行一蝕刻製程來形成一閘 電極。 該退火製程較佳係一快速熱處理（RTP)退火製程和一爐 内退火製程之一，該等退火製程用於結晶化一非晶金屬矽 化物膜，藉此形成一結晶化金屬矽化物膜。此外，其中較 佳在N2或ΝΑ氣體環境中在9〇〇至i〇0〇〇c範圍内之溫度下持 續10至30秒來進行該RTP退火製程，且其中較佳在乂或1^% 氣體環境中在850至1 〇〇〇〇(：範圍内之溫度下持續5至3〇分鐘 來進行該爐内退火製程。 該金屬矽化物膜較佳係矽化鎢膜。此外，較佳在用於蝕 刻該多晶矽膜之一製程條件下來進行該蝕刻製程。 而且，該蝕刻製程較佳係一乾式蝕刻製程，這是在一引 入了-由C12氣體和0 2氣體組成之混合氣體之感應耦合電 漿反應室中進行該乾式製程。 【實施方式】 在下述之說明中將結合附圖對本發明之前述方面及 O:\89\89517.DOC4 -8- 1300622 特徵進行說明。 現在’將參照附圖對本發明之較佳實施例加以詳細說明 。不過’可用各種類型之形式變更本發明之較佳實施例， 本《月之範圍不應S忍為侷限於下述之具體實施例。本發 明之該等較佳實施例僅用於為熟習本發明之技術者較清楚 地解釋本發明。故而，®中之薄膜之厚度等均加以誇大， 以利於較清楚地說明，且圖中相似之參考數字係用於指示 相同或相似之部分。而且，在本說明書中，，，某一薄膜位於 另薄膜之上或一半導體基底之上"此種措詞之含義係該 某一薄膜可直接接觸該另一薄膜或該半導體基底，或另外 也可係於它們之間插入一第三薄膜。 圖1至圖4為用於說明根據本發明一實施例之在半導體元 件内形成閘電極之方法之截面圖。 參照圖1，於由矽製成之半導體基底1〇之整個上表面上依 次形成一隧道氧化膜12、一構成一浮閘電極之第一多晶矽 膜14、一構成該浮閘電極之第二多晶矽膜16、一介電膜18 構成控制閘電極之第二多晶♦膜20、一梦化鶴膜22a 及一硬光罩24。形成該隧道氧化膜12的方式為，於75〇至 80CTC溫度下之濕式氧化處理，然後於义氣體環境下以9⑼ 至910。(：溫度下持續20至30分鐘之熱處理。藉由低壓化學氣 肢沈積法（下文中稱為LP-CVD法），使用一如SiH4或SiH^等 Si源氣體及一 PH3氣體以500至550°C溫度於約⑴丨至]托之壓 力下，將該構成浮閘電極之第一多晶秒膜14形成為厚度約7〇 至150埃。可於相似於該第一多晶矽膜14之製程條件下，將 O:\89\89517.DOC4 -9- 1300622 該構成浮閘電極之該第二多晶矽膜16形成為厚度約600至 1400埃。較佳地，按照ΟΝΟ結構形成該介電膜18，即，依 次形成一第一氧化膜、一氮化膜及一第二氧化膜的堆疊結 構。此時，將第一氧化膜和第二氧化膜裝入一反應室中， 以約600至700。(：之溫度範圍内進行製程，藉由lP-cvD法在 低於1至3托之壓力下以約810至850〇c之溫度將該等氧化膜 形成為厚度約35至60埃，並使用SiH2Cl2(二氣矽烷：DCS) 氣體作為源氣體將該等氧化膜之一形成為一高溫氧化 (HTO)膜，並使用比〇氣體作為源氣體將另一氧化膜形成為 另一 HT0膜。藉由LP-CVD法，使用NH3氣體和SiH2Cl2氣體 作為反應氣體，在低於1至3托之壓力下以650至800°C之溫 度將該氮化氧化膜形成為厚度約5 〇至6 5埃。然後，在形成 介電膜18之後，為了改良介電膜1 8之特性及加固膜層間邊 界’藉濕式氧化方式在約750至800。(：之溫度下進行一蒸汽 退火製程。進行該蒸汽退火製程係用以在介電膜18之沈積 之後無時間延遲地形成一厚度為150至300埃之氧化膜，藉 此防止任一自然氧化膜及由雜質造成之污染。藉由LP-cvd 法，使用如SiHU或SiH6等Si源氣體以及ph3氣體在〇·ι至3托 之壓力下以500至550〇C之溫度，將該構成控制閘電極之該 弟二多晶石夕膜20形成為厚度70至150埃。該石夕化鎢膜22係一 非晶矽化鎢膜。藉由SiH4(曱矽烷：MS)或SiH2Cl2(二氯矽烷 :DCS)與WF6之反應，然後藉由在3〇〇至5〇〇〇c之溫度下調 節2.0至2.8之理想配比值，將該膜形成為具有⑼至 埃之厚度，藉此實現一良好階梯覆蓋並最小化該矽化鎢膜 O:\89\89517.DOC4 -10- 1300622 的表面阻抗。此時’形成厚度該刚⑴埃之碎化鶴膜 22係考慮了減少總厚度約2〇%之情形，即，在隨後退火製 程中減少總厚度約200埃。 參照圖2,針對該產生物進行一退火製程。藉由該退火製 程，使該非晶矽化鎢膜22a結晶為具有該膜之特性，即，與 第三多晶矽膜20相類似之蝕刻率。若該結晶化之矽化鎢膜 22b之蝕刻率相似於第三多晶矽膜2〇之蝕刻率，則可在用於 圖樣化閘電極之蝕刻製程中，藉由一次蝕刻作業同時蝕刻 該結晶化之矽化鎢膜22b及該第三多晶矽膜2〇。此時所使用 之退火製程係一 RTP退火製程或一爐内退火製程。此處，會 在N2或NH3氣體環境中以900至1〇〇〇<>c之溫度持續1〇至3〇秒 來進行該RTP退火製程係，而在乂或況札氣體環境中以85〇 至1000。(：之溫度持續5至30分鐘來進行該爐内退火製程係 。此外，在該退火製程中，總厚度為1〇〇〇至12〇〇埃之矽化 鎢膜22b的厚度減小了 200埃，即，總厚度之2〇%，並因此 使該石夕化鎢膜之厚度為8〇〇至1〇〇〇埃。 參照圖3 ’藉由使用作為光罩而形成於該産生物上之硬光 罩24進行蝕刻製程，藉此形成一閘電極圖樣G p·。首先，藉 由使用該硬光罩24以針對該結晶化之矽化鎢膜22b及該第 二多晶石夕膜20來進行蝕刻製程，藉此形成經圖樣化之矽化 鎢膜22P及經圖樣化之第三多晶矽膜2〇p。由於蝕刻製程所 處理的該經結晶化之鎢膜22b及該第三多晶矽膜20之蝕刻 率彼此相似，因此會同時蝕刻該等兩個膜。因此，為了形 成閘電極，需對該結晶化之矽化鎢膜22b及該第三多晶矽膜 O:\89\895l7.DOC4 -11- Ϊ300622 2〇進行一次姓刻製程，並因此，可防止該第三多晶矽膜20 幵> 成任何凹痕，而得以形成具有垂直輪廓之閘電極圖樣。 4餘刻製程係乾式蝕刻製程，這是在引入了混合比例為4:6 之Cl2和〇2之混合氣體之感應耦合電漿反應室中來進行該 乾式蝕刻製程。由於在該蝕刻製程中，認為該經結晶化之 夕化鎢膜22b及該第三多晶矽膜2〇之蝕刻率相似，因此在相 似於该第三多晶矽膜2〇上之蝕刻製程之製程條件下來進行 忒乾式蝕刻製程。下文中，若藉由利用已圖樣化為前述垂 直輪廓之第三多晶矽膜20p及矽化鎢膜22P來蝕刻下方膜， 則形成了經圖樣化之介電膜18p、第二多晶矽膜16p、第一 多晶石夕膜14P及隨道氧化膜12p，藉此完成了具有垂直輪摩 之閘電極圖樣G.P.之形成。 參照圖4,針對前述閘電極圖樣αρ·進行氧化製程。首先 、，為準備氧化製程，針對閘電極圖樣Gp·進行清洗製程。爲 進仃清洗製程，使用一種SC-1(NH4〇h/H2〇2/h2⑺清洗劑， 該清洗劑幾乎不會破壞㈣氧化膜12和介電㈣之氧化膜 ’從而不會降低具有前述垂直輪廓之閘電極圖樣以之側壁 之傾斜度。當針對該產生物之整體表面進行氧化製程時， 會在具有垂直輪，之閘電極圖樣Gp•上形成一均句氧化膜 %，而得以穩定側壁之粗糙度。此時，可藉由乾式氧化法 在750至95〇°C之溫度下進行該氧化製程，在〇2氣體為丨至 1〇Sim的製程條件下，該乾式氧化法易於控制氧化率。 化：=?明之該等較佳實施例，藉由-退火製程使财 b & m時間㈣該多晶石夕膜及該經結 O:\89\89517.DOC4 -12- 1300622 晶化之石夕化鶴膜，藉此防止該多晶矽膜形成任何凹痕，而 得以形成具有垂直輪廓之閘電極圖樣。 雖然前述實施例揭示了在一快閃記憶體裝置中具有一多 晶金屬石夕化物結構之閘電極，但本發明可適用於任何用於 形成具有多晶金屬矽化物結構之閘電極之製程。 如上述，按照本發明，藉由在退火製程中結晶化矽化鎢 膜，在同一時蝕刻該多晶矽膜和經結晶化之矽化鎢膜，藉 此防止多晶矽膜形成任何凹痕，而得以形成了具有垂直輪 廓之閘電極圖樣，俾能獲得防止元件性能劣化之效果。 雖然前面所做介紹係參照該等較佳實施例而做出者，但 應當瞭解，_ t此項技藝者可對本發明進行多種改變和修 改，而並不會超出本發明和所附申請專利範圍之精神及範 圍。 【圖式簡單說明】 圖1至圖4係根據本發明之一實施例，用於說明一種在半 導體元件内形成閘電極之方法之截面圖。 【圖式代表符號說明】 G.P. 閘電極圖樣 10 半導體基底 12,12P 隧道氧化膜 14，14P 第一多晶碎膜 16，16P 第二多晶矽膜 18 介電膜 18P 圖樣化介電膜 O:\89\89517.DOC4 -13- 1300622 20,20P 第三多晶矽膜 22a，22P 石夕化鶴膜 22b 結晶化碎化嫣膜 24 硬光罩 26 氧化膜 O:\89\89517.DOC4 -14-

Claims (1)

1300622 拾、申請專利範圍： 1. 一種在一半導體内形成一閘電極之方法，包括下述步驟： 在一半導體基底之上部上依次形成一多晶石夕膜及一金 屬矽化物膜； 進行一退火製程，藉此結晶化該金屬矽化物膜，促使 遠經結晶化之金屬矽化物膜之蝕刻率相似於該多晶矽膜 之蝕刻率；以及 藉由使用5亥經結晶化之金屬石夕化物膜和該多晶♦膜的 相似蝕刻率，同時針對該金屬矽化物膜和該多晶矽膜進 行一蝕刻製程來形成一閘電極。 2·如申請專利範圍第丨項之在一半導體内形成一閘電極之 方法，其中該退火製程係一快速熱處理（RTp)退火製程和 爐内退火製程之一，用以結晶化一非晶金屬梦化物膜 ’藉此形成一結晶化金屬矽化物膜。 3·如申請專利範圍第2項之在一半導體内形成一閘電極之 方法’其中在N2或NH3氣體環境中以9〇〇至i〇〇〇〇c範圍内 之溫度下持續10至30秒來進行該rtp退火製程，以及其中 在N2或NH3氣體環境中以850至1〇〇〇〇C範圍内之溫度下持 續5至30分鐘來進行該爐内退火製程。 4.如申請專利範圍第1項之在一半導體内形成一閘電極之 方法，其中該金屬矽化物膜係一矽化鎢膜。 5·如申請專利範圍第1項之在一半導體内形成一閘電極之 方法，其中在一用於|虫刻該多晶石夕膜之製程條件下來進 行該蝕刻製程。 O:\89\895l7.DOC5 1300622 6·如中請專利範圍第5項之在一丰導舻 ,^ 牛導體内形成〜Mg 方法’其令該蝕刻製程係一乾式蝕刻製程，$ :】極之 入了由體和〇2氣體組成之混合氣體之感應耦合電 漿反應室中來進行該乾式製程。 7.如申請專利範圍第1項之在-半導體内形成-閉電極之 方法’其中㈣刻製程係-乾式㈣製程，這是在一弓| 入了由Cl2氣體和〇2氣體組成之混合氣體之感應耦合電 衆反應室巾來進彳”乾式製p O:\89\895l7.DOC5 -2-
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KR100673242B1 (ko) * 2005-06-24 2007-01-22 주식회사 하이닉스반도체 플래쉬 메모리 소자의 유전체막 제조방법
KR100714039B1 (ko) * 2006-05-10 2007-05-04 주식회사 하이닉스반도체 반도체 소자의 제조 방법

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH047822A (ja) * 1990-04-25 1992-01-13 Fuji Xerox Co Ltd 半導体装置の製造方法
JPH0779102B2 (ja) * 1990-08-23 1995-08-23 富士通株式会社 半導体装置の製造方法
JP3327109B2 (ja) * 1996-04-08 2002-09-24 ソニー株式会社 半導体装置の製造方法
US6159811A (en) * 1996-05-15 2000-12-12 Samsung Electronics Co., Ltd. Methods for patterning microelectronic structures using chlorine, oxygen, and fluorine
JPH10223561A (ja) * 1997-02-10 1998-08-21 Nec Corp 半導体装置の製造方法
KR100425147B1 (ko) * 1997-09-29 2004-05-17 주식회사 하이닉스반도체 반도체소자의제조방법
US6376348B1 (en) * 1997-09-30 2002-04-23 Siemens Aktiengesellschaft Reliable polycide gate stack with reduced sheet resistance and thickness
JPH11289021A (ja) * 1998-04-02 1999-10-19 Hitachi Ltd 半導体集積回路装置およびその製造方法ならびにマイクロコンピュータ
US6380029B1 (en) * 1998-12-04 2002-04-30 Advanced Micro Devices, Inc. Method of forming ono stacked films and DCS tungsten silicide gate to improve polycide gate performance for flash memory devices
US6277736B1 (en) * 1998-12-08 2001-08-21 United Microelectronics, Corp. Method for forming gate
TW501199B (en) * 1999-03-05 2002-09-01 Applied Materials Inc Method for enhancing etching of TiSix
US6228695B1 (en) * 1999-05-27 2001-05-08 Taiwan Semiconductor Manufacturing Company Method to fabricate split-gate with self-aligned source and self-aligned floating gate to control gate
JP2001068670A (ja) * 1999-08-30 2001-03-16 Nec Corp 半導体装置の製造方法
KR20020044261A (ko) * 2000-12-05 2002-06-15 박종섭 플래쉬 메모리 셀의 제조 방법
JP2002359231A (ja) * 2001-05-31 2002-12-13 Hitachi Ltd 半導体集積回路装置の製造方法
US6642112B1 (en) * 2001-07-30 2003-11-04 Zilog, Inc. Non-oxidizing spacer densification method for manufacturing semiconductor devices

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US20040259369A1 (en) 2004-12-23
US7179707B2 (en) 2007-02-20
KR20040110016A (ko) 2004-12-29
JP2005012159A (ja) 2005-01-13
KR100497474B1 (ko) 2005-07-01
DE10354814A1 (de) 2005-01-05
TW200501410A (en) 2005-01-01

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