TW200501410A - Method of forming gate electrode in semiconductor device - Google Patents

Method of forming gate electrode in semiconductor device

Info

Publication number
TW200501410A
TW200501410A TW092133188A TW92133188A TW200501410A TW 200501410 A TW200501410 A TW 200501410A TW 092133188 A TW092133188 A TW 092133188A TW 92133188 A TW92133188 A TW 92133188A TW 200501410 A TW200501410 A TW 200501410A
Authority
TW
Taiwan
Prior art keywords
gate electrode
silicide film
film
metal silicide
forming
Prior art date
Application number
TW092133188A
Other languages
Chinese (zh)
Other versions
TWI300622B (en
Inventor
Cha-Deok Dong
Ho-Min Son
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200501410A publication Critical patent/TW200501410A/en
Application granted granted Critical
Publication of TWI300622B publication Critical patent/TWI300622B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

The present invention relates to a method of forming a gate electrode in the semiconductor device. The present invention provides a method of forming a gate electrode in a semiconductor, comprising the steps of: forming a polysilicon film and a metal silicide film sequentially on an upper portion of a semiconductor substrate; performing an annealing process to crystallize the metal silicide film, so that etch rate of the crystallized metal silicide film is similar to that of the polysilicon film; and forming a gate electrode by performing an etching process at one time on the metal silicide film and the polysilicon film using the similar etch rates of the crystallized metal silicide film and the polysilicon film. According to the present invention, the tungsten silicide film is crystallized by an annealing process and the polysilicon film and the crystallized tungsten silicide film are etched at one time to prevent any formation of recesses of the polysilicon film, so that it is possible to form the gate electrode pattern having the vertical profile.
TW092133188A 2003-06-20 2003-11-26 Method of forming gate electrode in semiconductor device TWI300622B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR10-2003-0040155A KR100497474B1 (en) 2003-06-20 2003-06-20 Method of forming gate electrode in semiconductor device

Publications (2)

Publication Number Publication Date
TW200501410A true TW200501410A (en) 2005-01-01
TWI300622B TWI300622B (en) 2008-09-01

Family

ID=33509724

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092133188A TWI300622B (en) 2003-06-20 2003-11-26 Method of forming gate electrode in semiconductor device

Country Status (5)

Country Link
US (1) US7179707B2 (en)
JP (1) JP2005012159A (en)
KR (1) KR100497474B1 (en)
DE (1) DE10354814B4 (en)
TW (1) TWI300622B (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4307919B2 (en) * 2003-06-27 2009-08-05 三洋電機株式会社 Manufacturing method of semiconductor device
KR100609942B1 (en) * 2004-01-09 2006-08-08 에스티마이크로일렉트로닉스 엔.브이. Method of manufacturing flash memory cell
KR100586009B1 (en) * 2004-05-31 2006-06-01 삼성전자주식회사 Method of manufacturing a semiconductor device and apparatus for performing the method
KR100673242B1 (en) * 2005-06-24 2007-01-22 주식회사 하이닉스반도체 Method for fabricating dielectric layer in flash memory device
KR100714039B1 (en) * 2006-05-10 2007-05-04 주식회사 하이닉스반도체 Method for fabrication a semiconductor device
WO2024176864A1 (en) * 2023-02-21 2024-08-29 東京エレクトロン株式会社 Etching method and plasma treatment device

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH047822A (en) * 1990-04-25 1992-01-13 Fuji Xerox Co Ltd Manufacture of semiconductor device
JPH0779102B2 (en) * 1990-08-23 1995-08-23 富士通株式会社 Method for manufacturing semiconductor device
JP3327109B2 (en) * 1996-04-08 2002-09-24 ソニー株式会社 Method for manufacturing semiconductor device
US6159811A (en) * 1996-05-15 2000-12-12 Samsung Electronics Co., Ltd. Methods for patterning microelectronic structures using chlorine, oxygen, and fluorine
JPH10223561A (en) * 1997-02-10 1998-08-21 Nec Corp Manufacture of semiconductor device
KR100425147B1 (en) * 1997-09-29 2004-05-17 주식회사 하이닉스반도체 Method for manufacturing semiconductor device
US6376348B1 (en) * 1997-09-30 2002-04-23 Siemens Aktiengesellschaft Reliable polycide gate stack with reduced sheet resistance and thickness
JPH11289021A (en) * 1998-04-02 1999-10-19 Hitachi Ltd Semiconductor integrated-circuit device and its manufacture as well as microcomputer
US6380029B1 (en) * 1998-12-04 2002-04-30 Advanced Micro Devices, Inc. Method of forming ono stacked films and DCS tungsten silicide gate to improve polycide gate performance for flash memory devices
US6277736B1 (en) * 1998-12-08 2001-08-21 United Microelectronics, Corp. Method for forming gate
WO2000052749A1 (en) * 1999-03-05 2000-09-08 Applied Materials, Inc. Method for enhancing etching of titanium silicide
US6228695B1 (en) * 1999-05-27 2001-05-08 Taiwan Semiconductor Manufacturing Company Method to fabricate split-gate with self-aligned source and self-aligned floating gate to control gate
JP2001068670A (en) * 1999-08-30 2001-03-16 Nec Corp Fabrication of semiconductor device
KR20020044261A (en) * 2000-12-05 2002-06-15 박종섭 Method of manufacturing a flash memory cell
JP2002359231A (en) * 2001-05-31 2002-12-13 Hitachi Ltd Manufacturing method of semiconductor integrated circuit device
US6642112B1 (en) * 2001-07-30 2003-11-04 Zilog, Inc. Non-oxidizing spacer densification method for manufacturing semiconductor devices

Also Published As

Publication number Publication date
TWI300622B (en) 2008-09-01
DE10354814A1 (en) 2005-01-05
KR20040110016A (en) 2004-12-29
US7179707B2 (en) 2007-02-20
KR100497474B1 (en) 2005-07-01
US20040259369A1 (en) 2004-12-23
JP2005012159A (en) 2005-01-13
DE10354814B4 (en) 2010-04-08

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees