TWI295071B - Method of manufacturing an electronic device and electronic device - Google Patents

Method of manufacturing an electronic device and electronic device Download PDF

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TWI295071B
TWI295071B TW091136510A TW91136510A TWI295071B TW I295071 B TWI295071 B TW I295071B TW 091136510 A TW091136510 A TW 091136510A TW 91136510 A TW91136510 A TW 91136510A TW I295071 B TWI295071 B TW I295071B
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nitrogen
copper
layer
seed layer
barrier layer
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TW200411737A (en
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Adrianus Maria Wolters Robertus
Maria Van Graven-Claassen Anouk
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Nxp Bv
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846Layer combinations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855After-treatment introducing at least one additional element into the layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864Thermal treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76867Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76871Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068Formation and after-treatment of conductors
    • H01L2221/1073Barrier, adhesion or liner layers
    • H01L2221/1084Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L2221/1089Stacks of seed layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

1295071 (1) 發明說明鑛頁 玖、發明說明 技術領域 本發明關於製造備有基板上之銅金屬化之半導體裝置之 方法,該銅金屬化包含一種子層及一銅金屬化層,該方法 包含一步驟以沉積銅於含氮之大氣中,以便形成一含銅及 氮之種子層,及形成銅金屬化層於該種子層上。 本發明亦關於備有基板之電子裝置,基板上有含金屬氮 化物之及銅金屬化之障礙層堆疊,該障礙層及銅金屬化有 一共同介面。 先前技術 眾所週知在積體電路内提供連接性係以金屬化及通路方 式完成。已成為半導體工業曰益知名之一種金屬化材料為 銅。但現存之缺點為發現其在經不同材料中迅速擴散,特 別在介電材料如氧化物。 尋求使用銅金屬化之半導體結構因此備有障礙材料,以 作為半導體本體之下面材料與銅金屬化隔離,俾防止半導 體中之擴散。含氮障礙材料證明為一適當選擇,但尚有在 黏接度之缺點,該黏接度程度可在障礙層與銅種子層之間 達成,該層係在隨後之銅金屬化層之電子沉積之前沉積在 障礙層上。形成該結構之一部分之銅金屬化磁道引起之表 面電阻亦為其缺點。 美國專利US-A-6 174 799揭示一電子裝置及一製造如本發 明開頭段落所述種類裝置之相對應的方法,該方法中,種
I 1295071 (2) --- SHi銳明鑛麗 子層,鋼及鎂,鍚或紹合金。此種子層在氮大氣下沉# _ ^辰^在種子層沉積進行時降低,因而可提供―展現> . 種子層°此氮含量之分級可使接近障礙層之冑 子層有阿/辰度之氮,而遠離障礙層之種子層區域,即形 成銅金屬化層電沉積之表面之氮濃渡甚低甚至無氮。或者 種子層可含二氮含量不同之子層。吾人認為種子層與障 礙層及銅金屬化層間之黏接可以達成。 此已知方法之無謂複雜性為其缺點,特別關於控制氮大 鲁 氣之需求以提供分級種子層。 發明内容 因此,本發明之第一個目的為提供一如上所述之方法, 其中不而控制氮大氣,並可提供適當之種子層與障礙層及 銅金屬化層之黏接。 本發明第二個目的為提供一如開頭段落所述之電子裝置 ’其中在障礙層與銅金屬化間與有一適當黏接。 第一個目的之達成係因為銅金屬化形成前,種子層被加 熱以釋放氮含量以構成障礙層之一部分將種子層與基板分 隔0 第二個目的之達成係因為障礙層為在介面區域之氮甚豐 富,而導致經介面之氮擴散。 種子層之加熱優異的使含氮之銅分解,因而產生面電阻 之降低及所需之氮釋放。釋放之氮有效氮化基板下之區域 ,因而使障礙區域作為阻止銅種子層之擴散,亦阻止以後 沉積之銅金屬化層擴散至基板。此一在障礙層功能上之優
I 1295071 .. (3) 發明銳明績賈 異改進可與已在原位之銅種子層有效達成。因此,所需之 銅種子層黏接至半導體本體已在下面區域之氮化前達成, 其所以需要係為提供一有效障礙層。 本舍明方法中’種子層係在銅金屬化層施加前加熱。如 加熱係在以後實施,其將無效。銅金屬化層係由電鍍方式 κ施’之後以化學機械法拋光。如加熱在電鐘後實施,加 熱將使銅金屬化層加熱。此舉將導致再度晶體化,並可能 使銅金屬化層斷裂。如加熱係以後施加,氮之擴散無法有 效實施。 本發明之方法亦可在電子裝置製造時使用二次或多次。 銅金屬化對加熱之敏感性在銅金屬化之硫經拋光消除後, 將不致過高而成為缺點。因此可提供一第一銅金屬化,包 括加熱步驟以實施氮擴散,之後提供第二銅金屬化,包括 另一加熱步驟以實施第二銅金屬化之種子層之氮擴散。 雖然種子層沉積後直接貫施加熱步驟較佳以獲得地擴散 至障礙層中,此擴散亦可由其他方式獲得,如升高之壓力 ’及Katalysator之存在等。 由於下面基板之擴散及隨後之氮化物豐富,逐漸改變氮 含量之區域將在障礙層於銅金屬化層間之介面發展出來。 結果,障礙層與銅金屬化間之黏接將甚適合。種子層與銅 金屬化間之黏接由於氮擴散離開銅種子層亦為適當。此黏 接可選擇銅種子層中之氮含量而最佳。 曰本專利號碼JP07090546揭示具有基板上之銅金屬化之 半導體裝置,其係由利用銅及含氮之氣體潑濺一目標而獲 1295071
發明銳麵頁 得。此舉導致一含氮0.2-17%之銅金屬化。但,無徵候顯示 一 曾有本發明之加熱步驟,以使銅金屬化中之氮擴散而離開 · 。結果,銅金屬化可能有強氧化電阻,而未備有降低之電 阻如本銅金屬化一樣。 在一優異之方法中,一障礙層,釋放之氮構成其一部分 ,在銅種子層沉積前沉積。利用此方法,另一障礙層可由 任何可供氮化之適當材料形成,或已包含氮作為以後之氮 豐备化。P早礙層較佳包含氮化鈦或氮化叙。障礙層可包含 _ 具不同氮含量之多數個子層。優異之障礙層為鈕,氮化鈕 及組之堆疊其最後者在加熱步驟時加以氮化。 含氮大氣中可為任何含有氮之氣體,如n2, N2h2,NH2 ’ NH3 ’ NO,其中可添加惰性氣體。較佳的含氮大氣為低 重量氣體,其具有每莫耳2〇克或更低之平均莫耳質量。吾 人發現’透過利用此低重量氣體,含氮層之覆蓋是足夠的 。此種氣體可包括,氮源之後的Ne,He,H2,CH4。氬含 量較少之氬與氮混合氣亦可使用,如8〇%體積之N2及2〇%體 積之Ar的混合氣體。本發明方法之另一版本中,含氮大氣 ® 為包含氮源A之大氣。發現使用純氮氣可有良好結果。此 一良好結果亦可自另一含氮大氣中獲得,包括沉積一含氮 15_25%之種子層,特別是約20%。最佳為使用氮及氖混合 氣。由於氖之低莫耳質量,基板之覆蓋將甚優異。 在另一版式中,銅種子層包含至少二個子層,僅其中之 一在含氮大氣中形成。其優點在於僅銅種子層之一部分或 一子層需在含氮大氣中形成。其亦提供隨後結構與處理步 1295〇71
雜之彈性。 實施方式 吾人瞭解,本發明之電子裝置可為一半導體裝置。但電 子裝置可為電容器及電感器之被動網路。其他裝置已為精 於此技藝人士所知,通常為薄膜裝置包含複數個在基板上 之層,均在本發明之範疇中。本發明所關於之銅金屬化程 序通常包含在半導體本體上沉積一障礙薄膜,及隨後之銅 種子層潑濺沉積。在此實施例中,銅種子層之沉積隨後為 銅金屬化層之電子化學沉積。 任何精於此技藝人士當瞭解,此申請内容中‘基板,一詞 係指任何層或各層之堆疊,障礙層及/或種子層即沉積在 該層上。其特別包括一半導體基板,其中限定複數個半導 體元件,該元件可由一或多個絕緣及互聯層所蓋住。應瞭 解’基板不需為平面表面。反之,其可為有圖案之絕緣層 ,該層以顆粒花紋或雙顆粒花紋結構之銅金屬化沉積後形 成。 根據本發明,至少部分銅種子層在較佳為純氮大氣下沉 積’雖然,混合氣如80%之Ns及20%之Ar混合氣,或乂及 He之混合氣體可提供低重量之工作氣體。以此方式,以薄 膜中約有20%之氮沉積含氮之銅薄膜。此薄膜然後有利地 在’例如,溫度150-300°C之範圍内分解;此舉導致電阻之 降低10個因數,重要的是釋放氮氣。此氮氣之釋放可氮化 下面之障礙薄膜及阻止銅擴散進入半導體本體。此種子層 可優異的用作被動網路之矽基板上之第一層,如 -10- 1295071 ⑹ 發明酴明鑛貫 WO-A01/61847專利所揭示。 應瞭解,本發明可優異的加在任何適當之可形成氮化物 之金屬/合金薄膜或加在現有之氮薄膜,其可在氮中被豐富 。例如,此種薄膜包括鈦或鈕薄膜或氮化物。障礙對銅擴 散之特性在原地形成之簡單性及已存在之下面銅種子層方 面特別優異。 該一般特性如參考圖1A及1B說明。此圖為Rutherfore反 向散射光譜圖’其中之正常產量γ為以Me V之反射能量E之 函數。該光譜圖係在一層上提供具有2 MeV之一束He而獲 得。反向散射能量為層中原子之原子重量之量渡。正常化 產量Y之定義為每單位所加之He返回之He數目,該數目與 特定原子有關。圖中之實驗結果以實線表示,虛線表示模 擬結果。 圖1A及1B係為種子層所獲得。圖1A顯示種子層之光譜, 其獲得係在加熱前在含氮大氣中潑濺所得。圖1B_示種子 層加熱後所得之光譜。圖1A與1B比較可知,銅種子層中之 氮含量已大幅降低。此一降低之分析導致一結論,即此特 例中,約20Xl〇15Si3N4/cm2之量將出現在銅矽介面。可知 圖中亦存在碳及氧。相信氧係產生自銅氧化為Cu〇,及碳 則自來He束中。 圖2顯示以在一矽基板上之15〇 之純銅層與3〇 nm含氮 銅所作之實驗結果。此圖中,正化表面電阻設定為火爐溫 度之函數,帶層之基板即在爐中加熱。在實驗開始之1處設 疋表面電阻,純銅表現表面電阻之增加,因其已擴散至石夕 1295071 ⑺ 基板但含氮薄膜展現與釋放氮有關之表面電阻之降低。 優異地,發現銅薄膜切基板上甚衫直到火爐溫度達 500 c士為止’此一結果係來自矽之氮化,矽作為鋼之擴散障 礙。結果’表面電阻在冷卻後保持甚低。
圖3純鋼層及10 nm之鈦在矽上之含氮鋼之實驗曲線。曲 線中,正常化表面電阻以火爐溫度為函數而繪出。銅之表 面電阻隨溫度因為銅及鈦之擴散而增加,而含氮銅薄膜首 先展現表面電阻之降低,隨後展現表面電阻之穩定直到溫 度550〇C為止。因此可知有氮存在時可優異的阻止銅-鈦間 擴散。 圖4顯示本發明半導體裝置之實施例。一基板1〇〇包括複 數個半導體元件如場效電晶體或雙極電晶體,由一未示出 之絕源層所蓋住。該絕源層以光致蝕刻作成圖案,隨後加 以敍刻以限定溝道。之後,TaN障礙層121利用化學蒸氣沉 積法沉積(為一 5 nm Ta,1 5 nm TaN及5 nm Ta之堆疊)。之 後以200 nm厚含銅之種子層122沉積。第一 15 nm係經由N2 大氣下潑濺獲得,其次之185 nm係在Ar大氣下潑濺穫得。 在加熱300QC 30分鐘後,銅金屬化層101由電鍍銅而生長, 隨後以化學機械方式拋光。之後,沉積另一障礙層114。之 後,另一銅金屬化層102利用熟知之顆粒圖案技術提供。絕 緣層106,107之圖案提供後,由一硬屏罩108隔開一天,一 障礙層123即可提供。種子層124潑濺其上並加熱以使氮擴 散進入障礙層123,該層已成為氮豐富化。隨後,銅金屬化 層102以電鍍生長。 -12- 1295071
’其提供半導體本體上之鋼金屬化,
導體本體分隔。 本發明提供一方法, 方法包括在含氮之大翕 圖式簡單說明 本發明以下將以舉例及參考所附圖式詳細說明,其中: 圖1A顯示在加熱步驟前在矽上形持之含氮薄膜之rbs光 譜曲線; 圖1 B顯示加熱後圖1A之銅薄膜之RBS光譜曲線; 圖2顯示代表銅層及在矽上含氮銅層之表面電阻曲線; 圖3顯示純銅及含氮銅在10 nm之鈦上之表面電阻曲線; 及 圖4顯示本發明電子裝置之一例。 圖式代表符號說明 100 基板 101 銅金屬化層 102 銅金屬化層 106 絕源層 107 絕源層 108 硬屏罩 114 障礙層 121 障礙層 122 種子層 -13- 1295071 (9) 發明說明鑛頁 123 障礙層 124 種子層
-14-

Claims (1)

  1. t 1295071 第91136510號專利申請案中請專利範圍修正本96 〇7 16 拾、申請專利範圍 1· 一種製造備有一銅金屬化於基板上之電子裝置的方法 ,其中該銅金屬化包括一種子層及一銅金屬化層,該方 法包括下列步驟: -在含氮大氣下沉積銅以便形成一含氮銅種子層; 將該種子層加熱以便釋放氮來形成障礙層之一部分 ’而將該種子層自基板分隔,隨後 -在該種子層上施加銅金屬化層。 2 ·如申明專利範圍第1項之方法,其中所釋放氮而形成之 邛为的卩羊礙層係在該銅種子層沉積之前沉積。 3·如申請專利範圍第1或2項之方法,其中該種子層加熱至 150°C以上。 4·如申請專利範圍第3項之方法,其中該種子層加熱至一 低於500°C的溫度。 5·如申请專利範圍第丨項之方法,其中該含氮大氣係包含 Ns作為氮源之大氣。 6·如申研專利範圍第1項之方法,其中該銅種子層包含至 少二子層,僅一子層係在含氮大氣中形成。 7.如申請專利範圍第!項之方法,其中該氮化物障礙層包 含氮化鈦或氮化鈕。 如申4專利範圍第丨項之方法,其中該障礙層係由可形 成一氮化物之任何適當的金属或可由含氮銅層釋放氮 後加以豐富化的一氮化物材料所形成。 >·-種備有-基板之電子農置,纟中基板上存在有包含一 V 1295071 金屬氮化物及一銅金屬化之隆 ^ ^ I礙層堆疊,該障礙層及該 銅金屬化有一共同介面,其特 ^ ^ 、将徵為該障礙層在介面區域 為氣豆畐化,係由於氮擴散通過該介面。 10. 如申请專利範圍第9項之電子裝置,其特徵為其可自具 有與該介面相鄰之銅種子層的銅金屬化所獲得,該銅種 子層在擴散前包含15%至25%原子之氮。 参 1295071
    (二)、本代表圖之元件代表符號簡單說明:
    柒^本案若有、化學,式、時”:讀揭#:編龜麵義義1犯事:式 賴__|議__|__襲^^^
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