TWI285954B - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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TWI285954B
TWI285954B TW094137585A TW94137585A TWI285954B TW I285954 B TWI285954 B TW I285954B TW 094137585 A TW094137585 A TW 094137585A TW 94137585 A TW94137585 A TW 94137585A TW I285954 B TWI285954 B TW I285954B
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source
layer
drain
depth
substrate
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TW094137585A
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TW200620664A (en
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Hung-Wei Chen
Tang-Xuan Zhong
Shui-Ming Cheng
Sheng-Da Liu
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Taiwan Semiconductor Mfg
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    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Thin Film Transistor (AREA)

Description

1285954 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體之製造技術，特別是有關於一種減少浮體 【先前技術】 絕緣層上覆矽（silicon on insulator, SOI)乃未來積體電路世代所選用的 基底。典型的SOI係由埋有-絕緣層的德底所構成，其中半導體裝置係 建立於絕緣層上的補中。由於SOI可減少寄生電容以及加強裝置之絕緣 能力，故能改善其效能。 然而’使用SOI會引發浮體效應。為了延長時間週期，電荷存在於負 晶體本體而導致起始籠的題。有許多的方法可用來減少浮體效應，έ 括錯（Ge)祕/祕植人、氬植人、高傾滅人㈤。implant)以及使月 (bipolar embedded source structure, BESS) 〇 , ^bess , „ 電/ = 37 ’例如_合金，有助於減少存在於電晶體撕^ 電何。因{賈電帶的偏移而帶有 、^ ^ ^ ♦锻甲白、 體。鍺化義極她為孰f上广二二洞可更容祕流出電晶體本 ^ ^ P-FB1 極贿細術物自等ET ° ，酬錯化矽源 有上少浮體效應之半導體裝置製造方法，其不^ 【發明内容】 有鑑於此， 本發明之目& 6在於提供一種半導體裝置及其製造方法， 其
0503-A30984TWF 1285954 藉由在不同的裝置中形成有深淺落差的源極/汲極層，以減少浮體效應。 根據上述目的，本發明提供一種半導體裝置，其包括：一基底:一第 -裝置及-第二裝置。第-裳置位於基底上，其包括—源極層及—沒極層， 各自位於基底中並延伸至-第—深度。第二裝置位於基底上，其包括一源 極層及-汲極層’各自位於基底中並延伸至—第二深度。其中第二深度不 同於第一深度。 又根據上述目的，本發明提供一種半導體裝置，包括：一基底、至少 - PMOS錢及至少-nm〇s裝置。PM〇s裝置位於基底上，其包括陷入 的源極層及汲極層，各自位於基底中並延輕一第一深度。職〇3裝置位 於基底上’其包括陷入的源極層及汲極層，各自位於基底中並延輕一第 二深度。其中第二深度大於第一深度。 又根據上述目的，本發明提供—種半導職置之製造方法。提供一基 底’其上具有m極堆疊結構及―第二閘極堆疊結構。铜基底，以 在其中形成源極及祕凹陷區，其具有—第1度且鄰近於第—及第二閑 極堆疊結構。再次_鄰近於第二祕堆疊結構之源極及雜極凹陷區， 使其延伸至一第二深度，其中第二深度大於第一深度。在鄰近於第一及第 二閘極堆疊結構之源極及汲極凹陷區製作源極及汲極，以形成一第一裝置 及一第二裝置。 、 為讓本發明之上述目的、特徵和優點能更明顯易懂，下文特舉較佳實 施例，並配合所附圖式，作詳細說明如下： 土只 【實施方式】 以下配合第la及lb圖說明減少浮體效應之半導體裝置製造方法忉。 睛參照第la及2圖，首先進形方法1〇之步驟1〇〇，在一基底1〇6上掣 作複數閘極堆疊結構皿及腦。閘極堆疊結構1〇2及猶可藉由習知的^ 法形成之。閘極堆疊結構搬包括一硬式罩幕驗、一閘極電極⑺此、閘
0503-A30984TWF 6 Γ285954 極介電層102c。在一實施例中，閘極堆疊結構1〇2係位於基底1〇6的pM〇s 區106a。閘極堆疊結構104包括一硬式罩幕1〇4a、一閘極電極1〇仙、閘極 介電層104c。在一實施例中，閘極堆疊結構1〇4係位於基底1〇6的應〇;§ 區1061^在一實施例中，基底1〇6包括一絕緣層1〇6c，其可藉由s〇i技術 所开癌之，例如佈植隔離石夕晶（separati〇n by implanted siHc〇n，欣）。 在一貝施例中’複數淺溝槽隔離（shaii〇w trench is〇iati〇n，sti)結構⑽a、 108b及108c係鄭近於閑極堆疊結構1〇2及1〇4及/或位於其間。閑極堆疊 結構102及104可包括氧化石夕、氮化石夕、高介墊常數⑴材料或其組合。 硬式罩幕職及腕可包含氮化梦、碳化碎、二氧化喊其他適合的材料。 請參照第la及3圖，進行方法1〇之步驟2〇〇，在閑極堆疊結構皿及 104、基底106及淺溝槽隔離結構施、麵及驗上沉積四乙基石夕酸鹽 (TE0S)層202。接著在TE0S層202上沉積氮化矽（SiN)層2〇4。此處， 可藉由習知方法沉積TEOS層202與氮化石夕層2〇4。 請參照第la及4圖，進行方法10之步驟搬，藉由非等向性回钱刻第 3 ® 204 .1〇2 (^} 間隙壁302a。藉由非等向性回侧第3圖所示之氮化石夕層2〇4，以在鄰近 閘極堆疊結構104處形成辅助間隙壁3〇4a。 〜 請夢照第la及5圖’進行方法10之步驟彻，钕刻基底觸表面至_ 深度A，以在鄰近閘極堆疊結構搬處形成凹陷區術&及娜。在一^ 例中，钕刻而成的凹陷區402a位於淺溝槽隔離驗與輔助間隙壁3〇二 間補而成的凹陷區術W立於淺溝槽隔離働與輔助間隙壁施 4#構1G4處形成凹陷區刪&及娜。s -實施射，侧而區她位，藉_麵與伽間隙璧 徽之間，侧而成的凹陷區404b位於淺溝槽隔離祕與辅助間隙壁鳥 請參照第la及6圖， 進行方法1G之步驟，，在間極堆疊結構102上
0503-A30984TWF 1285954 形成-光阻圖案層502。在-實施例中，光阻圖案化可藉由習知方法形成 之’其包括了光阻塗佈、軟烤、光罩對準、曝光、顯影及硬烤等步驟。在 -貫施例中’光阻圖案層502位於淺溝槽隔離观a與丨鳴之間且位於 PMOS區l〇6a及閘極堆疊結構1〇2上。 請參照第la、7及8圖，進行方法10之步驟_，再次钕刻第5圖中 鄰近於問極堆疊結構1〇4的凹陷區40如及4〇4b至一深度B，以在鄰近於間 極堆$結構104處形成凹陷區602a及602b。凹陷區602a及602b的深度B 大於凹|^區4〇2a及4〇2b的深度A。舉例而言，凹陷區4伽及彳咖的深度 A約在50至1000埃（ A)，602a及602b的深度B約在100至1500埃。 接著，在步驟700中去除光阻圖案層205 ,以露出閘極堆疊結構1〇2以及 PMOS 區 l〇6a 〇 請參照第la及9圖，進行方法1〇之步驟8〇〇,藉由在閘極堆疊結構 102的兩相對側製作源極/没極層8〇仏及8〇2b，以構成裝置8〇2 ^在一實施 例中，源極/；：及極層802a係藉由在第8圖的凹陷區4〇2a中形成石夕鍺合金層 802aa以及在其上开〉成石夕上盍層8〇2ab而構成之。在一實施例中，源極/沒極 層8〇2b係藉由在第δ圖的凹陷區402b中形成矽鍺合金層802ba以及在其 上形成矽上蓋層802bb而構成之。在一實施例中，裝置8〇2包括閘極堆疊 結構102、源極/；;及極層8〇2a及8〇2b以及基底106之PM〇s區1〇6a。裝置 804亦藉由在閘極堆疊結構1〇4的兩相對側製作源極級極層8〇如及8⑽ 而構成之。在一實施例中，源極/汲極層8〇乜係藉由在第8圖的凹陷區繼： 中形成發錯合金層8〇4aa以及在其上形成矽上蓋層8〇4ab而構成之。在一實 施例中’源極/沒極層804b係藉由在第8圖的凹陷區602b中形成矽鍺合金 層804ba以及在其上形成矽上蓋層804bb而構成之。在一實施例中，裝置 804包括閉極堆疊結構1〇4、源極/沒極層8〇如及8_以及基底1〇6之應〇s 區1〇6b。展一實施例中，矽鍺合金層8〇2aa、，ba、_aa及8〇伽1可藉 由每擇性蟲晶成長（selective epitaxial growth, SEG)法形成之，其包括使用 0503-A30984TWF . Q 、 1285954 鹽酸（HC1)以及甲娜（GeHO，其他的參數如下··溫度在勸。⑶9⑻ °C的範圍；HC1氣體流量在15至2000 sccm的範圍；GeH4氣體流量在 至200 _的範圍；壓力在10至250 torr的範圍。在—實施例中，石夕上签 層8〇2ab、802bb、80灿及80杨亦可藉由SEG法形成之，其包括使用肥 以及二氯魏（di—，DCS)，其他的參數如下：溫产在·。c到 篇。C的範圍；HC1氣體流量在15至2〇〇_的範圍；^氣體流量在 10至300 seem的範菌；壓力在10至25〇於汀的範圍。 請參照第la及1〇圖’進行方法10之步驟着，分別去除第4圖中鄰 近間極堆疊結構搬的輔助間隙壁施、第4圖中鄰近閘極堆疊結構刚 的輔助間隙壁綱a以及閘極堆疊結構1〇2及谢上的硬式撤 触。在-實施例中，辅助間隙壁施及純以及硬式罩幕驗及购 可藉由磷酸溶液去除之。 、請參照第以及η圖，進行方法10之步驟1〇〇〇，在裝置㈣上形成一 光阻圖案層1002。在一f施柄φ，日同杳^ 隹中，先阻圖案層職位於淺溝槽隔離結掮 l〇8a及l〇8b之間，且位於裝置8〇2上方。 月第la及12圖’知*方法1()之步驟11()()，在裝置姻的源極/ 没極層中植入一淺摻雜汲極（lightd〇phgdr血）職，且在裝置咖 觸祕愤人_·驗極聰。在—實施财，植入於裝 f t1〇4 ^ 止於淺溝槽隔離結構l〇8b。在一每# 由 , A ^ ^ 在声、％例中，楂入於裝置804的源極/汲極層 108 芬c。在-貫施例中’摻雜類型可為η型，例如用於觀〇s區屬的ρ (coimplt Ρ型’例如用於PM〇S區1〇6a的Β、即2、或是B_F共植 位於壯罢 > 及13圖’進行方法10之步驟1200’去除第11及12圖中 衣置2上的光阻圖案層驗，且在裝置804上形成一光圖案層跡
0503-A30984TWF Ώ85954 在-實施例中，光阻圖案層位於淺溝槽隔離結構嶋及隱之間， 且位於裝置804上方。 請麥照第lb、14及15圖’進行方法1()之步驟測，在裝置繼的源 極/及極層黯中植入一淺摻雜汲極13Q2a，且在裝置8Q2的源極級極層 _中植人-淺摻雜汲極屬。在一實施例中，植入於裝置觀的細 雜層802a中的淺摻雜汲極職始於閘極堆疊結構搬而止於淺溝槽隔 p構她。在一實施例中，植入於裝置8〇2的源極級極層雛中的淺 4雜維1302b始於閘極堆疊結構撤而止於淺溝槽隔離結構腿。接著， 在步驟1400中去除裝置_上的光阻圖案層1202。 、”請參照第ib及16圖，進行方法1〇之步驟·，在裝置搬及_上 /几積二膜=502。在-實施例中，膜層15〇2可包括一勘s層及一汹層。 月一第，及17圖’進仃方法10之步驟1600，侧第16圖的膜層 牛:’以在鄰近於裝置802巾的閘極堆4結構1〇2處形成間隙壁膽且在 钟近於裝置804中的閘極堆疊結構刚處形成間隙壁應。 請參照第lb及18圖，土隹;^古、土 1Λ 止 I仃方法10之步驟1700，在裝置802上形成- ==服。在—實施辦，光_細取於淺溝槽隔觀 a及108b之間且位於裝置8〇2上。 #請參照第lb、19及20圖，進行方法1〇之步驟18〇〇，在裝置_刺 極/及極層804a中植入一松啼％ 〜 ’’
Him ，雜18G2a。在—錢例巾，植人於裝置804存 16〇/ d8〇4a中的接雜物18〇2Ε，始於閘極堆疊結構104的間隙驾 入-淺溝槽隔離結構1娜。錄置謝的源極/汲極層難中指 的^嶋。在—實施例中，植人於裝置8G4的源極/祕層獅中 沾麟1802b，始於閘極堆疊結 辟 離結構。接著進行牛驟1〇1 的間隙壁1604，而止於淺溝槽隔 达夫㈣1k 一觸，去雜置搬上料光関案層1702。 明茶知弟lb及21圖‘，谁耔古雀1Λ > t 光阻圖案層·2々之步驟厕，在裝置_上形成一 S _辦’光賴案層獅2餘於淺溝槽隔離結構
0503-A30984TWF 1285954 108b及108c之間且位於裝置8〇4上。 清茶弟 lb、22 及 2τ 岡 圖’進灯方法10之步驟2100，在裝置8〇2的源 極/没極層802a中植入―挟右么仏，1Λ。丄 、、 乡雜物2102a。在一實施例中，植入於裝置802的 源極/及極層嶋中的摻雜物2黯，始於閑極堆疊結構脱的間隙壁 1602 &而止於氏屢槽隔離結構舰。在裝置搬的源極/汲極層難中植 入減物2腿。在-實施例中’植入於裝置搬的源極/沒極層_中 的摻雜物2102b ’始於閑極堆疊結構1〇2的間隙壁·，而止於淺溝槽隔 離結構108b。接著進行步驟綱，去除裝置8〇4上方的光阻圖案層雇。 請參照第㈣24圖，進行方法1〇之步驟測，在裝置8〇2中形成石夕 化物層2302a、2032b及2302c，其中魏物層2施形成於源極/汲極層8〇2a 上，石夕化物層2032b形成於閘極堆疊結構他上，而魏物層纖c形成 於源極練層8()2b上。錢置8G4帽成魏餐2施、綱b及23心 其中矽化物層2304a形成於源極/汲極層_上，石夕化物層2祕形成於間 極堆疊結構104上，而石夕化物層2304c形成於源極級極層8〇4b上。石夕化物 層2302^、2^2b、2302c、2施、2034b及2304c可藉由習知的方法形成之。 請簽照第lb及25圖，進行方法10之步驟24〇〇，在裝置8〇2及8⑽上 沉積-接雕麟止層2402。接職鱗止層繼可藉由習知方法沉積而 成’例如化學氣相沉積（CVD)。接觸蝕刻終止層24〇2包括氮化梦、碳化 矽、二氧化矽、或其他適合的材料或是其組合。 雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任 何熟習此項技藝者，在不脫離本發明之精神和範圍内，當可作更動與潤飾， 因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 0503-A30984TWF 11 1285954 【圖式簡單說明】 方法I程圖圖。Τ θ τ出根據本發明實施例之減少浮體效應之半導體裝置製造 方法_本發明實闕之減少_效應之半 導體裝置製造 之剖^示^圖。恤據本發明實施例之在基底上製作複數閘極堆疊結構 氮化月實施例之在第2圖之閘極堆疊賴^ 示意本發明實施例之侧形成複數輔助間隙物^ =/、，丨霞^2圖之_堆疊結構。. 围，===例，形成複數凹__ 第6圖係緣示出根據本發明實施例之 上形成光阻圖案層之剖面示意圖。 困中"中一閘極堆疊結構 甘+弟7圖係4會示出根據本發明實施例之姓成巴 · 其鄰，第6圖之其中-閑極堆疊結構。 之韻不思圖， 光阻圖案層之剖面本發明貫施例之去除第7圖中間極堆疊結構上的 = 示出根據本發明實施例之藉近於 ’ 結構的凹陷區中形成_源極級極層以作數之:二圖，姆疊 第示出根據本發明實施例之二 壁之剖面示意圖。 图之衣置中的辅助間隙 光：：：，實™•其中，上· 叫鱗μ軸本靖綠她丨㈣卜裝置的馳
0503-A30984TWF 12 ^85954 、♦層中it㈣彳錄&極植人之剖面示雜。 y _心根據本發明實施例之去_ ==:其他裝置上形成光阻圖案層之到面示意圖 弟14圖係緣示出根據本發明實施例 甘 汲極層中進行__極植人之剖面示缝。 射—裝置的祕 案層娜本發明實施例之絲第㈣之裝置上的光阻圖 層之峰縣伽技狀麵15社錢上形成間隙壁 隙壁之剖面示意圖丁。出根據本發明實施例之在第16圖之裝置上形成複數間 光本發明實施例之她7圖之其中—裝置上形成 弟19圖鱗示出根據本發明實施例之在第 沒極層中進行摻雜植人之剖面示意圖。 圖之，、中-褒置之源極/ 案層1W的光阻圖 光阻===^禅咖_¥ W上形成 第2圖係、會不出根據本發明實施例之在第21圖之盆中 及簡中進行摻雜植入之剖面示意圖。丨3之/、中-裳置之源極/ 之23 m形翁化物 第25___她輸⑽W輸職
0503-A30984TWF 13 1285954
刻終止層之剖面示意圖D 【主要元件符號說明】 102、104〜閘極堆疊結構； 102b、l〇4b〜閘極電極； 106〜基底； 106b〜NMOS 區； 102a、104a〜硬式罩幕; 102c、104c〜閘極介電層； 106a〜PMOS 區； 106c〜絕緣層； l〇8a、108b、l〇8c〜淺溝槽隔離結構；
2〇2〜四乙基矽酸鹽（TEOS)層； 204〜氮化矽（SiN)層； 302a、304a〜辅助間隙壁； 402a、402b、404a、404b、602a、602b 〜凹陷區； 502、1002、1202、1702、2002〜光阻圖案層； 802、804〜裝置； 802a、802b、8〇4a、804b〜源極/汲極層； 802aa、802ba、804aa、804ba〜石夕鍺合金層； 802ab、802bb、804ab、804bb〜發上蓋層； 1102a、1102b、1302a、1302b 〜淺摻雜汲極； 1502〜膜層； 1602、1604〜間隙壁； 1802a、1802b、2102a、2102b〜摻雜物； 2302a、2302b、2302c、2304a、2304b、2304c〜石夕化物層· 2402〜接觸蝕刻終止層； θ ’ Α、Β〜深度。 0503-A309B4TWF 14

Claims (1)

  1. Π85954 /及極層’各自位於該基底中並延伸至一第二深度，該第二深度大於該第一 深度。 10.如申請專利範圍第9項所述之半導體裝置，其中該基底包括一絕緣 層。 11·如申請專利範圍第9項所述之半導體裝置，其中該pM〇S裝置之該 第一源極層及該第一汲極層包括鍺化矽（SiGe)。 12·如申請專利範圍第9項所述之半導體裝置，其中該NMOS裝置之該 第二源極層及該第二汲極層包括鍺化石夕（SiGe)。 13. 如申請專利範圍第9項所述之半導體裝置，更包括一接觸蝕刻終止 層，鄰近於該PMOS裝置及該NMOS裝置。 14. 如申請專利範圍第9項所述之半導體裝置，更包括一淺溝槽結構， 鄭近於該PMOS裝置及該裝置。 15. —種半導體裝置之製造方法，包括·· 提i、基底，其上具有一第一閘極堆疊結構及一第二閘極堆疊結構； 姓刻該基底，以在其巾形成雜及祕凹陷區，其具有—第_深度且 鄰近於該第一及該第二閘極堆疊結構； 再蝕刻鄰近於該第二閘極堆疊結構之該源極及該汲極凹陷區，使其延 伸至第_凍度，該第二深度大於該第一深度；以及 在鄰近於該帛及該第二閑極堆疊結構之該源極及該&極凹陷區製作 源極及汲極，以形成一第_裝置及一第二裝置。 I6·如申請專觀’ ^酬述之半導體裝置之製造方法，更包括分別 在該第-及該第二閘極堆疊結構上形成一辅助間隙壁。 ？ ，Π•如申請專利範圍第ls項所述之半導體裝置之製造方法，其中製作該 第一裝置更包括·· 、在W近於該第閘極堆疊結構之該源極及該汲極凹陷區中形成複數源 極/没極層；以及 0503-A30984TWF 16 1285954 摻雜該等源極/汲極層，以形成該第一裝置之該源極及該沒極。 18·如申請專利範圍第15項所述之半導體裝置之製造方法，其中製作該 第二裝置更包括： 在鄰近於該弟二閘極堆疊結構之該源極及該沒極凹陷區中形成複數源 極/>及極層；以及 摻雜該等源極/汲極層，以形成該第二裝置之該源極及該汲極。 19·如申請專利範圍第15項所述之半導體裝置之製造方法，更包括在對 應於該第一及該第二裝置之該源極及該汲極上分別形成一接觸蝕刻終止 層。 20.—種半導體裝置，包括： 一基底，其包括一絕緣層； 一 PMOS装置’位於該基底上，其包括一第一源極層及一第二汲極層， 各自位於該基底中並延伸至一第一深度；以及 一 NMOS裝置，位於該基底上，其包括一第二源極層及一第二汲極層， 各自位於該基底中並延伸至_第二深度，該第二深度大於該第_深度；以 及 、 一接觸蝕刻終止層，鄰近於該PM〇s裝置及該裝置。— 21·—種半導體裝置之製造方法，包括： f'、f底’其上具有一第—閘極堆疊結構及-第二閘極堆疊結才| 二別在轉-及該第二閘縣疊結構上形成—獅_:壁； 藉由該_助間隨與第__及該第二_堆疊結構作為侧罩幕: 刻，基底’ ^在射形成祕及祕_區，其具有—第—深度且鄰3 該弟一及該第二閘極堆疊結構； /料於該第—閘極堆疊結構之該祕及該紐凹陷區 伸至一 fn該第二深度大於該第-深度； k於該第_及該第二閑極堆疊結構之該源極及該沒極凹陷位 0503-A30984TWF 17 Γ285954 成源極/汲極層；以及 摻雜鄰近於該第一閘極堆疊結構之該源極/汲極層，以形成一第一裝置 之源極及没極； 摻雜鄰近於該第二閘極堆疊結構之該源極/汲極層，以形成一第二裝置 之源極及汲極；以及 在對應於該第一及該第二裝置之該源極及該汲極上分別形成一接觸蝕 刻終止層。 0503-A30984TWF 18
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