TWI283069B - Thin film transistor and method for manufacturing of the same - Google Patents

Thin film transistor and method for manufacturing of the same Download PDF

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TWI283069B
TWI283069B TW090113334A TW90113334A TWI283069B TW I283069 B TWI283069 B TW I283069B TW 090113334 A TW090113334 A TW 090113334A TW 90113334 A TW90113334 A TW 90113334A TW I283069 B TWI283069 B TW I283069B
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Taiwan
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film
layer
gate
gate insulating
thin film
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TW090113334A
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Hiroshi Tanabe
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Nippon Electric Co
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current

Abstract

To provide a thin film transistor which can suppress deterioration of transistor characteristics caused by channeling of ions. In a thin film transistor 10 including a crystallized silicon thin film 2 having a source drain region 2a formed on an insulating substrate 1 and a channel region 2b, a gate insulating film 3 formed on the crystallized silicon thin film 2, and a gate electrode 4 formed on the gate insulating film 3, an amorphous layer 5 and a crystalline layer 6 are formed in the gate electrode 4.

Description

12830691283069

五、發明說明（！） [技術領域] (請先閱讀背面之注意事項再填寫本頁) 本發明爲有關一種薄膜電晶體及其製造方法，其係 作爲記憶體、中央處理器（CPU)等的半導體裝置、或顯 示器、感測器、打印設備等功能機器的構成元件所使用 之形成在絕緣體上的薄膜電晶體者。 [背景技術] 以往，例如形成在玻璃或石英等絕緣基板上的，作 爲薄膜電晶體（以下稱TFT)之代表例中，是有氫化非晶 質矽TFT及多結晶矽TFT。 其中，氫化料晶質矽TFT在其製造過程中的最高溫 度爲約300 °C程度，因而其絕緣性基板可用廉價的低軟 化點玻璃基板。又，其移動度也達到lcm2/V · sec程度 的載體移動度。 經濟部智慧財產局員工消費合作社印製 此氫化非晶質矽TFT被作爲主動矩陣型液晶顯示器 (以下稱爲主動矩陣型LCD)中的、各象素的開關電晶體 之用，而由配置在畫面周邊的驅動積體電路（積體電路 (1C)或形成在單結晶基板上的大型積體電路（LSI)等）所 驅動。在此場合中，氫化非晶質TFT是配置在每一個 象素上。 由此，此主動矩陣型LCD如與從周邊驅動積體電路 傳送液晶驅用電氣信號的被動型液晶顯示器（以下稱被 動型LCD)相比時，其串音已被減低而具可獲得良好圖 像品質之特徵。 其次，多結晶矽TFT是例如使用石英基板作爲其絕 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 1283069 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（2 ) 緣性基板’且，使用和L S I的製造過程同等的1 〇 〇 〇 °c 程度之高溫處理，就可獲得載體移動度爲30〜10〇cm2/V • s e c的性能。 在此，對於將此多結晶矽TFT應用在液晶顯示器上 的情形等予以說明。此多結晶矽TFT是如上述的，由 和LSI製造過程同等的約100(TC程度之高溫處理所形 成且可實現高的載體移動度。由此，可在同一絕緣性基 板上，同時的形成驅動各象素的多結晶矽TFT和周邊 驅動電路部（例如LSI)，其與上述主動矩陣型LCD相比 時，可容易的使液晶顯示器小型化。 具體上，在主動矩陣型LCD中，基板與周邊驅動積 體電路之間的連接是使用卷帶自動接合（TAB)或打線接 合（Wire Bonding)法。 因而，主動矩陣型LCD會隨著要其小型化或高解析 度化，其基板與周邊驅動積體電路之間的連接節距會狹 小化，難於解決這些的連接。相對的，在於使用多結晶 矽TFT的液晶顯示器中，如上述的可在於同一絕緣基 板上，同時的形成多結晶矽TFT和周邊驅動電路部， 因而，其小型化較爲容易。 即，此多結晶矽TFT是有助於在液晶顯示器製造過 程中的製造成本的減低及小型化。例如使用這種多結晶 矽TFT的液晶顯示器中，是有一種用在液晶投影機的 液晶光閥。此液晶光閥中，已被實現相當於解析度 1 000dpi(點/英尺）的驅動電路一體型顯示元件。 -4- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） &—』--------裝--------訂—^------- (請先閱讀背面之注意事項再填寫本頁) 1283069 A7 B7 五、發明說明（3 ) (請先閱讀背面之注意事項再填寫本頁) 然而，這些多結晶矽TFT是如上述的，在約1 000 °C 程度的高溫處理所製造者，因而，不能使用在於主動矩 陣型LCD中可使用的廉價的低軟化點玻璃基板，而不 得不使用高價的石英基板。即，要用廉價的低軟化點玻 璃和多結晶矽TFT以形成液晶顯示器是有困難之問題 。因此，爲了要使用低軟化點玻璃基板，必須將多結晶 矽TFT在製造過程中之溫度降低，而其降低溫度手段 中已被硏究開發的是應用準分子雷射結晶化技術的多結 晶矽膜之低溫形成技術。 又，要形成閘極之際，例如用濺射鋁膜作爲該閘極 ，以使其處理溫度溫度的低溫化。雖以如此使低軟化點 基板的使用成爲可能，但在此產生新的問題。在具體上 ，隨著製造過程整體上的處理溫度低溫化之進展，對閘 極絕緣膜的熱處理溫度也必須降低，閘極絕緣膜的品質 會降低。由此，閘極絕緣膜與閘極（A1)會容氣產生反應 ，且，隨著TFT元件尺寸的微細化、低電壓驅動化， 也在謀求閘極絕緣膜的薄膜化，因而，閘極絕緣膜的可 靠性會有大幅降低之問題。 經濟部智慧財產局員工消費合作社印製 在此，可使此問題解決的是有如特開平1 1 -3 07777號 : 公報所公佈的薄膜電晶體。此薄膜電晶體是具備形成在 絕緣基板上的持有源極·汲極領域之結晶化矽薄膜；介 以閘極絕緣膜，形成在該結晶化矽薄膜的通道領域上方 之微結晶矽薄膜；和，用濺射法形成在該微結晶矽薄膜 上閘極金屬者。在此場合中，源極•汲極領域是以閘極 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 1283069 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（4 ) 爲遮罩，用離子注入法或離子摻雜法，以自調合的形成 者。又，微結晶矽薄膜是用電漿心學氣相沈積（以下稱 CVD)法所形成。如此，使用這種可在於3 00t程度的 低成膜溫度就可獲得低電阻的磷摻雜層之由電漿CVD 法所形成的微結晶矽薄膜，就可解決上述問題。 然而在閘極的下層是有微結晶矽薄膜，即，是使用 結晶性材料，因而，於形成源極•汲極之際，所注入或 引進的離子會引起通道作用，此離子會有到達更深之虞 。在具體上是離子會穿透閘極而到達閘極絕緣膜中或結 晶化矽薄膜中，致使電晶體特性劣化之虞的問題之存在。 本發明的目的是在於提供一種可改善往例所持有的 問題，可抑制離子的通道作用所引起的電晶體特性劣化 之薄膜電晶體者。 [發明之啓示] 本發明的薄膜電晶體是由具備：持有形成在基板上 的源極•汲極領域及通道領域之結晶化矽膜；形成在該 結晶化矽膜上的閘極絕緣膜；和，形成在該絕緣膜上的 閘極之構造所構成。在此，閘極是設有非晶質層和結晶 質層者。 又，本發明的薄膜電晶體之製造方法是在於包含： 在基板上形成源極·汲極領域用的結晶化矽膜的工程； 在該結晶化砂層上形成閘極絕緣膜的工程；及在該閘極 絕緣膜上形成閘極的工程之薄膜電晶體之製造方法中， 在上述閘極形成工程中係包含形成作爲閘極構成要素的 -6- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） « L---r-------裝--------訂---：------- C請先閱讀背面之注意事項再填寫本頁} 1283069 A7 B7 五、發明說明（5 ) 非晶質層及結晶質層之工程者。 (請先閱讀背面之注意事項再填寫本頁) 以如此形成薄膜電晶體時，如要用離子注入法或離 子摻雜法，且，以閘極作爲遮罩，自調合的形成源極· 汲極領域之時，可抑制在往例中所擔心的，由於所注入 或引進的離子之通道作用所引起弊病之事。 又，也可將非晶質層設在閘極絕緣膜表面上，並在 該非晶質層上設置結晶質層。在此，對閘極詳述時，非 晶質層可由非晶質材料來形成，且結晶質層可由結晶質 材料來形成。其製造方法是例如要在閘極絕緣膜上形成 非晶質層之場合中’是在上述非晶質層的形成工程中， 在閘極絕緣膜上’層疊非晶質材料，然後，在上述結晶 質層的形成工程中，在該非晶質材料上，層疊結晶質材 料。在此場合中’非晶質材料及結晶質材料是可使用摻 雜磷、砷、或硼等雜質的砂薄膜。由此，如上述的，可 抑制由於離子的通道作用所引起的弊病。 、 經濟部智慧財產局員工消費合作社印製 又’也可用非晶質材料形成非晶質層後，在該非晶 質材料上照射雷射光，以使非晶質材料表面成爲結晶質 層，而形成爲閘極者。依此形成閘極，也可抑制由於離 子的通道作用所引起的弊病。 又，也可形成矽薄膜以作爲閘極的構成要素，而此 矽薄膜是具備非晶質層及結晶質層者。其製造方法是在 矽薄膜的形成工程中，控制該矽薄膜的成膜時間。例如 要在閘極絕緣膜上形成砂薄膜的場合中，控制其成膜時 間’以使其與閘極絕緣膜的交界面近旁成爲非晶質層， 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 1283069V. INSTRUCTIONS (!) [Technical Fields] (Please read the precautions on the back and fill out this page.) The present invention relates to a thin film transistor and a method of manufacturing the same, which is used as a memory, a central processing unit (CPU), or the like. A thin film transistor formed on an insulator used for a constituent element of a functional device such as a display device, a sensor, or a printing device. [Background Art] Conventionally, for example, a thin film transistor (hereinafter referred to as TFT) which is formed on an insulating substrate such as glass or quartz is a hydrogenated amorphous germanium TFT and a polycrystalline germanium TFT. Among them, the maximum temperature of the hydrogenated crystalline germanium TFT in the manufacturing process is about 300 ° C, so that the insulating substrate can be inexpensively used to lower the soft glass substrate. Further, the degree of mobility also reaches the carrier mobility of about 1 cm 2 /V · sec. The hydrogenated amorphous germanium TFT printed by the Intellectual Property Office of the Intellectual Property Office of the Ministry of Economic Affairs is used as a switching transistor for each pixel in an active matrix type liquid crystal display (hereinafter referred to as an active matrix type LCD), and is configured by A drive integrated circuit (integrated circuit (1C) or a large integrated circuit (LSI) formed on a single crystal substrate) is driven around the screen. In this case, a hydrogenated amorphous TFT is disposed on each of the pixels. Therefore, when the active matrix type LCD is compared with a passive type liquid crystal display (hereinafter referred to as a passive type LCD) that transmits an electric signal for driving a liquid crystal drive from a peripheral driving integrated circuit, the crosstalk is reduced and a good picture is obtained. Like the characteristics of quality. Secondly, the polycrystalline germanium TFT is, for example, using a quartz substrate as its absolute paper size. It is applicable to the China National Standard (CNS) A4 specification (210 X 297 mm). 1283069 Ministry of Economic Affairs Intellectual Property Bureau Staff Consumer Cooperative Printed A7 B7 V. Invention Description (2) The edge substrate 'and the high-temperature treatment of 1 〇〇〇 ° C equivalent to the manufacturing process of LSI can obtain the carrier mobility of 30 to 10 〇 cm 2 /V sec. Here, a case where the polycrystalline germanium TFT is applied to a liquid crystal display or the like will be described. The polycrystalline germanium TFT is formed as described above by a high temperature treatment of about 100 (the degree of TC is the same as that of the LSI manufacturing process and can achieve high carrier mobility. Thus, simultaneous formation can be performed on the same insulating substrate. The polycrystalline germanium TFT for driving each pixel and the peripheral driving circuit portion (for example, LSI) can easily reduce the size of the liquid crystal display when compared with the active matrix LCD. Specifically, in the active matrix type LCD, the substrate The connection with the peripheral drive integrated circuit is the use of tape automatic bonding (TAB) or wire bonding (Wire Bonding) method. Therefore, the active matrix LCD will be miniaturized or highly resolved with its substrate and The connection pitch between the peripheral driving integrated circuits is narrowed, and it is difficult to solve these connections. In contrast, in a liquid crystal display using a polycrystalline germanium TFT, as described above, the same insulating substrate can be formed on the same insulating substrate. The TFT and the peripheral driving circuit portion are relatively easy to be miniaturized. That is, the polycrystalline germanium TFT contributes to a reduction in manufacturing cost in the manufacturing process of the liquid crystal display. Miniaturization. For example, in a liquid crystal display using such a polycrystalline germanium TFT, there is a liquid crystal light valve used in a liquid crystal projector. This liquid crystal light valve has been realized to have a resolution of 1 000 dpi (dot/feet). Drive circuit integrated display component -4- This paper scale applies to China National Standard (CNS) A4 specification (210 X 297 mm) &-』--------Install-------- Order—^------- (Please read the notes on the back and fill out this page) 1283069 A7 B7 V. Inventions (3) (Please read the notes on the back and fill out this page) However, these are many The crystalline germanium TFT is a manufacturer which is treated at a high temperature of about 1 000 °C as described above, and therefore, an inexpensive low-softening point glass substrate which can be used in an active matrix type LCD cannot be used, and expensive quartz must be used. The substrate, that is, the use of inexpensive low-softening point glass and polycrystalline germanium TFT to form a liquid crystal display is difficult. Therefore, in order to use a low-softening point glass substrate, the temperature of the polycrystalline germanium TFT must be in the manufacturing process. Lowered, and its means of lowering temperature has been smashed Developed a low-temperature formation technique for a polycrystalline tantalum film using a pseudo-molecular laser crystallization technique. Further, when a gate is formed, for example, a sputtering aluminum film is used as the gate to lower the temperature of the processing temperature. Although the use of a low-softening point substrate is made possible in this way, a new problem arises here. Specifically, as the processing temperature is lowered as a whole in the manufacturing process, the heat treatment temperature of the gate insulating film must also be When the thickness of the gate insulating film is lowered, the gate insulating film and the gate electrode (A1) react with each other, and as the size of the TFT element is reduced and the voltage is driven low, the gate is also sought. The thin film of the insulating film is formed, and thus the reliability of the gate insulating film is greatly reduced. Printing by the Intellectual Property Office of the Ministry of Economic Affairs, the Consumers' Cooperatives. Here, the problem can be solved by the thin film transistor disclosed in the Gazette No. 1 1 -3 07777: Bulletin. The thin film transistor is a crystallized tantalum film having a source/drain region formed on an insulating substrate; and a microcrystalline germanium film formed over the channel region of the crystallized tantalum film via a gate insulating film; And, a gate metal is formed on the microcrystalline germanium film by sputtering. In this case, the source and bungee fields are applied to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) on the threshold of the paper. 1283069 Ministry of Economic Affairs Intellectual Property Bureau Staff Consumer Cooperative Printed A7 B7 V. Invention Note (4) For the mask, use ion implantation or ion doping to form the self-aligning. Further, the microcrystalline ruthenium film is formed by plasma center vapor deposition (hereinafter referred to as CVD). Thus, the above problem can be solved by using the microcrystalline germanium film formed by the plasma CVD method of the low-resistance phosphorus-doped layer at a low film formation temperature of about 300 00. However, in the lower layer of the gate, there is a microcrystalline ruthenium film, that is, a crystalline material is used. Therefore, at the time of forming the source/drain, the implanted or introduced ions cause channel action, and the ions will reach deeper. After that. Specifically, there is a problem that ions pass through the gate and reach the gate insulating film or crystallize the germanium film, causing deterioration of the transistor characteristics. SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film transistor which can improve the problems of the conventional example and can suppress the deterioration of the characteristics of the transistor caused by the channel action of ions. [Invention of the Invention] The thin film transistor of the present invention comprises: a crystallized tantalum film having a source/drainage field and a channel region formed on a substrate; and a gate insulating film formed on the crystallized tantalum film And the structure of the gate formed on the insulating film. Here, the gate is provided with an amorphous layer and a crystalline layer. Moreover, the method for producing a thin film transistor of the present invention includes: a process of forming a crystallized tantalum film for a source/drain region on a substrate; a process of forming a gate insulating film on the crystallized sand layer; In the method for manufacturing an engineered thin film transistor in which a gate electrode is formed on the gate insulating film, the gate forming process includes forming a -6-sheet material as a gate element for the Chinese National Standard (CNS) A4. Specifications (210 X 297 mm) « L---r-------装--------Book---:------- C Please read the notes on the back first Fill in the page again] 1283069 A7 B7 V. INSTRUCTIONS (5) Engineers of amorphous and crystalline layers. (Please read the precautions on the back and fill out this page.) When forming a thin film transistor, use ion implantation or ion doping, and use a gate as a mask to form a source of self-alignment. In the extreme field, it is possible to suppress the fears caused by the passage of ions injected or introduced in the conventional case. Further, an amorphous layer may be provided on the surface of the gate insulating film, and a crystalline layer may be provided on the amorphous layer. Here, when the gate is described in detail, the amorphous layer may be formed of an amorphous material, and the crystalline layer may be formed of a crystalline material. In the case where the amorphous layer is formed on the gate insulating film, for example, in the formation process of the amorphous layer, an amorphous material is laminated on the gate insulating film, and then, In the formation of the crystalline layer, a crystalline material is laminated on the amorphous material. In this case, the amorphous material and the crystalline material are sand films in which impurities such as phosphorus, arsenic or boron are doped. Thereby, as described above, the disadvantage caused by the action of the passage of ions can be suppressed. , the Ministry of Economic Affairs, the Intellectual Property Bureau, the employee consumption cooperative, printed and 'an amorphous material can also be used to form an amorphous layer, and the amorphous material is irradiated with laser light to make the surface of the amorphous material a crystalline layer. For the gate. By forming a gate in this way, it is also possible to suppress the disadvantage caused by the action of the channel of the ion. Further, a tantalum film may be formed as a constituent element of the gate electrode, and the tantalum film may be an amorphous layer or a crystalline layer. The manufacturing method is to control the film formation time of the tantalum film in the formation process of the tantalum film. For example, in the case where a sand film is formed on the gate insulating film, the film formation time is controlled so that it is adjacent to the interface of the gate insulating film to become an amorphous layer, and the paper scale is applicable to the Chinese National Standard (CNS) A4. Specifications (210 X 297 public) 1283069

經濟部智慧財產局員工消費合作社印製 五、發明說明（6 ) 且隨著此矽薄膜的沈積之進行，變化其結晶性，以使在 非晶質層上成爲結晶質層。此時，結晶質層中的結晶成 分會隨著離開於閘極絕緣膜而增加。以如此形成矽薄膜 時，也可抑制由於離子的通道作用所引起的弊病。 又，在形成矽薄膜後，進行30(TC以上的退火，然後 進行引進氫的處理，由此而可保護的薄膜的表面。 接著’將如上述所形成的矽薄膜製成圖案後，以該 砂薄膜作爲遮罩，在結晶化矽薄膜形成源極•汲極領域 。然後’照射所定照射強度之雷射光。因此，可使矽薄 膜及結晶化砂薄膜低電阻化之同時，也可使源極•汲極 領域活性化。 [實施發明之較佳形態] 參照第1圖，說明本發明的第1實施形態。此第1 圖中的符號1 0是表示薄膜電晶體。 此薄膜電晶體1 0是如第1圖所示的具備：、形成在絕 緣性基板1上的持有源極•汲極領域2a及通道領域2b 之結晶化矽薄膜2 ;形成在該結晶化矽薄膜2上的，例 如由矽氧化膜所構成之閘極絕緣膜3 ;和，形成在該閘 極絕緣膜3上之閘極4。 在此’絕緣性基板1是使用玻璃基板。又，結晶化 矽薄膜2是由非摻雜（無添加雜質）膜所形成，源極•汲 極領域2a是用離子注入法或離子摻雜法，以控制價電 子爲目的的、注入或引進磷、硼或砷等的高濃度雜質所 形成。 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公爱） ,!-------·裝--------訂---------^9 (請先閱讀背面之注意事項再填寫本頁) 1283069 五 '發明説明（7 ) 又，閘極4是具備形成在通道領域2b上方的下層閘 極矽5 (非晶質層），和形成在該下層閘極矽5上的上層 閘極矽（結晶質層）6，及，形成在該上層閘極矽6上的 金屬或金屬矽化物之閘極金屬7。其中，下層閘極矽5 是用預先摻雜磷的非晶質矽（非晶質材料），上層閘極矽 6是用同樣摻雜磷的結晶性矽（結晶性材料）。 如此的，在非晶質材料的閘極絕緣膜3上形成非晶 質材料的下層閘極矽5，因而，在於要形成源極•汲極 領域2a時，可防止如往例中的通道作用，而可抑制電 晶特性的劣化。 在本實施形態中，絕緣性基板1是用玻璃基板者， 但，也可用在玻璃基板上如後述的層疊基板覆蓋膜者， 或在矽基板上形成熱氧化膜者。又，結晶化矽薄膜2也 可用以控制閥値爲目的的、引進磷或硼作爲其低濃度雜 質者。 其次，參照第2圖（a)、（b)說明本發明的第2實施形態 、在此第2圖（a)、（b)中的符號20是表示薄膜電晶體。 此薄膜電晶體20是如第2圖（a)所示的，具備：形成 在絕緣性基板Η上的持有源極、汲極領域1 2a及通道 領域1 2 b之結晶化矽薄膜1 2 ;形成在該結晶化矽薄膜 1 2上的，例如由矽氧化膜所構成之閘極絕緣膜1 3 ;和 ，形成在該閘極絕緣膜1 3上，且在通道領域1 2b上方 之閘極1 4。 又，此閘極1 4是具備：形成在其凹凸部分的層間分 離絕緣膜1 8 ;和’埋沒於形成在該層間分離絕緣膜i 8 -9- 1283069 五、發明説明（8 ) 及閘極絕緣膜1 3的接觸孔1 7之由鋁所構成的，如第 2(a)、（b)圖所示之金屬配線19。由此可使其配線電阻 減低。 在此，閘極14是具備形成在通道領域12b上方的下 層閘極矽（非晶質層）1 5，和，形成在該下層閘極矽1 5 上的上層閘極矽（結晶質層）16。其中，下層閘極矽15 是用預先摻雜磷的非晶質矽（非晶質材料），上層閘極矽 1 6是用同樣摻雜磷的結晶性矽（結晶性材料）。 又，絕緣性基板Π是用和第1實施形態同樣的東西 ，結晶化矽薄膜1 2及源極•汲極領域1 2a是和第1實 施形態同樣的形成之。 如此，是在非晶質材料的閘極絕緣膜1 3上形成非晶 質材料的下層閘極矽1 5，因而和第1實施形態同樣， 要形成源極•汲極領域1 2 a時，可防止如往例中的通道 作用，而可抑制電晶體特性的劣化。 在本實施形態中，金屬配線1 9是用鋁所構成者，但 也可用銅、鎢、鉬、鈦等的金屬，以這些金屬作爲基礎 材料之合金、或多種金屬的層疊體以取代於鋁者。 在此，如在於上述第1及第2實施形態中不形成作 爲上層聞極砂層6、1 6的結晶性砂時，也可獲得和各實 施形態同樣效果。例如對作爲下層閘極矽5、1 5的非晶 質矽照射雷射光，以使非晶質矽表面成爲結晶質層即可。 以如上述各實施形態所例示的、構成薄膜電晶體！ 〇 、20時，是可解決往例之問題，但如採用如下述的構 成時，也可同樣可使問題獲得解決。 -10- 1283069 A7 B7 五、發明說明（9 ) ί請先閱讀背面之注意事項再填寫本頁) 首先，對形成在由非晶質材料所構成的鬧極絕緣膜 上之矽薄膜的膜厚與其電阻率之間的關係加以說明。爲 此，其試樣是用使用平板型的高頻電漿CVD裝置將矽 薄膜形成在玻璃基板（非晶質基板）上者。由此’可獲得 和在閘極絕緣膜上形成的矽薄膜時同等之效果。 以氣體摻雜磷的矽薄膜之形成條件如下。Printed by the Ministry of Economic Affairs, the Intellectual Property Office, and the Consumer Cooperatives. V. Inventive Note (6) and as the deposition of the tantalum film proceeds, its crystallinity is changed to become a crystalline layer on the amorphous layer. At this time, the crystal component in the crystalline layer increases as it leaves the gate insulating film. When the ruthenium film is thus formed, the disadvantage caused by the action of the ion channel can also be suppressed. Further, after the tantalum film is formed, 30 (the annealing of TC or more is performed, and then the treatment of introducing hydrogen is performed to thereby protect the surface of the film. Next, the pattern of the tantalum film formed as described above is patterned. The sand film is used as a mask to form a source and a drain in the crystallized tantalum film. Then, the laser light of the predetermined irradiation intensity is irradiated. Therefore, the tantalum film and the crystallized sand film can be made low-resistance, and the source can be made. In the first embodiment of the present invention, a first embodiment of the present invention will be described with reference to Fig. 1. Reference numeral 10 in the first drawing denotes a thin film transistor. 0 is a crystallized tantalum film 2 having a source/drain region 2a and a channel region 2b formed on the insulating substrate 1 as shown in Fig. 1 and formed on the crystallized tantalum film 2 For example, a gate insulating film 3 composed of a tantalum oxide film; and a gate electrode 4 formed on the gate insulating film 3. Here, the insulating substrate 1 is a glass substrate. Further, the crystallized tantalum film 2 is used. Is formed by a non-doped (no added impurity) film The source/bungee field 2a is formed by ion implantation or ion doping to control or valence electrons, and to inject or introduce high-concentration impurities such as phosphorus, boron or arsenic. (CNS) A4 specifications (21〇X 297 public), !-------·装--------Book---------^9 (Please read the back Note: Please fill in this page again) 1283069 5 'Invention Description (7) Further, the gate 4 is provided with a lower gate electrode 5 (amorphous layer) formed over the channel region 2b, and formed in the lower gate electrode 5 Upper upper gate 矽 (crystal layer) 6, and gate metal 7 of metal or metal lanthanide formed on the upper gate 。6, wherein the lower gate 矽5 is pre-doped with phosphorus An amorphous germanium (amorphous material), the upper gate electrode 6 is a crystalline germanium (crystalline material) doped with phosphorus. Thus, amorphous is formed on the gate insulating film 3 of the amorphous material. The lower gate of the material is 矽5, and therefore, in the case where the source/drain region 2a is to be formed, the channel function as in the conventional example can be prevented, and the deterioration of the electrocrystal characteristic can be suppressed. In the present embodiment, the insulating substrate 1 is a glass substrate. However, it may be used as a laminated substrate coating film to be described later on a glass substrate, or a thermal oxide film may be formed on the germanium substrate. The tantalum film 2 may be used for controlling the valve 、, and phosphorus or boron may be introduced as a low-concentration impurity. Next, the second embodiment of the present invention will be described with reference to FIGS. 2(a) and 2(b). Symbols 20 in (a) and (b) are thin film transistors. The thin film transistor 20 is as shown in Fig. 2(a) and has a source which is formed on the insulating substrate 、. a gated film 1 2a and a channel region 1 2 b of a crystallized tantalum film 1 2; a gate insulating film 13 formed of the tantalum oxide film formed on the crystallized tantalum film 12; The gate insulating film 13 is on the gate and the gate 14 is above the channel region 12b. Further, the gate electrode 14 is provided with: an interlayer insulating film 18 formed on the uneven portion thereof; and 'buried in the interlayer insulating film i 8 -9 - 1283069 5, the invention description (8) and the gate The contact hole 17 of the insulating film 13 is made of aluminum, as shown in the second (a) and (b). This reduces the wiring resistance. Here, the gate electrode 14 is provided with a lower gate electrode (amorphous layer) 15 formed over the channel region 12b, and an upper gate electrode (crystal layer) formed on the lower gate electrode 15b. 16. Among them, the lower gate electrode 15 is made of amorphous germanium (amorphous material) which is previously doped with phosphorus, and the upper gate electrode 16 is a crystalline germanium (crystalline material) which is also doped with phosphorus. In addition, the insulating substrate Π is the same as that of the first embodiment, and the crystallization thin film 1 2 and the source/drain region 1 2a are formed in the same manner as in the first embodiment. In this manner, since the lower gate electrode 15 of the amorphous material is formed on the gate insulating film 13 of the amorphous material, the source/drain region is formed to be 1 2 a as in the first embodiment. It is possible to prevent the channel action as in the conventional example, and to suppress deterioration of the transistor characteristics. In the present embodiment, the metal wiring 19 is made of aluminum. However, a metal such as copper, tungsten, molybdenum or titanium may be used, and an alloy of these metals as a base material or a laminate of a plurality of metals may be used instead of aluminum. By. Here, in the case where the crystal sands of the upper layer of the sand layers 6 and 16 are not formed in the first and second embodiments, the same effects as in the respective embodiments can be obtained. For example, the amorphous germanium which is the lower gate electrode 5, 15 is irradiated with laser light so that the surface of the amorphous germanium becomes a crystalline layer. A thin film transistor is constructed as exemplified in each of the above embodiments! 〇 , 20 o'clock, can solve the problem of the previous example, but if the following configuration is adopted, the problem can be solved as well. -10- 1283069 A7 B7 V. INSTRUCTIONS (9) ίPlease read the precautions on the back side and fill in this page. First, the film thickness of the germanium film formed on the noise insulating film made of amorphous material. Explain the relationship between its resistivity and its resistivity. For this reason, the sample was formed by forming a tantalum film on a glass substrate (amorphous substrate) using a flat type high frequency plasma CVD apparatus. Thereby, the same effect as that of the tantalum film formed on the gate insulating film can be obtained. The formation conditions of the ruthenium film doped with a gas are as follows.

基板溫度 32Q°C 矽烷流量 20sccm 氫流量 lOOOsccm 膦（氫稀釋〇_5%)流量 40sccm 氣體壓力 50Pa 高頻電力密度（連續放電） 128mW/cm2 典型的成膜速度 3.7nm/min 經濟部智慧財產局員工消費合作社印製 基於此形成條件，控制矽薄膜的成膜時間，以作爲 膜厚不同的三種（40.7nm、68.5nm、104.6nm)試樣。然 後，測定各膜厚的薄片電阻，將此薄片電阻換算成電阻 率。其結果（各膜厚與薄片電阻和電阻率的關係）如第3 圖所示。由此第3圖可知，隨著膜厚的增加其電阻率會 降低。此乃暗示著其係在膜厚方向產生電阻率分佈之事。 依據以上的結果進行光譜偏振光分析（e 11 i p s 〇 m e t r y) 測定，用布魯吉曼（Bruggeman)的有效媒質近似 (Effective Medium Approximation)解析在膜厚方向的構 造變化。 此解析是用上述三種試樣。在此，在膜厚40.7nm、 -11- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 1283069 五、發明説明（i〇 ) 68.5nm、及104.6nm的各矽薄膜表面，分別形成膜厚 3.4nm、9.2nm、及12.7nm的表面氧化膜。而對膜厚 40· 7nm試樣的解析結果在第4(a)圖，膜厚68.5 nm試樣 的解析結果在第4(b)圖、膜厚104.6nm試樣的解析，結 果在第4(c)圖所示。這些在測定、解析上的誤差是由導 入空隙成分所調整。 在膜厚40.7nm的矽薄膜中，由第4(a)圖得知，其下 層（玻璃基板側）1 3 · 1 nm的閘極矽層中的非晶質矽成分 爲100%，上層27· 6nm的閘極矽層中的結晶性矽成分 已上升到14%。 其次，在膜厚6 8 · 5 n m的砂薄膜中，由第4 (b)圖得知 ，其下層27· lnm的閘極矽層中未能觀測到結晶性矽成 分，而非晶質矽成分已減少到79%。又，在上層l.4nm 的閘極矽層中的結晶生矽成分已增加到4 9 %。 同樣的，在膜厚104.8nm的矽薄膜中，由第4(c)圖得 知，其下層42· 1 nm的閘極矽層中未能觀測到結晶性矽 成分，而非晶質矽成分已減少到70%。又，在上層 62.5 nm的閘極矽層中，結晶性矽成分已增加到60%。 在此，對膜厚40· 7nm的矽薄膜之解析結果中，其下 層13. lnm閘極矽層是由100°/。非晶質矽成分所構成， 因而，在其他兩種矽薄膜中，也可推測其由100%非晶 質矽成分所構成的層是有1 3 nm程度。例如對膜厚 104.6nm的矽薄膜加以說明時，可想像其下層42.1nm 中的從玻璃基板算起的約13nm的層是由100%的非晶 -12- 1283069 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（11) 質矽成分所構成，其上部約29nm的層是結晶成分逐漸 的增加者。 由此，.控制矽薄膜的成膜時間，就可使其下層形成 爲非晶質層，上層形成爲結晶質層。基於此結果，將本 發明薄膜電晶體的其他實施形態（第3及第4實施形態） 於後述之。 又，用電漿CVD法所形成的，由矽薄膜所構成之閘 極層是如第1及第2實施形態所示的使用閘極金屬（金 屬配線），就可在於像LCD那樣大型裝置中，也可減低 其配線電阻。然而，在於被要求更高的驅動能力、且， 要使閘極絕緣膜的薄膜化或通道長度的微細化之場合中 ，閘極層也被要求更低的電阻。在此場合中，施加600 t〜1 0 00 °C程度的熱處理，就可促進結晶的結晶化，由 此，雖可實現閘極的低電阻化，但如此一來基板就不能 用廉價的低軟化點玻璃（例如在800°C以上就會軟化的 玻璃）。 因此，基於如下的解析結果，將在於被要求更高的 驅動能力，且要使閘極絕緣膜的薄形化或通道長度的微 細化時，也可使用廉價的低軟化點玻璃等之本發明實施 ‘ 形態（第3及第4實施形態）加以說明。 在此是用三種膜厚（45nm、72nm、102nm)的，由砂薄 膜所構成之試樣，以準分子雷射光照射，其照射強度與 矽薄膜的薄片電阻値之關係如第5圖所示。這些各矽薄 膜是用電漿CVD法所形成，在於將基板溫度保持在室 -13- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注咅？事項再填寫本頁) 裝--------訂---------· 1283069 五、發明説明（12 ) 溫的狀態下，照射準分子雷射光以使其再結晶化，測定 矽薄膜的薄片電阻値。其結果是如第5圖可知，隨著所 照射準分子雷射光照射強度的增強，矽薄膜的薄片電阻 値會降低。此時，如逐漸增強準分子雷射光的照射強度 時，由於過大的能量之投入，膜會消蝕。但是，由膜厚 102nm的矽薄膜中得知，使照射強度爲23 0mJ/ cm2時 ，其薄片電阻可降到3 00 Ω /□。Substrate temperature 32Q°C decane flow rate 20sccm Hydrogen flow rate 1000Ocm phosphine (hydrogen dilution 〇 5%) flow rate 40sccm gas pressure 50Pa high frequency power density (continuous discharge) 128mW/cm2 typical film formation speed 3.7nm/min Ministry of Economic Affairs Intellectual Property Bureau Based on this formation condition, the employee consumption cooperative printed the film forming time of the tantalum film as three kinds of samples (40.7 nm, 68.5 nm, 104.6 nm) having different film thicknesses. Then, the sheet resistance of each film thickness was measured, and the sheet resistance was converted into a specific resistance. The results (the relationship between the film thickness and the sheet resistance and the resistivity) are shown in Fig. 3. From Fig. 3, it can be seen that the resistivity decreases as the film thickness increases. This implies that it produces a resistivity distribution in the film thickness direction. According to the above results, spectral polarization analysis (e 11 i p s 〇 m e t r y) was carried out, and the structural change in the film thickness direction was analyzed by Bruggeman's Effective Medium Approximation. This analysis was performed using the above three samples. Here, the film thickness is 40.7nm, -11- This paper scale is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) 1283069 V. Invention description (i〇) 68.5nm, and 104.6nm each film On the surface, surface oxide films having a film thickness of 3.4 nm, 9.2 nm, and 12.7 nm were formed, respectively. The analysis result of the sample having a film thickness of 40·7 nm is shown in the fourth (a) figure, and the analysis result of the sample having a film thickness of 68.5 nm is analyzed in the fourth (b) and the film thickness of 104.6 nm, and the result is in the fourth. (c) shown in the figure. These errors in measurement and analysis are adjusted by the introduction of void components. In the tantalum film having a thickness of 40.7 nm, as shown in Fig. 4(a), the amorphous germanium component in the gate layer of the lower layer (glass substrate side) of 1 3 · 1 nm is 100%, and the upper layer 27 · The crystalline germanium component in the 6 nm gate layer has risen to 14%. Secondly, in the sand film with a film thickness of 6 8 · 5 nm, it is known from the 4th (b) diagram that the crystalline germanium component is not observed in the gate layer of the lower layer of 27·1 nm, and the amorphous germanium is not observed. The composition has been reduced to 79%. Moreover, the crystalline bismuth composition in the gate layer of the upper layer of 1.4 nm has increased to 49%. Similarly, in the ruthenium film with a film thickness of 104.8 nm, as shown in Fig. 4(c), no crystalline yttrium component was observed in the gate ruthenium layer of the lower layer 42·1 nm, and the amorphous yttrium component was observed. Has been reduced to 70%. Also, in the upper 62.5 nm gate layer, the crystalline germanium composition has increased to 60%. Here, in the analysis result of the ruthenium film having a film thickness of 40·7 nm, the lower layer of the 13.1 nm gate ruthenium layer is 100°/. Since the amorphous tantalum component is composed of the other two tantalum films, it is presumed that the layer composed of the 100% amorphous tantalum component has a thickness of about 13 nm. For example, when a ruthenium film having a film thickness of 104.6 nm is described, it is conceivable that a layer of about 13 nm from the glass substrate in the lower layer of 42.1 nm is 100% amorphous -12-1283069 Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative Printed A7 B7 V. Inventive Note (11) A composition consisting of a ruthenium component, a layer having an upper portion of about 29 nm is a gradual increase in crystal composition. Thus, by controlling the film formation time of the tantalum film, the lower layer can be formed into an amorphous layer, and the upper layer can be formed into a crystalline layer. Based on this result, other embodiments (third and fourth embodiments) of the thin film transistor of the present invention will be described later. Further, the gate layer formed of the tantalum film formed by the plasma CVD method is a gate metal (metal wiring) as shown in the first and second embodiments, and may be in a large device such as an LCD. It can also reduce its wiring resistance. However, in the case where higher driving ability is required and the gate insulating film is thinned or the channel length is miniaturized, the gate layer is also required to have lower resistance. In this case, by applying heat treatment at a temperature of about 600 t to 100 ° C, crystallization of crystals can be promoted, whereby the gate can be reduced in resistance, but the substrate cannot be inexpensively low. Softening point glass (for example, glass that softens above 800 ° C). Therefore, based on the analysis result as follows, when the driving ability is required to be higher and the gate insulating film is thinned or the channel length is made fine, the invention of inexpensive low-softening point glass or the like can be used. The embodiment (the third and fourth embodiments) will be described. Here, a sample composed of a sand film using three kinds of film thicknesses (45 nm, 72 nm, 102 nm) is irradiated with excimer laser light, and the relationship between the irradiation intensity and the sheet resistance of the tantalum film is as shown in FIG. . These films are formed by plasma CVD, which is to keep the substrate temperature in the chamber-13- This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (please read the back note first) ? 再 填写 填写 ) ) ) - - - - - - - - 830 830 830 830 830 830 830 830 830 830 830 830 830 830 830 830 830 830 830 830 830 830 830 830 准 准 准The sheet resistance of the tantalum film was measured. As a result, as is apparent from Fig. 5, as the irradiation intensity of the irradiated excimer laser light is increased, the sheet resistance of the tantalum film is lowered. At this time, if the irradiation intensity of the excimer laser light is gradually increased, the film will be ablated due to excessive energy input. However, it was found from the ruthenium film having a film thickness of 102 nm that the sheet resistance was reduced to 300 Ω / □ when the irradiation intensity was 23 0 mJ/cm 2 .

其次，準分子雷射光的照射強度與矽薄膜或源極· 汲極領域的薄片電阻値之間的關係是如第6圖及第7圖 所示。第6圖是將矽薄膜及源極•汲極領域的膜厚各個 形成爲50nm，第7圖是將矽薄膜及源極•汲極領域的 膜厚各個形成爲75nm者。Next, the relationship between the irradiation intensity of the excimer laser light and the sheet resistance of the germanium film or the source/drain region is as shown in Figs. 6 and 7. Fig. 6 shows that the film thicknesses of the germanium film and the source and drain electrodes are each formed to be 50 nm, and the seventh figure is that the film thicknesses of the germanium film and the source and drain electrodes are each formed to be 75 nm.

各試樣是具備用低壓化學氣相沈積（以下稱LPCVD) 法所形成而持有源極•汲極領域之非晶質矽層，和在該 非晶質矽層上用電漿CVD法所形成的矽薄膜（閘極矽層 )。在此，源極•汲極領域是將以磷化氫氣體作爲原料 的磷離子，用離子摻雜法的引進所形成。此場合中，摻 雜時的注入量程是設定在膜厚的大略中央，但，由於未 被質量分離，因而，其係也含有由多數原子所構成的磷 離子、磷、及氫的結合離子，或氫離子等。 如第6圖及第7圖所示，準分子雷射光的照射強度爲 13 0〜2 00 mJ/ cm2時，閘極矽層及源極•汲極領域各個都 呈現同等的電阻値。由此可知，例如將準分子雷射光的 照射強度設定在130〜200 m〗/ cm2時，就可使各矽層的 低電阻化，和源極•汲極領域的活性化同時的進行。 在此，參照第8圖說明本發明的第3實施形態。此 -14- 1283069 A7 B7 五、發明說明（ι〇 第8圖中的符號3 0是表示本實施例中的薄膜電晶體。 (請先閱讀背面之注意事項再填寫本頁) 此薄膜電晶體3 0是如第8圖所示，具備：形成在絕 緣性基板2 1上的持有源極•汲極領域22a及通道領域 2 2b之結晶化矽薄膜22 ;形成在該結晶化矽薄膜22上 的第1閘極絕緣膜23 A ;以要覆蓋於該基板的凹凸部分 似的，形成在其上面之第2閘極絕緣膜23B ;和形成在 該第2閘極絕緣膜23B上之閘極24。又，此薄膜電晶 體30並具備形成在其凹凸部分的層間分離絕緣膜28 ; 和，埋設於形成在該層間分離絕緣膜2 8及第2閘極絕 緣膜23B的接觸孔27之金屬配線29。 其中，絕緣性基板2 1是使用在玻璃基板2 1 a上層疊 有由CVD氧化膜所構成的基板覆蓋膜21b者。又，第 1及第2閘極絕緣膜23 A，23B是由矽氧化膜或氮化膜 所形成。 經濟部智慧財產局員工消費合作社印製 在此，閘極24是具備形成在第2閘極絕緣膜23 B的 表面上，且在於通道領域22b上方的，由n +矽膜（矽薄 膜）25A所構成之閘極矽層25，和，形成在該閘極矽層 25上的閘極金屬27。此閘極矽層25是形成爲80nm的 膜厚，其下層部分（從第2閘極絕緣膜23B上算起的約 ‘ 13nm部分）是成爲非晶質層，上層部分（閘極矽層25的 扣掉下層部分之部分）是成爲結晶質層者。 如此的，在非晶質材料的第1及第2閘極絕緣膜23 A 、23B上，形成持有非晶層之閘極矽層25，因而，在 於要形成源極•汲極領域22a時，可防此如往例中的通 -15 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 1283069 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（I4) 道作用，而可抑制電晶體特性的劣化。 在此，參照第9圖及第1 0圖說明本實施形態的薄膜 電晶體30之製造方法。此第9圖及第1〇圖是表示其製 造工程是從第9(a)圖到第9(e)圖、第l〇(f)圖到第l〇(h) 圖的順序進行者。 首先，在於經過洗淨、將有機物、金屬、以及微粒 子等除去的玻璃基板2 1 a上，層疊由CVD氧化膜所構 成的基板覆蓋膜21b，以形成第9(a)圖所示之絕緣性基 板21。接著，在該絕緣性基板21上形成矽薄膜22A， 然後，經由要除去有機物、金屬、微粒子，以及表面氧 化膜的洗淨工程後，將其引進於薄膜形成裝置（圖未示） 內。 在此，基板覆蓋膜2 1 b是以可防止基板材料（儘可能 減低鹼金屬濃度的玻璃、表面經過拋光的石英或玻璃等 )所含有的有害雜質之擴散者較爲有效。在具體上，本 實施形態的基板覆蓋膜2 1 b是用氧化矽膜。此氧化矽膜 是以矽烷和氧爲原料氣體，用LPCVD法，以基板溫度 4 5(TC在玻璃基板21a上形成Ιμιη的膜厚。如此用 LPCVD法時’也可使其覆蓋於玻璃基板21a的保持區 域（例如第9(a)圖中的玻璃基板21a的下面部分）以外的 全部表面（圖未示）。 此時，基板覆蓋膜21b(氧化矽膜）也可用四氧乙基矽 烷（以下稱TEOS)和以氧氣爲原料的電漿CVD，或以 TEOS和臭氧爲原料的常壓CVD等來形成。 -16- Ϋ紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） "" -----------裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 1283069 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（I5) 接著，矽薄膜22A是以乙矽烷氣體爲原料，用 LPCVD法，在基板溫度5 0CTC下形成爲75nm的膜厚。 由此，矽薄膜22A中所含有的氫原子濃度會成爲1原 子％以下，因而，可防止在於後述的雷射光L1照工程 中，由於氫的放出所引起的矽薄膜2 2 A之乾斑等。 此時，於形成矽薄膜22A之際，也可用電漿CVD法 。像這樣用電漿CVD法，也可由調整絕緣性基板2 1的 溫度、氫/矽烷的流量比、以及氫/四氟化矽烷的流量比 等，以形成氫原子濃度低的矽薄膜22 A，而可獲得和用 LPCVD法時同樣的效果。 接著，如第9(b)圖所示，照射雷射光L1，矽薄膜 22A會被重整成爲結晶化矽薄膜22。此時，雷射結晶 化是在99.9999以上的高純度氮氣700托（1托=1.333x 1〇2帕斯卡（Pa))以上之氣氛中所進行，於照射雷射光 L1完了之後，引進氧氣。 . 在此，於引進氧氣之前進行氫電漿處理時，可使存 在於結晶化矽薄膜22中的懸空鍵進行純化。此氫電漿 處理也可在於第1及第2閘極絕緣膜23 A、23B、閘極 24，或金屬配線29等形成之後的階段進行之。但，如 要經過3 50°C上的製造工程之情形時，要在於該工程之 後才來進行，且在氫純化後的製造過程中，要將溫度保 持在3 5 0°C以下爲理想。 接著，將氣體排出後，經由基板搬運室（圖未示）搬運 到電漿CVD室（圖未示）。然後，在結晶化矽薄膜22上 -17- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） •---·--------裝--------訂 (請先閱讀背面之注意事項再填寫本頁)Each sample is formed by a low pressure chemical vapor deposition (hereinafter referred to as LPCVD) method and holds an amorphous germanium layer in the source/drain region, and is formed by plasma CVD on the amorphous germanium layer. The ruthenium film (gate 矽 layer). Here, the source/bungee field is formed by the introduction of a phosphorus ion using a phosphine gas as a raw material by an ion doping method. In this case, the implantation range at the time of doping is set at the approximate center of the film thickness. However, since it is not separated by mass, it also contains a combination of phosphorus ions, phosphorus, and hydrogen composed of a plurality of atoms. Or hydrogen ions, etc. As shown in Fig. 6 and Fig. 7, when the intensity of excimer laser light is 13 0 to 2 00 mJ/cm2, the gate 矽 layer and the source and drain electrodes each have the same resistance 値. From this, it is understood that, for example, when the irradiation intensity of the excimer laser light is set to 130 to 200 m / cm 2 , the reduction in resistance of each of the germanium layers can be performed simultaneously with the activation of the source and drain regions. Here, a third embodiment of the present invention will be described with reference to Fig. 8. This-14- 1283069 A7 B7 V. DESCRIPTION OF THE INVENTION (The symbol 30 in Fig. 8 is a thin film transistor in this embodiment. (Please read the back note first and then fill in this page.) This thin film transistor As shown in Fig. 8, the present invention includes a crystallized tantalum film 22 which is formed on the insulating substrate 21 and which has a source/drain region 22a and a channel region 22b; and is formed on the crystallized tantalum film 22 The first gate insulating film 23A on the upper surface; the second gate insulating film 23B formed thereon to cover the uneven portion of the substrate; and the gate formed on the second gate insulating film 23B Further, the thin film transistor 30 is provided with an interlayer insulating film 28 formed on the uneven portion thereof, and is buried in the contact hole 27 formed in the interlayer insulating film 28 and the second gate insulating film 23B. In the insulating substrate 21, the substrate cover film 21b made of a CVD oxide film is laminated on the glass substrate 2 1 a. Further, the first and second gate insulating films 23 A, 23B It is formed by a tantalum oxide film or a nitride film. Here, the gate electrode 24 is provided with a gate electrode layer 25 formed of a n + 矽 film (矽 film) 25A formed on the surface of the second gate insulating film 23 B and above the channel region 22b, and a gate metal 27 formed on the gate electrode layer 25. The gate electrode layer 25 is formed to have a film thickness of 80 nm, and a lower portion thereof (about '13 nm portion from the second gate insulating film 23B) It is an amorphous layer, and the upper layer portion (the portion of the gate electrode layer 25 that is deducted from the lower layer portion) is a crystalline layer. Thus, the first and second gate insulating films 23 of the amorphous material. On A and 23B, a gate layer 25 having an amorphous layer is formed. Therefore, when the source/drain region 22a is to be formed, it can be prevented as in the conventional example. Standard (CNS) A4 specification (210 X 297 public) 1283069 Ministry of Economic Affairs Intellectual Property Office employee consumption cooperative printed A7 B7 V. Invention Description (I4) The channel function can suppress the deterioration of the transistor characteristics. 9 and 10 show a method of manufacturing the thin film transistor 30 of the present embodiment. 1〇图 shows that the manufacturing process is from the 9th (a)th to the 9th (e)th, the 1st (f)th to the 1st (h)th order. First, it is washed. On the glass substrate 2 1 a from which the organic material, the metal, the fine particles, and the like are removed, the substrate cover film 21b made of a CVD oxide film is laminated to form the insulating substrate 21 shown in Fig. 9(a). The tantalum film 22A is formed on the insulating substrate 21, and then subjected to a cleaning process for removing organic substances, metals, fine particles, and surface oxide film, and then introduced into a thin film forming apparatus (not shown). Here, the substrate cover film 2 1 b is effective for preventing diffusion of harmful impurities contained in the substrate material (glass which has a reduced alkali metal concentration, polished quartz or glass, etc.). Specifically, the substrate cover film 2 1 b of the present embodiment is a hafnium oxide film. The ruthenium oxide film is made of decane and oxygen as a raw material gas, and is formed by a LPCVD method at a substrate temperature of 45 (TC is formed on the glass substrate 21a by a thickness of Ιμηη. Thus, by LPCVD method, it can be covered on the glass substrate 21a). The entire surface (for example, not shown) other than the holding portion (for example, the lower portion of the glass substrate 21a in Fig. 9(a)). At this time, the substrate covering film 21b (yttrium oxide film) may also be made of tetraoxoethyl decane ( The following is called TEOS) and plasma CVD using oxygen as raw material, or atmospheric pressure CVD using TEOS and ozone as raw materials. -16- Ϋ Paper scale is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) ) "" -----------Install--------Book--------- (Please read the notes on the back and fill out this page) 1283069 Economy Ministry of Intellectual Property Bureau employee consumption cooperative printed A7 B7 V. Inventive Note (I5) Next, the tantalum film 22A is formed by using an acetonitrile gas as a raw material, and is formed into a film thickness of 75 nm at a substrate temperature of 50 CTC by an LPCVD method. The concentration of hydrogen atoms contained in the ruthenium film 22A is 1 atom% or less. Therefore, it is possible to prevent the laser light to be described later. In the L1 illumination project, the dry film of the ruthenium film 2 2 A caused by the release of hydrogen, etc. At this time, when the ruthenium film 22A is formed, a plasma CVD method can also be used. The temperature of the insulating substrate 21, the flow ratio of hydrogen/decane, and the flow ratio of hydrogen to decane are adjusted to form a tantalum film 22A having a low hydrogen atom concentration, and the same as in the case of the LPCVD method. Next, as shown in Fig. 9(b), the laser light L1 is irradiated, and the tantalum film 22A is reformed to become the crystallized tantalum film 22. At this time, the laser crystallizing is a high-purity nitrogen gas of 700.999.99 or more. (1 Torr = 1.333 x 1 〇 Pascal (Pa)) is carried out in an atmosphere above, and after the irradiation of the laser light L1 is completed, oxygen is introduced. Here, the hydrogen plasma treatment may be performed before the introduction of oxygen. The dangling bonds in the crystallized tantalum film 22 are purified. The hydrogen plasma treatment may be performed at a stage after the formation of the first and second gate insulating films 23 A, 23B, the gate 24, or the metal wiring 29. However, if you want to go through the manufacturing process at 3 50 ° C, it is It is only after the completion of the project, and it is desirable to keep the temperature below 350 ° C in the manufacturing process after hydrogen purification. Next, after the gas is discharged, it is transported to the electricity via the substrate transfer chamber (not shown). Plasma CVD chamber (not shown). Then, on the crystallization film 22, the paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). ----------- ---装-------- order (please read the notes on the back and fill out this page)

1283069 五、發明説明（16 ) 形成由氧化矽膜所構成的，如第9(c)圖所示之第1閘極 絕緣膜2 3 A。此氧化砍膜是以砂院、氦、及氧爲原料氣 體，用電漿CVD法，在基板溫度350°C下，形成l〇nm 膜厚。然後，視其所需，進行氫電漿處理或退火處理。 接著，用光刻法以及蝕刻法技術，如第9(d)圖所示 形成由結晶化矽薄膜22和第1閘極絕緣膜23 A所構成 的疊層膜之島部。此時，第1閘極絕緣膜23 A是要選 用比結晶化矽薄膜22的腐蝕率爲高的蝕刻條件者爲理 想。即，如第9(d)圖所示，以可使結晶化矽薄膜22和 第1閘極絕緣膜23 A成爲階梯式（或錐形）的施加蝕刻爲 理想。由此，可防止閘漏電流，而可提供可靠性高的薄 膜電晶體30。 接著，經由要除去有機物、金屬、以及微粒子的洗 淨工程後，以要將上述島部覆蓋似的，形成由氧化矽膜 所構成的，如第9(e)圖所示之第2閘極絕緣膜23B。此 氧化矽膜是以矽烷和氧爲原料氣體，用LPCVD法，在 基板溫度450 °C下，形成30nm膜厚。此時氧化矽膜是 也可用以TEOS和氧氣爲原料的電漿CVD法，或以 TEOS和臭氧爲原料的常壓CVD法來形成。 然後，在第2閘極絕緣膜2 3 B上，用電漿C V D法形 成如第9(e)圖所示的，80nm膜厚之n +矽膜25A。接著 ，將此n +矽膜25A製成圖案，以使其在以後要成爲通 道領域22b的上方，保留著n +矽膜25a。由此，形成 如第1 〇 (f)圖所示的閘極矽層2 5。 -18- 1283069 Α7 Β7 五、發明說明（π) (請先閱讀背面之注意事項再填寫本頁) 接著’以閘極矽層25爲遮罩，注入雜質離子，形成 源極•汲極領域22a。此時，是用對於所要注入雜質離 子不做質量分離的離子摻雜法、離子注入法、電漿摻雜 法、或雷射摻雜法來形成。 在此，如要形成互補金氧半導體（以下稱CMOS)型電 路時，可倂用光刻法，以分開的作成n +領域所需的η 型通道保護膜薄膜TFT或電要ρ +領域的ρ型通道保護 Β TFT 〇 接著，再度照射準分子電射光L2。由此，閘極矽層 25及結晶化矽薄膜22會被低電阻化之同時，源極•汲 極領域22a也會被活性化。此時，第1及第2閘極絕緣 膜23 A、23B會由於其膜厚的關係，在其表面的，對準 分子雷射光L2之反射率會變化，因而要調整準分子雷 射光L2的照射強度，以使閘極矽層25及結晶化矽薄 膜22可獲得所欲電阻値的程度爲理想。例如此照射強 度是可由，所欲電阻値與照射強度特性來做決定。 經濟部智慧財產局員工消費合作社印製 又，由於是用LPCVD法以形成n +矽膜25A，因而， 可照射更高照射強度的準分子雷射光L2，由此，可使 閘極24更爲低電阻化。在此，用電漿CVD法所形成的 n +矽膜25 A之消蝕定限強度很小，因而，其與用 LPCVD法所形成的n +砂膜25A相比，較難於f吏其{氐電 阻化。因此，在本實施形態中，n +矽膜25 A雖用電漿 CVD法所形成，但如被要求閘極24的更低電阻化時， 可用消鈾開始強度較高的材料，其一例爲可使用用 -19- 冢紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公Μ ) 1283069 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（18) LPCVD法所形成的n +矽膜25A 〇 接著，以要將第2閘極絕緣膜23b及閘極矽層25覆 蓋似的，沈積1 1 0 nm膜厚之金屬膜或鎢矽化物膜等的 金屬矽化物膜後製成圖案，以保留閘極矽層25的上部 金屬膜或金屬矽化物膜的，形成如第10(g)圖之閘極金 屬26。 在此，在前工程中如不照射準分子雷射L2時，要在 於形成閘極金屬26後，施加5 5 0°C的熱處理，以使源 極•汲極領域22a活性化。此時，熱處理溫度可在400 °C〜6 0 0°C程度範圍做適當的選擇。 接著’在此凹凸部分沈積層間分離絕緣膜28後，以 光刻法及鈾刻法技術，形成如第10(h)圖所示的接觸孔 27。然後在其凹凸部分沈積金屬（鋁）後，以光刻法及蝕 刻法技術，形成金屬配線29。 在此，層間分離絕緣膜28是用可使膜平坦<化的 TEOS系氧化膜。此時，也可用二氧化矽系塗布膜，或 有機塗布膜以取代於TEOS系氧化膜。又，金屬配線 29也可用銅、以鋁或銅爲基礎材料的合金、或者是鎢 或鉬等的高熔點金屬以取代於鋁。 經過以上的製造工程，就可形成性能和可靠性高的 薄膜電晶體3 0。 其次，參照第1 1圖說明本發明薄膜電晶體的第4實 施形態。在第1 1圖中的符號40是表示本實施形態之薄 膜電晶體。 -20- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） j-----------裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 1283069 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（I9) 此薄膜電晶體40是如第11圖所示，具備：形成在 絕緣性基板3 1上的持有源極•汲極領域3 2 a及通道領 域3 2b之結晶化矽薄膜3 2 ;形成在該結晶化矽薄膜3 2 上，且是在通道領域32b上方的第1閘極絕緣膜33 A ; 形成在該第1閘極絕緣膜3 3 A上的第2閘極絕緣膜 33B ;和，形成在該第2閘極絕緣膜33B上的，由n +矽 膜（矽薄膜）35A所構成之閘極34。又，此薄膜電晶體 40並具備形成在其凹凸部分的層間分離絕緣膜3 8 ’和 被埋設於形成在該層間分離絕緣膜3 8的接觸孔3 7之金 屬配線3 9。 其中，絕緣性基板3 1是使用在玻璃基板3 1 a上層疊 有由CVD氧化膜所構成的基板覆蓋膜3 lb者。又，第 1及第2閘極絕緣膜3 3 A、3 3 B是由矽氧化膜、或氮化 膜所形成。 在此，n +矽膜35A是形成爲80nm的膜厚，.和第3實 施形態同樣，其下層部分（從第2閘極絕緣膜33B上算 起的約13nm部分）是成爲非晶質層，而其上層部分（n + 矽膜3 5 A的扣掉下層部分）是成爲結晶質層。 如此，在非晶質材料的第1及第2閘極絕緣膜33 A、 ‘ 33B上，形成持有非晶質層的閘極34，因而，在於要 形成源極•汲極領域32a之際，可防止如往例中的通道 作用，而可抑制電晶體特性的劣化。 在此，參照第9圖及第1 2圖說明本實施形態中的薄 膜電晶體40之製造方法。此第9圖及第12圖是表示其 -21- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ：—：--------裝--------訂---------^_wi (請先閱讀背面之注意事項再填寫本頁) 1283069 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（2G) 製造工程是從第9(a)圖到第9(e)圖、第12(f)、第12(g) 的順序進行者。 此薄膜電晶體4 0的到途中爲止是經過和第3實施形 態的薄膜電晶體30的製造工程同樣之工程（第9 (a)圖到 第9(e)圖爲止）所形成。因此，在此只對其以下的製程（ 第12(f)圖及第12(g)圖的工程）說明如下。又，此時， 是將第9(a)圖到第9(e)圖中的符號21改爲31，符號 21a改爲31a，符號21b改爲31b，符號22A改爲32A ，符號22改爲32，符號23A改爲33A，符號23B改爲 3 3 B，符號2 5 A改爲3 5 A。 形成第9(e)圖所示的n +矽膜35A後，製成圖案，以 如第1 2圖所示的保留以後會成爲通道領域3 2b的部分 上方之第1及第2閘極絕緣膜33 A、33B及n +矽膜35 A 。由此，而形成如第12(f)圖所示的閘極34。 接著，以閘極3 4作爲遮罩，形成注入雜質.離子的源 極•汲極領域32a。此時，是用對於所要注入離子不做 質量分離的離子摻雜法、離子注入法、電漿摻雜法、或 雷射摻雜法來形成。 在此，如要和3第實施形態同樣形成CMOS型電路 時，可倂用光刻法，以分開的作成n+領域所需的η型通 道保護膜TFT，或需要ρ +領域的ρ型通道保護膜TFT。 接著，再度照射準分子雷射光L2。由此，閘極34及 結晶化矽薄膜22會被低電阻化之同時，源極•汲極領 域也會被活性化。 -22- $紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） _~ Γ I I .--I I I I I · I I I I--丨訂·丨丨丨丨丨丨丨- (請先閱讀背面之注意事項再填寫本頁) 1283069 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（21 ) 接著’在此凹凸部分沈積層間分離絕緣膜3 8後，以 光刻法及蝕刻法技術形成如第12(g)圖所示之接觸孔37 。然後’在其凹凸部分沈積金屬（鋁）後，以光刻法及蝕 刻法技術，形成金屬配線3 9。 在此’層間分離絕緣膜3 8是用可使膜平坦化的 TEO S系氧化膜。此時，也可用二氧化矽塗布膜或有機 塗布膜以取代於TEOS系氧化膜。又，金屬配線39也 可用銅、以銅或鋁爲基礎材料的合金、或者是鎢或鉬等 的高熔點金屬，以取代於鋁。 經過以上的製造工程，就可形成性能和可靠性高的 薄膜電晶體40。 其次，第1 3圖是使用上述各實施形態薄膜電晶體的 ’由2nx2m位元之儲存格MEM2所構成的記憶陣列之 一例。此記憶體是由行解碼器MEM5從2n字中，指定 2m位元的一字，從列解碼器MEM4所存取的f?之2m位 元內指定2k位元。然後與外部介面（圖未示）之間，由 字線MEM1、位元線MEM3、放大器/驅動器MEM6、 列位址MEM7、行位址MEM8，傳送資料MEM9者。 接著，第1 4圖是使用上述各實施形態薄膜電晶體的 液晶光閥（液晶顯示器L C V 5 )之一例，第1 5圖是應用此 液晶光閥的投影機之一例。 液晶（象素LCV4)是如第14圖所示的，由周邊驅動電 路資料驅動器LCV1、閘驅動器LCV2連接於動態矩陣 LCV3、並受其驅動。於是，影像信號資料LCV6從外 -23- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） L^-------裝·-------訂--------- (請先閱讀背面之注意事項再填寫本頁) 1283069 A7 B7 五、發明說明（22) 部輸入，顯示在各象素LCV4上。 (請先閱讀背面之注意事項再填寫本頁) 第15圖所示的投影機LCV7是，由鹵素灯LCV8所 發出的光會經由雙向分光鏡LCV9入射於光閥LCV10， 其影象會經由投影透鏡LCV14投影到銀幕LCV15者。 在此，各光閥LCV 10是用分別對應於光線的紅色成分 LCV11、綠成分LCV12、及藍成分LCV13者。 又，除上述之外，本發明的薄膜電晶體也可用在非 晶質矽光二極體的驅動上。在此場合中，影像感測器是 由非晶質矽光二極體；由控制主掃描方向的薄膜電晶體 所構成的移位暫存器；和，讀出開關所構成。將光源、 影像感測器及纖維陣列板層疊，從影像感測器背面將經 過証明的原稿表面圖像用纖維陣列板讀取其圖像。由滾 輪及編碼器向副掃描方向進行移動位置的讀取，所讀出 的圖像信號會經由形成在印刷基板上的外部電路連接於 電腦或記錄裝置，由此形成爲攜帶型掃描器：在此是以 攜帶型掃描器爲例說明者，但本發明的薄膜電晶體也可 應用於平板型掃描器、傳真機、或數位複製機等的影像 感測器，或二維感測器上。 經濟部智慧財產局員工消費合作社印製 [產業上之利用領域] 本發明的薄膜電晶體是在其閘極設有非晶質層者。 因而，可抑制在於要用離子注入法或離子摻雜法，且以 閘極作爲遮罩，而自調合的形成源極•汲極領域時所注 入的或所引進的離子之通道作用所引起的弊病。由此， 可防上離子的更深入於內部，即透過閘極而到達鬧極絕 -24- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 1283069 經濟部智慧財產局員工消費合作社印製 Α7 Β7 五、發明說明（23) 緣膜中或結晶化矽薄膜中所產生的缺陷，而可設計其係 考慮到製造過程中的通道作用弊病之元件。 又’在於要在非晶質材料的閘極絕緣膜上形成閘極 之際，是在閘極絕緣膜上設置非晶質材料，或在與閘極 絕緣膜的界面設具非晶質層的矽薄膜，因而，可穩定的 形成_極。 又，將矽薄膜製成圖案作爲閘極後，以此矽薄膜作 爲遮罩，在結晶化矽薄膜上形成源極•汲極領域，然後 照射所定強度之雷射光，由此使矽薄膜及結晶化矽薄膜 低電阻化之同時，可使源極•汲極領域活性化，也即可 獲得從來沒有的優異薄膜電晶體。 [圖式之簡單說明] 第1圖係本發明薄膜電晶體的第1實施形態之構造 圖。 第2(a)圖係本發明薄膜電晶體的第2實施形態圖，第 2(b)圖係第2(a)圖中的箭頭A-A線之斷面圖。 第3圖係表示不同膜厚的各矽薄膜之薄片電阻和電 阻率的表。 第4圖係表示矽薄膜的上層和下層中的成分之表， 第4(a)圖是膜厚40.7nm，第4(b)圖是膜厚68.5nm，第 4(c)是膜厚104.6nm的矽薄膜的表。 第5圖係表示不同膜厚的各矽薄膜中，準分子雷射 光的照射強度與矽薄膜的薄片電阻値之關係表。 第6圖係在於由50μπι膜厚所構成的矽薄膜及源極· -25- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -L---^-----I I · I I I----訂--------- (請先閱讀背面之注意事項再填寫本頁) 1283069 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（24) 汲極領域中，準分子雷射光的照射強度與矽薄膜成源極 •汲極領域的薄片電阻値之關係圖。 第7圖係在於由7 5 n m膜厚所構成的砂薄膜及源極· 汲極領域中，準分子雷射光的照射強度與砂薄膜或源極 •汲極領域的薄片電阻値之關係圖。 第8圖係本發明薄膜電晶體的第3實施形態之構造 圖。 第9圖係第9(a)圖到第9(e)圖是本實施形態的薄膜電 晶體之製造工程圖，是從第9(a)圖到第9(e)圖的順序進 行其製造工程者。 第10圖係第10(f)圖到第10(h)圖是本實施形態的薄 膜電晶體之製造工程圖，是連續於第9(e)圖的工程並從 第10(f)圖到第10(h)圖的順序進行其製造工程者。 第1 1圖係本發明薄膜電晶體的第43實施形態之構 造圖。 < 第12圖係第12(f)圖及第12(g)圖是本實施形態的薄 膜電晶體之製造工程圖，是連續於第9(e)圖的工程，並 依第12(f)圖、第12(g)圖的順序進行其製造工程者。 第1 3圖係將本發明薄膜電晶體應用於記憶體時之例 示圖。 第1 4圖係將本發明薄膜電晶體應用於液晶顯示元件 時之例示圖。 第1 5圖係將本發明薄膜電晶體應用於投影機時之例 示圖。 -26- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） II Γ I---------I I ----II--- (請先閱讀背面之注意事項再填寫本頁) 1283069 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（25) [參考符號說明] 1 .....絕緣性基板 2 .....結晶化矽薄膜 2a.....源極•汲極領域 2 b.....通道領域 3 .....閘極絕緣膜 4 .....閘極 5 .....下層閘極砂（非晶質層） 6 .....上層閘極矽（結晶質層） 7 .....閘極金屬 10 .....薄膜電晶體 11 .....絕緣性基板 12 · · · · ·結晶化矽薄膜 12a.....源極•汲極領域 12b.....通道領域 13 .....閘極絕緣膜 14 .....闊極 15 .....下層閘極矽（非晶質層） 16 .....上層閘極矽（結晶質層） 17 .....接觸孔 18 .....層間分離絕緣膜 19 .....金屬配線 20 .....薄膜電晶體 2 1.....絕緣性基板 -27- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） J---I I I I I I ·1111111 ^ ·11111111 (請先閱讀背面之注意事項再填寫本頁) 1283069 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（26) 2 1a.....玻璃基板 21b.....基板覆蓋膜 22 .....結晶化矽薄膜 22a.....源極•汲極領域 22b.....通道領域 23 A.....第1閘極絕緣膜 23B.....第2閘極絕緣膜 2 4.....閛極 2 5.....間極砂層 2 6.....闊極金屬 2 7.....接觸孔 28.....層間分離絕緣膜 2 9· · · ••金屬配線 30.....薄膜電晶體 3 1.....絕緣性基板 3 1a.....玻璃基板 31b.....基板覆蓋膜 32.....結晶化矽薄膜 32a.....源極•汲極領域 3 2b.....通道領域 33A.....第1閘極絕緣膜 33B.....第2閘極絕緣膜 3 4.....聞極 37.....接觸孔 -28- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----Γ---------------訂·-------IAWI (請先閱讀背面之注意事項再填寫本頁) 1283069 A7 B7 五、發明說明（27) 8 9 0 3 3 4 膜 緣 絕體 離線晶 分配電 間屬膜 層金薄 (請先閱讀背面之注意事項再填寫本頁) -· n ϋ I n ·ϋ ϋ ϋ 一-口，Μ ·ΒΒ I 1^·· MB Μ» ΙΒΙΒ < 經濟部智慧財產局員工消費合作社印製 9 -2 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）1283069 V. Description of Invention (16) A first gate insulating film 2 3 A composed of a hafnium oxide film as shown in Fig. 9(c) is formed. The oxidized chopping film is a gas source of sand, enamel, and oxygen, and a film thickness of 10 nm is formed by a plasma CVD method at a substrate temperature of 350 °C. Then, hydrogen plasma treatment or annealing treatment is performed as needed. Then, the island portion of the laminated film composed of the crystallized tantalum film 22 and the first gate insulating film 23 A is formed by photolithography and etching techniques as shown in Fig. 9(d). At this time, it is desirable that the first gate insulating film 23A is to be selected to have a higher etching rate than the crystallized tantalum film 22. In other words, as shown in Fig. 9(d), it is preferable to apply etching which makes the crystallized tantalum film 22 and the first gate insulating film 23A stepwise (or tapered). Thereby, the gate leakage current can be prevented, and the highly reliable thin film transistor 30 can be provided. Next, after the cleaning process of removing the organic matter, the metal, and the fine particles, the second gate shown in FIG. 9(e) is formed by covering the island portion so as to cover the island portion. Insulating film 23B. This ruthenium oxide film was made of decane and oxygen as a raw material gas, and a film thickness of 30 nm was formed by a LPCVD method at a substrate temperature of 450 °C. At this time, the ruthenium oxide film can also be formed by a plasma CVD method using TEOS and oxygen as a raw material, or an atmospheric pressure CVD method using TEOS and ozone as raw materials. Then, on the second gate insulating film 2 3 B, an n + germanium film 25A having a film thickness of 80 nm as shown in Fig. 9(e) is formed by a plasma C V D method. Next, the n + germanium film 25A is patterned so as to be above the channel region 22b, and the n + germanium film 25a remains. Thereby, the gate 矽 layer 25 as shown in the first 〇 (f) is formed. -18- 1283069 Α7 Β7 V. Invention description (π) (Please read the note on the back and fill in this page.) Next, use the gate layer 25 as a mask to inject impurity ions to form the source•bungee field 22a. . At this time, it is formed by an ion doping method, an ion implantation method, a plasma doping method, or a laser doping method which does not perform mass separation for the impurity ions to be implanted. Here, in order to form a complementary MOS (hereinafter referred to as CMOS) type circuit, photolithography may be used to separately form an n-type channel protective film thin film TFT or an electric ρ + field required for the n + field. The p-channel protection Β TFT 〇 then illuminates the excimer electroluminescence L2 again. As a result, the gate electrode layer 25 and the crystallized tantalum film 22 are reduced in resistance, and the source/drain region 22a is also activated. At this time, the first and second gate insulating films 23 A and 23B have a change in the reflectance of the aligned molecular laser light L2 on the surface thereof due to the film thickness, and thus the excimer laser light L2 is adjusted. The irradiation intensity is such that the desired thickness of the gate electrode layer 25 and the crystallized tantalum film 22 can be obtained. For example, the intensity of the illumination can be determined by the desired resistance 値 and the intensity of the illumination. The Ministry of Economic Affairs, the Intellectual Property Bureau, the employee consumption cooperative, also printed, because the LPCVD method is used to form the n + tantalum film 25A, so that the excimer laser light L2 with higher irradiation intensity can be irradiated, thereby making the gate 24 more Low resistance. Here, the n + ruthenium film 25 A formed by the plasma CVD method has a very low extinction limit strength, and therefore, it is more difficult to be compared with the n + sand film 25A formed by the LPCVD method.氐 Resistance. Therefore, in the present embodiment, the n + ruthenium film 25 A is formed by a plasma CVD method. However, when the lower resistance of the gate electrode 24 is required, a material having a high uranium-initiating strength can be used, and an example thereof is Can be used with the -19- 冢 paper scale applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 metric tons) 1283069 Ministry of Economic Affairs Intellectual Property Office Staff Consumer Cooperative Printed A7 B7 V. Invention Description (18) Formed by LPCVD n + 矽 film 25A 〇 Next, after the second gate insulating film 23b and the gate 矽 layer 25 are to be covered, a metal film such as a film thickness of 1 10 nm or a metal bismuth film such as a tungsten bismuth film is deposited. The pattern is patterned to retain the upper metal film or the metal halide film of the gate layer 25 to form the gate metal 26 as shown in Fig. 10(g). Here, in the case where the excimer laser L2 is not irradiated in the prior art, after the gate metal 26 is formed, heat treatment at 550 °C is applied to activate the source/drain region 22a. At this time, the heat treatment temperature can be appropriately selected in the range of 400 ° C to 600 ° C. Then, after the insulating film 28 is separated between the uneven portions, the contact holes 27 as shown in Fig. 10(h) are formed by photolithography and uranium etching. Then, after depositing metal (aluminum) on the uneven portion thereof, the metal wiring 29 is formed by photolithography and etching. Here, the interlayer separation insulating film 28 is a TEOS-based oxide film which can flatten and flatten the film. In this case, a ruthenium dioxide-based coating film or an organic coating film may be used instead of the TEOS-based oxide film. Further, the metal wiring 29 may be replaced by copper, an alloy based on aluminum or copper, or a high melting point metal such as tungsten or molybdenum. Through the above manufacturing process, a thin film transistor 30 having high performance and reliability can be formed. Next, a fourth embodiment of the thin film transistor of the present invention will be described with reference to Fig. 1 . Reference numeral 40 in Fig. 1 denotes a film transistor of this embodiment. -20- This paper scale applies to China National Standard (CNS) A4 specification (210 X 297 public) j-----------Install--------Book ------ --- (Please read the note on the back and fill out this page) 1283069 Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative printed A7 B7 V. Invention Description (I9) This thin film transistor 40 is as shown in Figure 11 a crystallized tantalum film 3 2 having a source/drain region 3 2 a and a channel region 3 2b formed on the insulating substrate 31; formed on the crystallized tantalum film 3 2 and in the channel field a first gate insulating film 33 A above 32b; a second gate insulating film 33B formed on the first gate insulating film 3 3 A; and a second gate insulating film 33B formed on the second gate insulating film 33B The gate 34 formed by the n + germanium film (germanium film) 35A. Further, the thin film transistor 40 is provided with an interlayer separation insulating film 38' formed on the uneven portion thereof and a metal wiring 39 buried in the contact hole 37 formed in the interlayer insulating film 38. Among them, the insulating substrate 31 is formed by laminating a substrate covering film 3b composed of a CVD oxide film on a glass substrate 31a. Further, the first and second gate insulating films 3 3 A and 3 3 B are formed of a tantalum oxide film or a nitride film. Here, the n + germanium film 35A is formed to have a film thickness of 80 nm, and the lower layer portion (about 13 nm portion from the second gate insulating film 33B) is an amorphous layer as in the third embodiment. And the upper layer portion (n + 矽 film 35 A is deducted from the lower layer portion) becomes a crystalline layer. In this manner, the gate electrode 34 having the amorphous layer is formed on the first and second gate insulating films 33 A and '33B of the amorphous material, and therefore, the source/drain region 32a is formed. It can prevent the channel action as in the previous example, and can suppress the deterioration of the transistor characteristics. Here, a method of manufacturing the thin film transistor 40 of the present embodiment will be described with reference to Figs. 9 and 2 . Figures 9 and 12 show that the 21-sheet size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm): —:--------Install----- ---Book---------^_wi (Please read the note on the back and fill out this page) 1283069 Ministry of Economic Affairs Intellectual Property Bureau Staff Consumer Cooperative Printed A7 B7 V. Invention Description (2G) Manufacturing Engineering It is the order from the 9th (a)th to the 9th (e), 12th (f), and 12th (g). This thin film transistor 40 is formed in the same manner as in the manufacturing process of the thin film transistor 30 of the third embodiment (from the 9th to the 9th (e)th). Therefore, only the following processes (the works of the 12th (f)th and 12th (g) drawings) are explained below. Also, at this time, the symbol 21 in the 9th (a)th to the 9th (e)th figure is changed to 31, the symbol 21a is changed to 31a, the symbol 21b is changed to 31b, the symbol 22A is changed to 32A, and the symbol 22 is changed to 32, the symbol 23A is changed to 33A, the symbol 23B is changed to 3 3 B, and the symbol 2 5 A is changed to 3 5 A. After forming the n + germanium film 35A shown in Fig. 9(e), a pattern is formed, and after the retention as shown in Fig. 2, the first and second gate insulating portions above the portion of the channel region 3 2b are formed. Membrane 33 A, 33B and n + tantalum film 35 A . Thereby, the gate electrode 34 as shown in Fig. 12(f) is formed. Next, using the gate 34 as a mask, a source/drain region 32a into which impurities and ions are implanted is formed. At this time, it is formed by an ion doping method, an ion implantation method, a plasma doping method, or a laser doping method which does not perform mass separation for ions to be implanted. Here, when a CMOS type circuit is to be formed in the same manner as in the third embodiment, photolithography can be used to separately form an n-type channel protective film TFT required for the n+ field, or a p-type channel protection of the ρ + field is required. Film TFT. Then, the excimer laser light L2 is again irradiated. As a result, the gate electrode 34 and the crystallized tantalum film 22 are reduced in resistance, and the source/drain region is also activated. -22- $ Paper scale applies to China National Standard (CNS) A4 specification (210 X 297 mm) _~ Γ II .--IIIII · III I--丨 丨丨丨丨丨丨丨 丨丨丨丨丨丨丨 - (please read first Note on the back side of this page) 1283069 Ministry of Economic Affairs Intellectual Property Office Staff Consumer Cooperatives Print A7 B7 V. Invention Description (21) Next, after separating the insulating film 38 between the uneven portions, photolithography and etching The technique forms a contact hole 37 as shown in Fig. 12(g). Then, after metal (aluminum) is deposited on the concavo-convex portion, metal wiring 39 is formed by photolithography and etching techniques. Here, the interlayer insulating film 38 is a TEO S-based oxide film which can flatten the film. At this time, a ruthenium dioxide coating film or an organic coating film may be used instead of the TEOS oxide film. Further, the metal wiring 39 may be made of copper, an alloy of copper or aluminum as a base material, or a high melting point metal such as tungsten or molybdenum instead of aluminum. Through the above manufacturing process, the thin film transistor 40 having high performance and reliability can be formed. Next, Fig. 1 is an example of a memory array composed of a cell MEM2 of 2nx2m bits using the thin film transistor of each of the above embodiments. This memory is a word of 2 m bits from 2n words by the row decoder MEM5, and 2k bits are specified from 2 m bits of f? accessed by the column decoder MEM4. Then, between the external interface (not shown), the data MEM9 is transmitted by the word line MEM1, the bit line MEM3, the amplifier/driver MEM6, the column address MEM7, and the row address MEM8. Next, Fig. 14 is an example of a liquid crystal light valve (liquid crystal display L C V 5 ) using the thin film transistor of each of the above embodiments, and Fig. 15 is an example of a projector to which the liquid crystal light valve is applied. The liquid crystal (pixel LCV4) is as shown in Fig. 14, and is driven by the peripheral driving circuit data driver LCV1 and the gate driver LCV2 to be connected to the dynamic matrix LCV3. Therefore, the image signal data LCV6 is applied to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) from the outer-23- paper scale. L^-------Installation-------- -------- (Please read the notes on the back and fill out this page) 1283069 A7 B7 V. Invention Description (22) Inputs are displayed on each pixel LCV4. (Please read the note on the back and fill out this page.) The projector LCV7 shown in Figure 15 is that the light emitted by the halogen lamp LCV8 is incident on the light valve LCV10 via the bidirectional beam splitter LCV9, and its image is projected. The lens LCV14 is projected onto the screen LCV15. Here, each of the light valves LCV 10 is a red component LCV11, a green component LCV12, and a blue component LCV13 respectively corresponding to light. Further, in addition to the above, the thin film transistor of the present invention can also be used for driving a non-crystalline phosphor diode. In this case, the image sensor is composed of an amorphous neon diode; a shift register formed of a thin film transistor for controlling the main scanning direction; and a read switch. The light source, the image sensor, and the fiber array plate are stacked, and the image of the certified original surface image is read from the back of the image sensor by the fiber array plate. The moving position is read by the roller and the encoder in the sub-scanning direction, and the read image signal is connected to the computer or the recording device via an external circuit formed on the printed substrate, thereby forming a portable scanner: This is an example of a portable scanner, but the thin film transistor of the present invention can also be applied to an image sensor such as a flatbed scanner, a facsimile machine, or a digital copying machine, or a two-dimensional sensor. Printed by the Intellectual Property Office of the Ministry of Economic Affairs, the Consumers' Cooperatives [Industrial Applicability] The thin film transistor of the present invention is an amorphous layer provided on its gate. Therefore, it can be suppressed by the ion implantation method or the ion doping method, and the gate is used as a mask, and the self-aligned formation of the source/drain region is caused by the channel action of the ion implanted or introduced. Disadvantages. Therefore, it is possible to prevent the ion from being deeper into the interior, that is, through the gate to reach the extremes - 24 - This paper scale applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 1283069 Ministry of Economic Affairs Intellectual Property Bureau Employees' Consumption Cooperatives Printed on Β7 Β7 5. Inventive Note (23) Defects in the film or in the crystallization of the ruthenium film, which can be designed to take into account the components of the channel during manufacturing. In addition, when a gate is formed on the gate insulating film of the amorphous material, an amorphous material is provided on the gate insulating film, or an amorphous layer is provided at the interface with the gate insulating film. The ruthenium film, therefore, can form a stable _ pole. Further, after the ruthenium film is patterned as a gate, the ruthenium film is used as a mask to form a source/drain region on the crystallization ruthenium film, and then irradiated with a predetermined intensity of laser light, thereby causing the ruthenium film and crystallization. The low-resistance of the palladium film can activate the source/drain region and obtain an excellent thin film transistor that has never been achieved. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a structural view showing a first embodiment of a thin film transistor of the present invention. Fig. 2(a) is a view showing a second embodiment of the thin film transistor of the present invention, and Fig. 2(b) is a cross-sectional view taken along line A-A of Fig. 2(a). Fig. 3 is a table showing the sheet resistance and resistivity of each of the films of different film thicknesses. Fig. 4 is a table showing the components in the upper and lower layers of the tantalum film, the fourth layer (a) is a film thickness of 40.7 nm, the fourth (b) is a film thickness of 68.5 nm, and the fourth (c) is a film thickness of 104.6. A table of nm thin films. Fig. 5 is a graph showing the relationship between the irradiation intensity of excimer laser light and the sheet resistance of the tantalum film in each of the films of different film thicknesses. Figure 6 is a ruthenium film and source consisting of 50μπι film thickness. -25- This paper scale is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) -L---^---- -II · II I----订--------- (Please read the notes on the back and fill out this page) 1283069 Ministry of Economic Affairs Intellectual Property Bureau Staff Consumer Cooperatives Print A7 B7 V. Invention Description ( 24) In the bungee field, the relationship between the intensity of excimer laser light and the sheet resistance of the tantalum film and the sheet resistance in the bungee field. Fig. 7 is a graph showing the relationship between the irradiation intensity of excimer laser light and the sheet resistance of the sand film or the source/drain region in the field of the sand film and the source and drain electrodes composed of the film thickness of 7 5 n m. Fig. 8 is a structural view showing a third embodiment of the thin film transistor of the present invention. Fig. 9 is a view showing the manufacturing process of the thin film transistor of the present embodiment, and the manufacturing process of the thin film transistor of the present embodiment is carried out in the order of Fig. 9(a) to Fig. 9(e). Engineer. Fig. 10 is a manufacturing drawing of the thin film transistor of the present embodiment, and is a drawing continuous to the drawing of Fig. 9(e) and from Fig. 10(f) to Fig. 10(f) to 10(h). The order of Figure 10(h) is carried out by its manufacturing engineer. Fig. 1 is a view showing the configuration of a 43rd embodiment of the thin film transistor of the present invention. < Fig. 12 is a view showing a manufacturing process of the thin film transistor of the present embodiment, which is a process continuous to the figure 9(e), and is based on the 12th (f) The figure and the 12th (g) figure are in the order of the manufacturing engineer. Fig. 13 is a view showing an example in which the thin film transistor of the present invention is applied to a memory. Fig. 14 is a view showing an example of the case where the thin film transistor of the present invention is applied to a liquid crystal display element. Fig. 15 is a view showing an example in which the thin film transistor of the present invention is applied to a projector. -26- This paper scale applies to China National Standard (CNS) A4 specification (210 X 297 mm) II Γ I---------II ----II--- (Please read the back of the note first) 1230 69 A7 B7 Ministry of Economic Affairs Intellectual Property Bureau Staff Consumer Cooperative Printed 5, Invention Description (25) [Reference Symbol Description] 1 ..... Insulating Substrate 2 ..... Crystallized Bismuth Film 2a.....source•bungee field 2 b.....channel field 3 ..... gate insulating film 4 ..... gate 5 ..... lower gate sand ( Amorphous layer) 6 ..... upper gate 矽 (crystal layer) 7 ..... gate metal 10 ..... thin film transistor 11 ..... insulating substrate 12 · · · · · Crystallized tantalum film 12a.....source pole•bungee field 12b.....channel field 13 ..... gate insulating film 14 ..... wide pole 15 .... Lower gate 矽 (amorphous layer) 16 ..... upper gate 矽 (crystal layer) 17 ..... contact hole 18 ..... interlayer separation insulating film 19 ..... Metal wiring 20 ..... Thin film transistor 2 1.....Insulating substrate -27- This paper scale is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) J---IIIIII ·1111111 ^ ·11 111111 (Please read the note on the back and fill out this page) 1283069 A7 B7 Ministry of Economic Affairs Intellectual Property Bureau Staff Consumer Cooperative Printed V. Inventions (26) 2 1a.....glass substrate 21b.....substrate Cover film 22 ..... Crystallized tantalum film 22a..... Source • Bungee field 22b.....Channel field 23 A.....1st gate insulating film 23B.... .2nd gate insulating film 2 4.....bung pole 2 5.....between sand layer 2 6..... wide pole metal 2 7.....contact hole 28.... Interlayer separation insulating film 2 9 · · · • Metal wiring 30..... Thin film transistor 3 1.....Insulating substrate 3 1a.....glass substrate 31b.....substrate coverage Film 32.....crystallized tantalum film 32a.....source pole•bungee field 3 2b.....channel field 33A.....first gate insulating film 33B..... The second gate insulating film 3 4.....When the electrode is 37.....Contact hole -28- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ----Γ ---------------Book·-------IAWI (Please read the note on the back and fill out this page) 1283069 A7 B7 V. Description of invention (27) 8 9 0 3 3 4 Membrane edge extinction Crystal distribution (Please read the notes on the back and fill out this page) -· n ϋ I n ·ϋ ϋ ϋ 一-口,Μ ·ΒΒ I 1^·· MB Μ» ΙΒΙΒ < Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative 9 -2 This paper scale applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm)

Claims (1)

1283069 六、申請專利範圍 第9 0 1 1 3 3 3 4號「薄膜電晶體及其製造方法」專利案 (91年12月3日修正） 六、申請專利範圍： 1 . 一種矽薄膜，係在非晶質膜上以一定條件連續形 成，其特徵爲具有形成在該非晶質膜上的下層和 形成在該下層上的上層，而該下層係非晶質層， 該上層係結晶質層。 2 ·如申請專利範圍第1項之矽薄膜，其中在該下層及該 上層係摻雜磷，砷或硼之雜質。 3 .如申請專利範圍第丨項之矽薄膜，其中該結晶質層中 的結晶成分係隨著遠離該下層而增加。 4. 一種薄膜電晶體，具有形成在基板上的源極，汲極領 域及通道領域的結晶化矽薄膜，形成在該結晶化矽薄 膜上的閘極絕緣膜；以及形成在該閘極絕緣膜上且含 有矽薄膜所形成之閘極電極，其中該矽薄膜係具有在 該閘極絕緣膜上以一定條件連續形成的下層及上層， 該下層係非晶質層，該上層係結晶質層。 5 ·如申請專利範圍第4項之薄膜電晶體，其中該閘極電 極係包含有形成在該矽薄膜上的閘極金屬所構成。 6 .如申請專利範圍第5項之薄膜電晶体，其中該閘極金 屬爲金屬或金屬氧化物所構成。 7.—種薄膜電晶體之製造方法，包含：在基板上形成源 極’汲極領域用之結晶化矽薄膜的步驟，在該結晶化 1283069 六、申請專利範圍 矽薄膜上形成閘極絕緣膜的步驟，以及在該閘極絕緣 膜上形成閘極電極的步驟， 其特徵爲：在形成該閘極電極的步驟中，於形成作爲 該閘極電極的構成要素之非晶質層及結晶質層之際， 以該非晶質層及該結晶質層之順序，在同一條件下連 續形成。 8 .如申請專利範圍第7項之薄膜電晶體之製造方法，其 中係根據電漿化學沈積法執行該非晶質層及該結晶質 層之形成。 9 .如申請專利範圍第7項之薄膜電晶体之製造方法，其 中在形成該非晶質層及該結晶質層之後，照射雷射 光。 10 .如申請專利範圍第7至9項中任一項之薄膜電晶体之 製造方法、其中在該閘極絕緣膜上形成該非晶質層、 在該非晶質層上形成該結晶質層。 11 · 一種薄膜電晶体之製造方法，包含：在基板上形成 源極，汲極領域用之結晶化矽薄膜的步驟，在該結晶 化砂薄膜上形成閘極絕緣膜的步驟，以及在該閘極絕 緣膜上形成閘極電極的步驟， 其特徵爲：在形成該閘極電極的步驟中，於形成作爲 該閘極電極之構成要素的矽薄膜之際，將該矽薄膜以 一定條件連續形成，該矽薄膜之該閘極絕緣膜側的部 分係成爲非晶質層，且與該閘極絕緣膜相反側的部分 1283069 六、申請專利範圍 係成爲結晶質層般地控制該矽薄膜的成膜時間。 1 2 .如申請專利範圍第1 1項之薄膜電晶體之製造方法， 其中在構成該矽薄膜之後，執行300°C以上的退火， 然後執行氫導入處理。 13 .如申請專利範圍第1 1項之薄膜電晶體之製造方法， 其中將該矽薄膜製成圖案之後，將該矽薄膜作爲遮 罩，形成該源極，汲極領域，然後照射雷射光。 1 4 ·如申請專利範圍第1 1至1 3項中任一項之薄膜電晶體 之製造方法，其中將該矽薄膜形成在該閘極絕緣膜。1283069 VI. Patent Application No. 9 0 1 1 3 3 3 4 "Thin Film Transistor and Its Manufacturing Method" Patent Case (Revised on December 3, 1991) VI. Patent Application Range: 1. A enamel film is attached The amorphous film is continuously formed under certain conditions, and has a lower layer formed on the amorphous film and an upper layer formed on the lower layer, and the lower layer is an amorphous layer, and the upper layer is a crystalline layer. 2) A film according to the first aspect of the patent application, wherein the lower layer and the upper layer are doped with impurities of phosphorus, arsenic or boron. 3. A film according to the ninth aspect of the invention, wherein the crystalline component in the crystalline layer increases as it moves away from the lower layer. A thin film transistor having a source formed on a substrate, a crystallized tantalum film in the field of the drain and the channel, a gate insulating film formed on the crystallized tantalum film; and a gate insulating film formed on the gate insulating film And a gate electrode formed by the ruthenium film, wherein the ruthenium film has a lower layer and an upper layer continuously formed on the gate insulating film under certain conditions, and the lower layer is an amorphous layer, and the upper layer is a crystalline layer. 5. The thin film transistor of claim 4, wherein the gate electrode comprises a gate metal formed on the tantalum film. 6. The thin film transistor of claim 5, wherein the gate metal is a metal or a metal oxide. 7. A method for producing a thin film transistor, comprising: forming a gated crystallized tantalum film for use in a source field on a substrate, and forming a gate insulating film on the film of the crystallized 12283069 And a step of forming a gate electrode on the gate insulating film, characterized in that in the step of forming the gate electrode, forming an amorphous layer and a crystalline substance as constituent elements of the gate electrode In the case of the layer, the amorphous layer and the crystalline layer are successively formed under the same conditions. 8. The method of producing a thin film transistor according to claim 7, wherein the amorphous layer and the crystalline layer are formed by a plasma chemical deposition method. 9. The method of producing a thin film transistor according to claim 7, wherein the laser beam is irradiated after the amorphous layer and the crystalline layer are formed. The method for producing a thin film transistor according to any one of claims 7 to 9, wherein the amorphous layer is formed on the gate insulating film, and the crystalline layer is formed on the amorphous layer. 11 . A method of manufacturing a thin film transistor, comprising: forming a source on a substrate, a step of crystallizing a germanium film for use in the field of germanium, a step of forming a gate insulating film on the crystallized sand film, and a step of forming the gate insulating film on the crystallized sand film a step of forming a gate electrode on a pole insulating film, characterized in that, in the step of forming the gate electrode, the tantalum film is continuously formed under certain conditions at the time of forming a tantalum film as a constituent element of the gate electrode The portion of the ruthenium film on the side of the gate insulating film is an amorphous layer, and the portion on the opposite side of the gate insulating film is 1283069. The patent application scope controls the formation of the ruthenium film as a crystalline layer. Membrane time. The method for producing a thin film transistor according to the first aspect of the invention, wherein after the ruthenium film is formed, annealing at 300 ° C or higher is performed, and then hydrogen introduction treatment is performed. 13. The method of producing a thin film transistor according to claim 11, wherein the ruthenium film is patterned, the ruthenium film is used as a mask to form the source, the drain region, and then the laser light is irradiated. The method for producing a thin film transistor according to any one of claims 1 to 3, wherein the tantalum film is formed on the gate insulating film.
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KR20030028489A (en) 2003-04-08
US7052944B2 (en) 2006-05-30
JP4389359B2 (en) 2009-12-24
EP1304746A4 (en) 2006-01-11
KR100517037B1 (en) 2005-09-26
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ATE429036T1 (en) 2009-05-15
US20030096462A1 (en) 2003-05-22

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