TWI278034B - A method of manufacturing a semiconductor device - Google Patents
A method of manufacturing a semiconductor device Download PDFInfo
- Publication number
- TWI278034B TWI278034B TW090107398A TW90107398A TWI278034B TW I278034 B TWI278034 B TW I278034B TW 090107398 A TW090107398 A TW 090107398A TW 90107398 A TW90107398 A TW 90107398A TW I278034 B TWI278034 B TW I278034B
- Authority
- TW
- Taiwan
- Prior art keywords
- conductor
- layer
- etch stop
- top surface
- stop layer
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 5
- 239000004020 conductor Substances 0.000 claims abstract description 77
- 238000000034 method Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000000463 material Substances 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 239000010937 tungsten Substances 0.000 claims description 10
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 claims description 9
- 150000004767 nitrides Chemical class 0.000 claims description 9
- 229910003468 tantalcarbide Inorganic materials 0.000 claims description 9
- 229910052721 tungsten Inorganic materials 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 7
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 3
- 239000004642 Polyimide Substances 0.000 claims description 2
- 239000003989 dielectric material Substances 0.000 claims description 2
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 claims description 2
- 229920000052 poly(p-xylylene) Polymers 0.000 claims description 2
- 229920001721 polyimide Polymers 0.000 claims description 2
- 230000000295 complement effect Effects 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 8
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 abstract 1
- 229910010271 silicon carbide Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 97
- 230000015572 biosynthetic process Effects 0.000 description 7
- 230000003993 interaction Effects 0.000 description 7
- 229920000642 polymer Polymers 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical group [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 239000010970 precious metal Substances 0.000 description 3
- -1 tungsten nitride Chemical class 0.000 description 3
- 241000238631 Hexapoda Species 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 2
- 229910000416 bismuth oxide Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000002689 soil Substances 0.000 description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000008267 milk Substances 0.000 description 1
- 210000004080 milk Anatomy 0.000 description 1
- 235000013336 milk Nutrition 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 1
- 229920002098 polyfluorene Polymers 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- XGZGDYQRJKMWNM-UHFFFAOYSA-N tantalum tungsten Chemical compound [Ta][W][Ta] XGZGDYQRJKMWNM-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
- 229910001930 tungsten oxide Inorganic materials 0.000 description 1
- 238000007704 wet chemistry method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
1278034 九、發明說明: 【發明所屬之技術領域】 本發明係Μ於-種製造電子裝置(特別是半導體裝置,但 非排除其他裝置)之方法,包括下列步.驟: 施用-半導體基板,在其一表面上備置有一導體,該 導體具有一頂部表面部分及側壁部分,其中至少該頂部表 面邵分備置有一蝕刻終止層, -施用一介電層, -在該導ft上之該介電層中蚀刻—通道,並且終止於該 蝕刻終止層,以形成該蝕刻終止層之一曝露部分, :從該導f4之至少該頂部表面部分,移除在該通道内部 的戎姓刻終止層之該曝露部分, -用一導電材料填充該通道。 【先前技術】 從US5,45i,543已知使用一介電材料(即,氮化 或一導電材料(即,鎢、氕化敍j 、、 、1 $虱化鈦或虱化鈕)作為蝕刻終止層之 方法。 使用鎢、氮化敍或氮化赵作為該蚀刻終止層之缺點在 =止=該介電層中簡該通道期間,在㈣化學與該㈣ =層,該導電材料交互作用之時刻,形成了金屬聚合 、、在该介電層中同時㈣之該等通道的深度差異愈大, 々至屬永口物形成愈顯著地發生。因此彼等金 物使電通道電阻省仆 ^ »水口 力化’所以必須更加費力地予以移除,這 疋9 <用濕式化學進行1虫刻予以更高效率地達成。但 70241-950302.doc 1278034 是’由於其多孔性(porous)且除此之外之不穩定之性質,多 =:似乎不相容於濕式嫌學,也就是說,使其低 =生力化。❹氮切或氧化_為該㈣終止層之缺點 :’與乳切或-低w料相比,氮切或氧化銘等兩種 有-相對高之介電常數,這對半導體裝置之寄生電 谷k成不利之影響。 【發明内容】 本發明《目的尤其係提供一種製造屬於[發明所屬之技 術領域]中提出之種類的半導體裝置之方法,該方法在通道 餘刻期間當抵達該姓刻終止層時抑制形成金屬聚合物,並 且減小所產生之半導體裝置的寄生電容。 、根據本發明’達成此目的在於,施用一含碳化石夕之層作 為减刻終止層。碳化矽的介電常數小於氮化矽及氧化鋁 =迅吊數’且因此提供一種含一減小之寄生電容之半導 體裝置、。另外,由於碳化石夕受到所施用之蚀刻化學的侵襲 私度低万;鎢、氮化鈦或氮化短的受侵襲程度,所以在通道 蝕刻期間金屬聚合物之形成較不顯著。 形成該導體(該導體具有一頂部表面部分及側壁部分,其 :至少該頂部表面部分備置有該钱刻終止層)之方式為:沉 知導兩層(一堆疊(其中該钱刻終止層在其頂部以及隨 後圖案㈣堆疊。但是,有利做法為,形成該導體之方式 係、·先'ϋ電層且將該導電層圖案化;以及隨後將該 、X】、、止層她用至該導體之該頂部表面部分及該等側壁部 刀在此万式中,孩導體被該餘刻終止層所囊封,這對於 70241-950302.doc 1278034 I虫刻無著點(imlanded)通道期間有所助益,無著點通 有可能脫離該導體’而非完全落在該導體之該頂部表面; 分上。位料導體之該等側壁部分的㈣刻終止層抑_ 於Μ無者點通道期間所施用之㈣化學與該導體材科之 間的交互作用,且因此抑制金屬聚合物之形成。 隨附的中請專利範圍中描述根據本發明之方法的進—步 有益之具體實施例。 < 【實施方式】 圖1緣示半導體裝置之一部分,其作用用於描述根據本發 明之万法的適當開始點。該半導體結構包括一半導體基板 1,在該半導體基板1之-表W上備置有導體3,4,5,每個導 體各具有一頂部表面部分6及侧壁部分7。請注意,雖然本 文中就三個導體及三個通道而論來描述本發明,但是應明 白,本發明也適用於僅僅一個導體及一個通道。實際上, 一半導體裝置將包括複數個此類導體及通道。雖然圖中繪 示為一個元件,但是實際上,該半導體基板〗很可能包括^ 層,彼等層係形成於(例如)一由(例如)矽所組成之半導體主 體上。基於簡單明瞭,該等層連同該主體(該等層係形成在 該主體上)被共同繪示為一單層,即,半導體基板丨。功能 上,該等導體3,4,5可能係(例如)一金屬氧化物半導體場效 電晶體(MOSFET)或一薄膜電晶體(TFT)的閘極、一雙極性 或BICMOS裝置的基極或射極,或可能係(例如)一多層式互 連結構之一金屬層的邵分。該等導體3,4,5係由位於一非貴 重金屬(base metal)部分11之頂部上的一覆蓋層8所組成,藉 70241-950302.doc 1278034 等導體M,5之該頂部表面部分6。在本 d中’孩非貴重金屬部外包含銘。但是,也 他材料,舉例而言,諸如銅或鹤。在本實例中,一由—包 頂部之—氮化敍層1G所組成的-雙層體被施 ·、、及< 盍層8。請注意,在圖案化該非貴重金屬部分^ 期間’通常施用該覆蓋層8以作為一抗反射塗層,該覆蓋層 8係及導體3,4,5的-選用部分。也可以使用其他適用的材料 (諸如鈦鎢、氮化鎢及氮化㈣來取代氮化鈇。替代做法為, 該覆蓋層8可係由-(例如)氮化歛、鈥鎮、氮化鎢及氮化赵 ^單層所組成°在此情況下’因為由於料該非眚重金屬 邵分U與㈣蓋層8之間的交互作用導致可能形成高電阻 材料’而高電阻材料對電通道電阻造成不利的影響,所以 有利的做法為’在用導電材料填充該等通道之前,先移除 該等通道内部的該覆蓋層8。 ^ 按照習知之處理來形成該等導體3,4,5。舉例而言,在該 半導體基板1之該表面2上沉積一層疊體,該層疊體係由二 鋁層、一鈦層與一氮化钽層所組成’接著圖案化該層疊體 以形成圖1之該等導體3,4,5。 且a 形成孩等導體3,4,5之後,將一蝕刻終止層12施用至該等 導體3,4,5之孩頂邵表面部分6及該等侧壁部分7,並且施用 至孩半導體基板1之未被該等導體3,4,5所覆蓋的部分。根據 本發明,該蝕刻終止層12係由碳化矽所組成,可藉由(例如) 化學氣體沉積(CVD)來沉積該層。該蝕刻終止層12之厚度可 能係(例如)在約10 nm與1〇〇 nm<範圍内。替代做法為,可 70241-950302.doc !278〇34 沉積一層疊體及隨後予以圖案化,該層疊體係由一鋁層、 —鈇層、一氮化鈥層與一碳化矽層所組成。在此情況下, 由碳化矽所組成之該蝕刻終止層12僅存在於該等導體3,4,5 之該頂部表面部分6,而該等導體3,4,5之該等側壁部分7未 被該蝕刻終止層12所覆蓋。 沉積由碳化矽所組成之該蝕刻終止層12之後,在該姓刻 終止層12上沉積一介電層13 (圖2)。該介電層13可能係由氧 化石夕所組成。但是,有利的做法為,該介電層係由一介電 常數低於氧化矽之介電常數的材料所組成,舉例而言,諸 如三氧化矽烷(hydrogen silsesquioxane)、聚對二甲苯 (Parylene)、氟化聚醯亞胺(fluorinated polyimide)或美國密 西根州Midland之Dow Chemical所銷售的「SILK0」。可藉由 習知之沉積技術(舉例而言,諸如旋轉塗佈法)來沉積此類介 電層。 /儿和之後’泫介電層1 3 (在本實例中係由三氧化石夕燒所組 成)被圖案化,以形成覆蓋該等導體3,4,5之通道14,15,16。 使用習知之微影技術來達成該圖案化,其中在該介電層13 上沉積一光阻層(圖中未繪示),該光阻層被有選擇地曝露於 輻射且顯影,以便形成一具有開口之光罩(圖中未繪示),該 等開口曝露出位於擬形成該等通道14,15,16之區域中的該 介電層13。其後,藉由移除該介電層13之未被遮罩的區域 來蚀刻該等通道14,15,1 6。 繼續蝕刻該等通道14515,16,直到已移除該等未被遮罩之 通道區域中該等導體3,4,5上的所有該介電層13。假使發生 70241-950302.doc -10- 1278034 該介電層丨3之差異厚度(典型發生於半導體裝置各處),則可 在一段廷長之時期期間使某些通道曝露於蝕刻化學,促使 一過度蚀刻發生。在此類過度触刻期間,由於介於所施用 之银刻化學與該等通道内部所曝露之導體材料之間的交互 作用’導致可能形成金屬聚合物。另夕卜,如果一通道有稍 微錯位(在此情況下,係覆蓋導體4的通道15(圖2)),則過度 蝕刻將導致沿導體4之該等侧壁部分7中之至少—側壁部分 形成一溝渠17。此類錯位之通道(也稱為無著點通道)有可能 脫離該導體,而非完全落在該導體之該頂部表面部分上。 如果因發生此類錯位之通道而使過度蝕刻劇烈,則該溝渠 17甚至可抵達該半導體基板1(其也可能係局部由導電材料 所組成)。於通道蝕刻期間侵襲此半導體基板丨也可導致形 成金屬聚合物。但是’為了抑制上文所述之問題,對由碳 化石夕所組成之該钱刻終止層12有選擇地執行通道触刻,該 蝕刻終止層U係存在於該等導體M,5之該頂部表面部分6 和該㈣壁部分7以及該半導體基板i之未被料導體3儿5 所覆盖的邵分上。因此’一過度蚀刻不曝露出該半導體基 板卜也不曝露出任何部分,不管是該導體3,4,5之頂部表面 4刀或側壁邵分。因此’抑制由於介於過度蝕刻期間所使 用之㈣化學與料導體3,4,5或料導縣板丨之材料之 間的父互作用而形成金屬聚合物。 為了達成上文所述之通道姓刻選擇性,使用一姓刻化 學’其银刻該介電層13 (在本實例中係由三氧化石夕燒所組幻 的速度快於钱刻忐难外& & 人化矽所組成之該蝕刻終止層12的速 70241-950302.doc 1278034 又、、 万;形成通道14,15,16且同時終止於該蝕刻終止層 12的適合蚀刻 子货、(舉例而言)氟碳乾式蝕刻化學。在此方 式中,曝露出今Γ莲^1;、* η Μ寺通運14,15,16内部的由碳化矽所組成之該 蝕刻終止層12。 為了接觸到孩等導體3,4,5,必、須移ρ余該等通道14,15,16 内口ρ的由&化珍所組成之該終止層η的該等曝露部分(圖 3)可:足邊等導體3,4,5之該頂部表面部分6,以及從該導體 、,等側土部分7中之至少一側壁部分(該無著點通道土 5 位万、該至y 一侧壁邵分上),移除該等通道14,1Ή内部曝 路的▲蚀5«J終止層12。但是,彳利的做法為 ,僅從該等導 3’4,5之邊頂邵表面部分6移除由碳化矽所組成之該蝕刻 :止層12,較佳的做法為,使用(舉例而言)氟碳乾式蝕刻化 學,以各向異性方式實行該移除。如B3所示,各向異性餘 刻從泫等導體3,4,5之該頂部表面部分6移除該蝕刻終止層 12<孩等曝露部分,同時僅使沿該導體4之該等側壁部分7 足孩至少一側壁部分的該蝕刻終止層12之該等曝露部分凹 進。由於橫跨半導體裝置的由碳化矽所組成之該蝕刻終止 層12的厚度(可能在大約在約1〇 11111與1〇〇 之範圍内)相對 小且相對一致,因而得以用非常受控制方式予以移除,而 不會造成介於所施用之蝕刻化學與該等導體3,4,5之材料之 間的劇烈交互作用,並且因此不會造成劇烈形成金屬聚合 物。 在本實例中,從該等導體3,4,5之該頂部表面部分6移除該 蝕刻終止層12之後,該覆蓋層8 (其係由一鈕層9與位於其頂 70241-950302.doc 12 1278034 部之-氮化鈇層1〇所組成)被留在該等通道14,15,16内部的 通當位置。但是,假使該覆蓋層8係由„(例如)氮化数、敛 鎮、氮化鎢及氮化纽之單層所組成,則因為由於介於該非 貴重金屬部分u與該覆蓋層8之間的交互作用導致可能形 成高電阻材料,而高電阻材料對電通道電阻造成不利的影 響’所以有利的做法為’在料電材料填充該等通道之前, 先從該等通道14,1 5,16内部移除該覆蓋層8。 在下一步驟中(圖4)’藉由(例如)沉積(例如)一銘層、一銅 $或-鎢層’用導電材料18填充該等通道14,15,16。請注 意’有利的做法為,該導電材料層被施用作為一雙層體, 該雙層體係由位於-當做一黏著層及/或障壁層的層體之 頂崢上的一含金屬(舉例而言,諸如鋁、銅或鎢)的層體所組 成。就這一點而言,欽可被施用作為一黏著層,以及氮化 鈦或鈥鎢作為一障壁層。當使用一過大之遮罩時,隨後可 茲刻該沉積之導電材料層。但是,在本實例中,以無遮罩 万式移除m沉積之導電材料層,直到曝露出該介電層13, 如圖4所不。例如,可以使用一市售之研磨漿,藉由(舉例 而言)化學機械研磨法(C M P)來達成以無遮罩方式移除該導 電材料層。 Μ 應明白,本發明不限於上文所述之具體實施例,而是在 本叙明範嚀内,熟悉此項技術者可進行許多變化。 【圖式簡單說明】 參考【實施方式】中詳細說明的具體實施例及附圖的圖 解說明即可明白本發明的這些及其他態樣。圖式中·· 70241-950302.doc -13-
Claims (1)
- Ι278β3^Ρ07398號專利申請案 中文申請專利範圍替換本(95年10月)歹丨〜 ,/ ::· ..... f,,. , 十、申請專利範圍: ’:“..二心上7補兑厂/ h 一種製造半導體裝置之方法,包括下列步驟: -施用-半導體基板,在其一表面上備置有一導體,該 導體具有一頂部表面部分及侧壁部分,其中至少該頂部 表面部分備置有一蝕刻終止層, -施用一介電層, -在該導體上之該介電層中蝕刻一通道,並且終止於該 蝕刻終止層,以形成該蝕刻終止層之一曝露部分, -從該導體之至少該頂部表面部分,移除在該通道内部 的該蝕刻終止層之該曝露部分, -用一導電材料填充該通道 其特徵在於,施用一含碳化矽之層作為該蝕刻終止層。 2·如請求項1之方法,其特徵在於在該半導體基板之該表面 上備置泫導體之後,將該钱刻終止層施用至該導體之該 頂部表面部分及該等側壁部分。 3·如請求項2之方法,其特徵在於該通道被蝕刻,使其不完 全降落(land on)於該導體,俾曝露出至少部分該蝕刻終止 層’該触刻終止層覆蓋該導體之該頂部表面部分及該等 側壁部分之該至少一側壁部分。 4·如請求項3之方法,其特徵在於僅從該導體之該頂部表面 部分,從該通道内部移除該蝕刻終止層。 5.如請求項2、3或4之方法,其特徵在於將該蝕刻終止層施 用至該導體之該頂邵表面部分及該等侧壁部分,並且施 用至該半導體基板之未被該導體所覆蓋的部分。 70241-951020.doc1278034 其特徵在於備置該導體, 銘、銅與鎢之群組的材料 如請求項1 ' 2、3或4之方法,其书 其至少部分係由一選自一包含鋁、 所組成。 其特徵在於備置該導體, 如請求項1、2、3或4之方法, 孩導體包含—覆蓋層,該覆蓋層提供該導tf之該頂部表 面部分。 8.如請求項7之方法,其特徵在於該覆蓋層係由一選自—包 έ氮化鈥、鈥鶴與氮化拉之群組的材料所組成。 9·如請求項1、2、3或4之方法,其特徵在於藉由沉積—介 電常數低於氧化矽之介電常數的介電材料,來施用該介 電層。 W·如請求項9之方法,其特徵在於藉由沉積一選自一包含三甲笨 (parylene)、氟化聚醯亞胺(fluorinated polyimide)之群組 的材料,來施用該介電層。 11 ·如請求項1、2、3或4之方法,其特徵在於藉由沉積一導 電層來填充該通道,該導電層包括一選自一包含鋁、銅 與鎢之群組的金屬。 70241-951020.doc
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP00201166 | 2000-03-13 | ||
EP00201928 | 2000-05-31 |
Publications (1)
Publication Number | Publication Date |
---|---|
TWI278034B true TWI278034B (en) | 2007-04-01 |
Family
ID=26072070
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW090107398A TWI278034B (en) | 2000-03-13 | 2001-03-28 | A method of manufacturing a semiconductor device |
Country Status (6)
Country | Link |
---|---|
US (1) | US6939812B2 (zh) |
EP (1) | EP1183724A1 (zh) |
JP (1) | JP2003526944A (zh) |
KR (1) | KR100772736B1 (zh) |
TW (1) | TWI278034B (zh) |
WO (1) | WO2001069672A1 (zh) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100465761B1 (ko) * | 2002-06-17 | 2005-01-13 | 삼성전자주식회사 | 탄탈륨 질화막을 포함하는 반도체 배선 구조 및 그 형성방법 |
JP2003324201A (ja) * | 2002-02-26 | 2003-11-14 | Hitachi Ltd | 薄膜トランジスタ及びそれを用いた表示装置 |
US6833300B2 (en) * | 2003-01-24 | 2004-12-21 | Texas Instruments Incorporated | Method of forming integrated circuit contacts |
DE10305365B4 (de) * | 2003-02-10 | 2005-02-10 | Infineon Technologies Ag | Verfahren und Anordnung zum Kontaktieren von Anschlüssen eines Bipolartransistors |
US7100216B2 (en) * | 2003-10-15 | 2006-09-05 | Impact Innovative Products, Llc | Garment with energy dissipating conformable padding |
US7329953B2 (en) * | 2003-10-29 | 2008-02-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure for reducing leakage currents and high contact resistance for embedded memory and method for making same |
KR100514166B1 (ko) * | 2004-01-20 | 2005-09-13 | 삼성전자주식회사 | 상보형 반도체 소자 형성방법 |
US7132299B2 (en) * | 2004-02-27 | 2006-11-07 | Micron Technology, Inc. | Method of forming a magnetic random access memory structure |
JP4447419B2 (ja) * | 2004-09-29 | 2010-04-07 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
US7655973B2 (en) | 2005-10-31 | 2010-02-02 | Micron Technology, Inc. | Recessed channel negative differential resistance-based memory cell |
KR20090048178A (ko) * | 2007-11-09 | 2009-05-13 | 주식회사 하이닉스반도체 | 반도체 소자 및 그의 제조 방법 |
KR20100112669A (ko) * | 2009-04-10 | 2010-10-20 | 삼성전자주식회사 | 반도체 소자 및 이의 제조방법 |
US9685368B2 (en) | 2015-06-26 | 2017-06-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure having an etch stop layer over conductive lines |
US11189662B2 (en) | 2018-08-13 | 2021-11-30 | Micron Technology | Memory cell stack and via formation for a memory device |
US11373695B2 (en) * | 2019-12-18 | 2022-06-28 | Micron Technology, Inc. | Memory accessing with auto-precharge |
US11430950B2 (en) | 2020-03-27 | 2022-08-30 | Micron Technology, Inc. | Low resistance via contacts in a memory device |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5451543A (en) * | 1994-04-25 | 1995-09-19 | Motorola, Inc. | Straight sidewall profile contact opening to underlying interconnect and method for making the same |
US5818071A (en) * | 1995-02-02 | 1998-10-06 | Dow Corning Corporation | Silicon carbide metal diffusion barrier layer |
US5641712A (en) * | 1995-08-07 | 1997-06-24 | Motorola, Inc. | Method and structure for reducing capacitance between interconnect lines |
TW308719B (zh) * | 1995-10-23 | 1997-06-21 | Dow Corning | |
US5880018A (en) * | 1996-10-07 | 1999-03-09 | Motorola Inc. | Method for manufacturing a low dielectric constant inter-level integrated circuit structure |
US6190966B1 (en) * | 1997-03-25 | 2001-02-20 | Vantis Corporation | Process for fabricating semiconductor memory device with high data retention including silicon nitride etch stop layer formed at high temperature with low hydrogen ion concentration |
JP3383807B2 (ja) * | 1997-05-16 | 2003-03-10 | 松下電器産業株式会社 | 半導体装置の製造方法 |
US6303523B2 (en) * | 1998-02-11 | 2001-10-16 | Applied Materials, Inc. | Plasma processes for depositing low dielectric constant films |
US20030089992A1 (en) * | 1998-10-01 | 2003-05-15 | Sudha Rathi | Silicon carbide deposition for use as a barrier layer and an etch stop |
US6713346B2 (en) * | 1999-03-01 | 2004-03-30 | Micron Technology, Inc. | Methods of forming a line of flash memory cells |
US6821571B2 (en) * | 1999-06-18 | 2004-11-23 | Applied Materials Inc. | Plasma treatment to enhance adhesion and to minimize oxidation of carbon-containing layers |
US6593632B1 (en) * | 1999-08-17 | 2003-07-15 | Advanced Micro Devices, Inc. | Interconnect methodology employing a low dielectric constant etch stop layer |
US6413854B1 (en) * | 1999-08-24 | 2002-07-02 | International Business Machines Corp. | Method to build multi level structure |
US6159845A (en) * | 1999-09-11 | 2000-12-12 | United Microelectronics Corp. | Method for manufacturing dielectric layer |
US6348379B1 (en) * | 2000-02-11 | 2002-02-19 | Advanced Micro Devices, Inc. | Method of forming self-aligned contacts using consumable spacers |
US6426249B1 (en) * | 2000-03-16 | 2002-07-30 | International Business Machines Corporation | Buried metal dual damascene plate capacitor |
US6362094B1 (en) * | 2000-08-16 | 2002-03-26 | Agere Systems Guardian Corp. | Hydrogenated silicon carbide as a liner for self-aligning contact vias |
-
2001
- 2001-03-05 EP EP01907577A patent/EP1183724A1/en not_active Ceased
- 2001-03-05 KR KR1020017014364A patent/KR100772736B1/ko not_active IP Right Cessation
- 2001-03-05 JP JP2001567035A patent/JP2003526944A/ja not_active Withdrawn
- 2001-03-05 WO PCT/EP2001/002431 patent/WO2001069672A1/en active Application Filing
- 2001-03-12 US US09/804,004 patent/US6939812B2/en not_active Expired - Lifetime
- 2001-03-28 TW TW090107398A patent/TWI278034B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP1183724A1 (en) | 2002-03-06 |
US6939812B2 (en) | 2005-09-06 |
KR100772736B1 (ko) | 2007-11-01 |
US20010046784A1 (en) | 2001-11-29 |
KR20020010650A (ko) | 2002-02-04 |
WO2001069672A1 (en) | 2001-09-20 |
JP2003526944A (ja) | 2003-09-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI278034B (en) | A method of manufacturing a semiconductor device | |
TW516108B (en) | Dual damascene process using oxide liner as dielectric barrier layer | |
US7863150B2 (en) | Method to generate airgaps with a template first scheme and a self aligned blockout mask | |
TWI260703B (en) | Multi-layer gate stack structure comprising a metal layer for a FET device, and method for fabricating the same | |
JPH10509285A (ja) | 縮小したフィーチャーサイズのためのダマスクプロセス | |
JPH11168105A (ja) | 半導体集積回路の製造方法 | |
JP2000349150A5 (zh) | ||
JP3536104B2 (ja) | 半導体装置の製造方法 | |
TWI282591B (en) | Semiconductor device including porous insulating material and manufacturing method therefor | |
TW201225183A (en) | Semiconductor devices having through-contacts and related fabrication methods | |
TWI271781B (en) | Method of making dual damascene with via etch through | |
KR100277377B1 (ko) | 콘택트홀/스루홀의형성방법 | |
JP3214475B2 (ja) | デュアルダマシン配線の形成方法 | |
IE53237B1 (en) | Low resistivity composite metallization for semiconductor devices and method therefor | |
TWI253145B (en) | Semiconductor device manufacturing method | |
TW200536041A (en) | Method of manufacturing a semiconductor device | |
US8497208B2 (en) | Semiconductor device and method for manufacturing the same | |
JP2010232676A (ja) | 信頼性向上のためのケイ化銅パッシベーション | |
TW200402837A (en) | Interconnect structure and method for forming | |
TW447083B (en) | SOI device and method of isolation thereof | |
JPH10189592A (ja) | 半導体装置の製造方法 | |
TW447021B (en) | Method for preventing photoresist residue in a dual damascene process | |
JP2872086B2 (ja) | 半導体装置の製造方法 | |
JP4379878B2 (ja) | エアーギャップを選択的に形成する方法及び当該方法により作製された装置 | |
JP3613768B2 (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |