TWI277137B - Planarizing a semiconductor structure to form replacement metal gates - Google Patents

Planarizing a semiconductor structure to form replacement metal gates Download PDF

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Publication number
TWI277137B
TWI277137B TW094124356A TW94124356A TWI277137B TW I277137 B TWI277137 B TW I277137B TW 094124356 A TW094124356 A TW 094124356A TW 94124356 A TW94124356 A TW 94124356A TW I277137 B TWI277137 B TW I277137B
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Taiwan
Prior art keywords
layer
sacrificial
metal
forming
gate electrode
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TW094124356A
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English (en)
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TW200608471A (en
Inventor
Jack Kavalieros
Justin Brask
Mark Doczy
Uday Shah
Chris Barns
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Intel Corp
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Publication of TW200608471A publication Critical patent/TW200608471A/zh
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Publication of TWI277137B publication Critical patent/TWI277137B/zh

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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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  • Insulated Gate Type Field-Effect Transistor (AREA)
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

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m7137 (1) '九、發明說明 【發明所屬之技術領域】 本發明關係於製造半導體裝置的方法，更明確地說， 關係於具有金屬閘極電極的半導體裝置。 【先前技術】 具有由二氧化矽所製成之薄閘極介電層的Μ 0 S場效 Φ 電晶體可能有不可接受的閘極洩漏電流。由某些高介電常 數（k )介電材料形成閘極介電層，而不使用二氧化矽來 形成閘極介電層可以降低閘極洩漏。於此所述，高k介電 質表示具有介電常數大於10的介電質。然而，當高k介 電膜被開始形成時，其可能具有較不完美之分子結構。爲 了修復此膜，有必要將之以相當高的溫度加以退火。 因爲此高k介電層可能與多晶矽不匹配，所以，吾人 可能想要在包含有高k金屬介電質的裝置中，使用金屬閘 H <'極電極。當使得一 CMOS裝置包含金屬閘極電極時，有必 要使得NMOS及PMOS閘極電極由不同材料作成。一替代 閘極製程可以用以由不同金屬作成閘極電極。於該製程中 ，由一對間隔層所支撐的第一多晶矽層係被選擇性地對第 二多晶矽層移除，以在間隔層間建立一溝渠。該溝渠係被 塡充以第一金屬。第二多晶矽層然後被移除，並以與第一 金屬不同之第二金屬替換。 因此，有需要其他方式，以形成替代金屬閘極電極。 (2) 1277137 【發明內容】及【實施方式】 這些圖式中所示之特性並不是想要依實際尺 出。 第1 A -1 R圖顯示當執行本發明實施例的方法 結構。開始時，高k閘極介電層170及犧牲金屬 形成在基材1〇〇上，因而產生了第1 A圖的結構 雖然未顯示出，但可以經由此流程的此一部份， • 閘極介電層（例如20至30埃的Si〇2層），並 極製程時，爲一高k介電質所替換。基材1〇〇可 主體矽或絕緣層上覆矽基材。或者，基材1〇〇可 他材料一其可以或可不結合矽一例如：鍺、銻化銦 、砷化銦、磷化銦、砷化鎵、或銻化鎵。雖然於 可以形成基材1 〇 〇的幾個材料例，但任何之可以 供半導體裝置建立於其上之材料均落在本發明之 圍中。 φ 一部份可以完成高k閘極介電層170的材 化給、氧化給矽、氧化鑭、氧化鑭鋁、氧化鉻、 、氧化鉅、氧化鈦、氧化鋇緦鈦、氧化鋇鈦、氧 氧化釔、氧化鋁、氧化鉛銃鉅、及鈮化鉛鋅。最 給、氧化鉻、氧化鈦及氧化鋁。雖然，於此只說 以形成高k閘極介電層1 7 0的少數幾個材料例， 可以由其他作用以降低閘極洩漏的材料所作成。j 有大於1 0的介電常數及在本發明之一實施例中焉 25 ° 寸比例繪 所形成之 層169被 。或者， 執行一假 在替換閘 以包含一 以包含其 、締化鉛 此只說明 作爲基礎 精神及範 斗包含：氧 氧化锆矽 化總欽、 好是氧化 明可以用 但該層也 賢170具 f由15至 -6- (3) •127713,7 高k閘極介電層1 70可以使用傳統沉積方法，例如傳 統化學氣相沉積（CVD )、低壓CVD、或物理氣相沉積（ PVD )製程所形成在基材100上。較佳地，使用一傳統原 子層CVD製程。於此一製程中，金屬氧化物前驅物（例 如金屬氯化物）及蒸汽可以以選定流率流入CVD反應器 ，該反應器然後操作於選定溫度及壓力，以在基材1 〇〇及 高k閘極介電層170間，產生自動平滑界面。該CVD反 φ 應器應操作足夠久，以形成有想要厚度的一層。在多數的 應用中，高k閘極介電層170可以少於60埃厚，例如， 在一實施例中爲約5埃至約40埃厚之間。 一犧牲金屬層169可以形成在介電層170上。該犧牲 金屬層169可以爲忍受高溫（大於450 °C)而不會與在上 方的材料反應的任意金屬。例如，該犧牲金屬層1 69可以 爲氮化鈦所形成。於一實施例中，層1 69可以由濺鍍形成 。於另一實施例中，層1 69可以由原子層沉積所形成。 φ 在高k閘極介電層170及犧牲金屬層169形成在基材 100後，犧牲層171係形成在高k閘極介電層170，如第 1B圖中所示。於此實施例中，硬罩層172然後形成在犧 牲層171上，產生如第1B圖的結構。犧牲層171可以包 含多晶矽、氮化矽、矽鍺、或鍺，並可以使用傳統沉積製 程加以沉積在犧牲金屬層上。例如，犧牲層1 7 1可以例如 於約1 0 0至約2 0 0 0埃厚之間，及於一實施例中，於約5 0 0 至約1 600埃之厚。於另一實施例中，犧牲層171可以形 成在假閘極電極上，其係在閘極更換時被隨後替換。 (4) •127713,7 硬罩層172可以包含於約100至約1 000埃厚的氮化 矽，例如，於一實施例中爲約2 0 0至約3 5 0埃厚。硬罩層 172可以形成在犧牲層171上。 犧牲層171及硬罩層172然後被作出圖案，以形成有 圖案之硬罩層130、131，及有圖案犧牲層1〇4、1〇6及 1 69，如第1 C圖所示。傳統濕式或乾式蝕刻製程可以用以 移除硬罩層172、犧牲金屬層169及犧牲層171的未保護 φ 部份。於此實施例中，在這些層被蝕刻後，高k閘極介電 層170的曝露部份174被移除。 雖然高k閘極介電層1 70的曝露部份1 74可以使用乾 式或濕式蝕刻技術加以移除，但其很難使用此等製程蝕刻 該層，而不會對鄰近結構造成負面影響。很難使用一乾式 蝕刻製程，以選擇地蝕刻高k閘極介電層1 70入下層基材 ，及濕式蝕刻技術可以等向地蝕刻高k閘極介電層1 70-以 不想要的方式，底切該上層犧牲層104、106。 φ 爲了在該層的曝露部份1 74被蝕刻時，降低高k閘極 介電層1 7 0的側向移除，高k閘極介電層1 7 0的曝露部份 1 74可以被修改以促成其選擇地移除該層的覆蓋部份！ 75 。曝露部份1 7 4可以在犧牲層1 7 1被蝕刻後，藉由將雜質 加入至該高k閘極介電層1 7 0的該部份，而加以修改。一 電漿加強化學氣相沉積（PECVD )製程可以用以加入雜質 至該高k閘極介電層170的曝露部份174。於此一 pECVD 製程中，一鹵素或鹵化氣體（或此等氣體的組合）可以在 碰撞電漿之前，被饋入反應器。該反應器應在適當條件下 -8- (5) •1277137 (例如溫度、壓力、射頻、及功率），操作足夠時間，以 修改曝露部份1 74，以確保其可以對其他材料有選擇性地 移除。於一實施例中，一低功率P E C V D製程，例如採用 低於200瓦者可以被使用。 於一實施例中，溴化氫（HBr)及氯（Cl2)氣被以適 當流率被饋入反應器中，以確保由這些氣體所產生之電漿 將以想要的方式，修改曝露部份1 74。可以施加於約5 0至 約1 〇 〇瓦間之晶圓偏壓（例如約1 ο 〇瓦）一足夠時間，以 完成曝露部份1 74的想要轉變。持續少於1分鐘，或許短 至5秒的電漿曝露可以適當地完成該轉換。 在曝露部份1 74修改後，其可以被移除。所加入之雜 質的出現使得曝露部份對覆蓋部1 75選擇地蝕刻，以產生 第1D圖之結構。於一實施例中，將曝露部份174曝露至 相當強酸，例如鹵化物爲主之酸（例如氫溴或氫氯酸）或 磷酸之酸中加以移除。當使用鹵素爲主之酸時，該酸較佳 φ包含以體積計約〇 · 5 %至約1 0 %的Η B r或H C 1，更好是體 積計約5 %。使用此酸的蝕刻製程可以發生在室溫或接近 室溫，並持續於約5及約3 0分，如果有必要也可以使用 更長的曝露。當使用磷酸時，該酸可以包含體積計約7 5 % 至約95%的Η3Ρ04。使用此酸的蝕刻製程可以例如發生在 於約140°C至約180t之間，於一實施例中，在約160°C。 當使用此酸時，曝露步驟可以持續於約3 0秒至約5分之 間，及對於20埃厚的膜持續約一分鐘。
第1D圖代表一當製作互補金屬氧化物半導體（CMOS (6) 1277137 )時，可能形成之中間結構。該結構包含如第1E圖所示 之基材100的第一部件101及第二部件102。隔離區103 將第一部件1 0 1與第二部件1 02分離。隔離區1 03可以包 含二氧化矽，但可以將電晶體的作用區分開之其他材料均 可以使用。犧牲層104被形成在第一高k閘極介電層105 上，及第二犧牲層106被形成在第二高k閘極介電層107 上。硬罩130、131係被形成在犧牲層104、106上。 p 在形成第1 D圖的結構後，間隔層可以形成在犧牲層 1 04、1 06的相對側上。當這些間隔層包含氮化矽诗，它們 可以由以下方式形成。首先，一實質均勻厚度，例如約 1 0 00埃厚的氮化矽層被沉積在整個結構上，產生如第1E 圖所示之結構。可以使用傳統沉積製程以產生該結構。 於一實施例中，氮化矽層1 3 4被直接沉稹在基材1 〇 〇 上，及犧牲層1〇4、106的相對側上，而不必在基材100 及層犧牲層104、犧牲層106上形成一緩衝氧化物層。然 肇而，於另一實施例中，此一緩衝氧化物層可以在形成層 134前被形成。同樣地，雖然未如第1E圖所示，但一第 二氧化物可以在蝕刻該層前被形成在層1 3 4上。如果使用 的話，此一氧化物可能使得後續氮化矽蝕刻步驟產生一 L 形間隔層。 氮化矽層1 3 4可以使用傳統製程加以蝕刻，以非等向 地蝕刻氮化矽，以建立第1 F圖的結構。蝕刻步驟的結果 中，犧牲層1 〇 4係爲一對側壁間隔層1 〇 8、1 0 9所支撐， 及犧牲層1 0 6係爲一對側壁間隔層1 1 〇、1 1 〇所支持。 -10- (7) 1277137 第1 F圖的結構可以然後被覆蓋以一氮化物蝕刻停止 層1 8 0，以形成第1 G圖的結構。層1 8 0可以以相同於層 1 3 4的方式加以形成。 如同傳統所完成，吾人想要執行多數遮罩及離子佈植 步驟（第1H圖），以在犧牲層104、106上，形成間隔層 108、109、110、110前，接近犧牲層104、10 6(最後作 爲裝置之源極及汲極區）建立輕摻雜區135a-l 38b。通常 φ ，源極及汲極區1 3 5 - 1 3 8可以在形成間隔層108、109、 110、111後，藉由佈植離子至基材1〇〇的部件101及102 內，加以形成，其後施加一適當的退火步驟。 用以在基材100的部件101內，形成η型源極及汲極 區之離子佈植及退火順序可以在同時摻雜犧牲層1 04以η 型。同樣地，用以形成基材100的部件102內形成Ρ型源 極及汲極區的退火順序可以摻雜犧牲層1 06以Ρ型。當以 硼摻雜犧牲層1 06時，該層應包含足夠濃度的元件，以確 II保用以移除η型犧牲層1 04的後續濕式蝕刻製程將不會移 除顯著量的Ρ型犧牲層106。 該退火將會活化先前引入源極及汲極區及頂區及進入 犧牲層1 04、1 0 6的摻雜物。於一較佳實施例中，應用了 於約超出l〇〇〇t，最佳發生在l〇8(TC溫度的快速熱退火 。除了活化該摻雜物外，此一退火可以修改高k閘極介電 層1 05、1 07的分子結構，以建立顯現有改良效能的閘極 介電層。 因爲利用犧牲金屬層1 6 9，所以可以由這些高溫步驟 -11 - (8) 1277137 ，取得較佳效能的高k閘極介電層1 70，而在高k閘極介 電層170與犧牲層171間不會有顯著反應。 在形成間隔層1 0 8、1 0 9、1 1 0、1 1 1及層1 8 0後，介 電層112可以沉積在該裝置上，產生了第1H圖的結構。 介電層112可以包含二氧化矽，或低k材料。介電層112 可以摻雜以磷、硼或其他元素，並可以使用一高密度電漿 沉積製程加以形成。藉由此階段的製程，爲矽化物區1 3 9 H 、140、141、142所覆蓋的源極及汲極區135、136、137 、1 3 8已經被形成。這些源極及汲極區可以藉由將離子佈 植入基材，然後，活化它們加以形成。或者，一磊晶成長 製程可以用以形成該源極及汲極區，這對於熟習於本技藝 者係明顯的。 介電層112係由硬罩130、131移除，硬罩隨後自有 圖案犧牲層104、106移除，產生第II圖的結構。可以應 用傳統化學機械硏磨（CMP )操作，以移除一部份的介電 φ 層112及硬罩130、131。硬罩130、131可以被移除，以 露出有圖案犧牲層104、106。當介電層112被硏磨時，硬 罩130、131可以由層104、106的表面硏磨掉，因爲它們 已經在該製程階段完成了其目的。 在形成第II圖結構後，犧牲層104被移除，以產生 溝渠1 1 3，該溝渠係定位在側壁間隔層1 08、1 09之間，而 產生了第η圖所示之結構。 於一實施例中，一在犧牲層1 06上的對層1 04有選擇 性的濕式蝕刻製程被應用以移除層104及169’而不會移 -12- (9) 1277137 除層106的顯著部份。 當犧牲層104爲摻n型時，及犧牲層1〇6爲摻p型時 (例如以硼），則此一濕式蝕刻製程可以包含將犧牲層 1 0 4曝露至一包含有氫氧化物源具有足夠溫度的水溶液中 足夠時間，以完全地移除所有的層1 〇4。氫氧化物源可以 包含在去離子水中，體積計於約2至約30%的氫氧化銨或 氫氧化四烷基銨，例如氫氧化四甲銨（ΤΜΑΗ )。 p 任何殘留犧牲層104均可以藉由將該犧牲層曝露至一 溶液加以選擇地移除，該溶液係被保持於約15°C至約9(TC 間之一溫度（例如於約40°C以下），其包含在去離子水中 ，有約2至3 0百分比體積計之氫氧化銨。於曝露步驟中 ，較佳持續至少約1分鐘，可能想要施加有於約1 OKHz至 約2 00 0 KHz間之頻率與消耗約1至約10瓦每平方公分間 之超音波能量。 於一實施例中，具有約1 3 5 0埃厚的犧牲層104可以 φ選擇地藉由將之曝露至約2 5 °C的溶液，持續3 0分鐘，該 溶液包含在去離子水中之約1 5百分比體積計的氫氧化銨 ，同時，施加約1 OOOKHz的超音波能量一消耗約5瓦每平 方公分。此一蝕刻製程應實質地移除所有η型犧牲層104 ，而不會移除有影響量之Ρ型犧牲層106。 或者，犧牲層1〇4可以藉由將之曝露至一溶液至少一 分鐘，而加以選擇地移除，該溶液被保持於約60°C至約 9 0°C間之一溫度，其包含有在去離子水中之體積計約20 至約30%的TMAH，同時，施加有超音波能量。移除具有 -13- (10) 1277137 約1 3 5 0埃厚的犧牲層1 04，藉由將之曝露至約8 0 °c的溶 液2分鐘，該溶液包含約去離子水中約25 %體積計TM A Η ，同時，施加於約1 OOOKHz的超音能量一消耗約5瓦每平 方公分，可以實質移除所有層1 〇4 ’而不會移除顯著量的 層106。第一高k閘極介電層105應足夠厚，以防止施加 以移除犧牲層1 04的蝕刻劑到達位在第一高k閘極介電層 105下的通道區。 P 該犧牲金屬層169也可以藉由選擇地蝕加以移除。於 部份實施例中，層1 69可以不被移除。於部份實施例中， 介電層1 05可以在形成替換金屬閘極前被移除。於此時， 一金屬氧化閘極介電質可以在形成替換閘極前被形成。 於所示之實施例中，η型金屬層1 1 5係直接形成在層 105上，以塡溝渠及產生第1Κ圖的結構。Ν型金屬層115 可以包含任意η型導電材料，一金屬NMOS閘極電極可以 由該材料導出。Ν型金屬層115較佳具有熱穩定性特徵， φ 使得其適用以完成用於一半導體裝置的金屬NMOS閘極電 極。 可以用以形成η型金屬層1 1 5的材料包含：鉻、锆、 鈦、鉅、鋁、及其合金，例如金屬碳化物，其包含這些元 素，即碳化鈴、碳化鉻、碳化鈦、碳化鉅及碳化鋁。Ν型 金屬層1 1 5可以使用已知PVD或CVD製程，例如傳統的 濺鍍或原子層CVD製程，形成在第一高k閘極介電層105 上。如於第1 L圖所示，除了塡入於溝渠1 1 3的區域外， 所有的η型金屬層1 1 5係被移除。層1 1 5可以經由一濕式 •14- (11) 1277137 或乾式蝕刻製程，或一適當CMP製程，由裝置的其他部 份加以移除。當層115由介電層Π2移除時，介電層112 可以作爲一蝕刻或硏磨停止層。 N型金屬層115可以作爲一金屬NMOS閘極電極，其 具有於約3.9eV至約4.2eV的功函數，並且，在於100埃 至約20 00埃間之厚度，於一實施例中，可以特別是在約 5 0 0埃至約1 6 0 0埃之間的厚度。雖然第1 J及1 K圖代表η φ 型金屬層1 1 5塡充所有溝渠1 1 3的結構，但在其他實施例 中，η型金屬層1 1 5可以只塡充部份的溝渠1 1 3，而其他 的溝渠係被以一容易硏磨的材料塡充，例如鎢、鋁、鈦或 氮化鈦。使用一較高導電率塡充金屬，以替代功函數金屬 可以改良閘極堆疊的整個導電率。於另一實施例中，作爲 功函數金屬的η型金屬層115可以是在約50至約1000埃 厚，例如至少約1〇〇埃厚。 於包含功函數金屬及溝渠塡充金屬的溝渠1 1 3中，所 φ得之金屬NMOS閘極電極可以被認爲是包含功函數金屬及 溝渠塡充金屬的組合。如果溝渠塡充金屬被沉積在一功函 數金屬上，則溝渠塡充金屬可以於沉積時覆蓋整個裝置， 形成如第1 Κ圖的結構。該溝渠塡充金屬必須然後被硏磨 ’使得只塡充該溝渠’產生如第1 L圖所不之結構。 於所示之實施例中，在溝渠1 1 3內，形成η型金屬層 1 15後，犧牲層106被移除，以產生定位在側壁間隔層 1 1 0、1 1 1間之溝渠1 5 0，產生了如第1Μ圖所示之結構。 於一較佳實施例中，層1 06被曝露至一足夠溫度（例如於 -15- (12) 1277137 約60°C-90 °C間）溶液足夠時間，同時，施加超音波能量 ’該溶液包含在去離子水中之約20至約30%間體積計之 TMAH ’以移除所有的層106，而不會顯著移除n型金屬 層 1 1 5。 或者，也可以應用一乾蝕刻製程，以選擇地移除層 106 °當犧牲層106被（例如以硼）摻雜p型時，此一乾 倉虫刻製程可以包含將犧牲層106曝露至一電漿，該電漿係 φ 由六氟化硫（SF6 )、溴化氫（HBr )、碘化氫（HI )、氯 ' Μ、及/或氨所導出。此一選擇乾式蝕刻製程可以發生 在一平行板反應器或於電子迴旋諧振蝕刻機中。 在移除犧牲層1 06後，吾人想要清除第二高k閘極介 電層107，例如藉由將該層曝露至上述過氧化氫爲主之溶 液。或者，如上所述，在以p型金屬塡充溝渠150前，一 盡層（其可以在沉積後被氧化）可以形成在第二高k介電 層1 07上。然而，於此實施例中，p型金屬層1 1 6係直接 #形成在層1 0 7上，以塡充溝渠1 5 0並產生第1 N圖的結構 。P型金屬層116可以包含任意一金屬PMOS閘極電極可 以導出的p型導體材料。P型金屬層1 1 6較佳具有熱穩定 特徵’這使得其適用以完成一用於半導體裝置的金屬 PMOS閘極電極。 可以用以形成P型金屬層1 1 6的材料包含：釕、鈀、 鉑、鈷、鎳、及導電金屬氧化物，例如氧化釕。P型金屬 層]1 6可以使用已知PVD或CVD製程，例如傳統濺鍍或 原子層CVD製程，形成在第二高k閘極介電層107上。 -16- (13) 1277137 如第1 Ο圖所示，除了塡入溝渠丨5 0中的以外，所有p型 金屬層1 1 6係被移除。層i丨6可以由裝置的其他部份，經 由濕式或乾式蝕刻製程，或其他適當的CMP作業加以移 除’以介麗層1 1 2作爲一蝕刻或硏磨停止層。 P型金屬層116可以作爲一金屬PMOS閘極電極，具 有於約4.9eV至約5.2eV間之功函數，並係在約100埃至 約2000埃厚，更好是在約500埃至約1 600埃厚。雖然第 φ ^及1〇圖顯示P型金屬層116塡充所有溝渠150的結構 ’但在其他實施例中，p型金屬層1 1 6也可以只塡充部份 之溝渠150。至於金屬NMOS閘極電極，溝渠的其他部份 可以以容易被硏磨的材料塡充，例如鎢、鋁、鈦或氮化鈦 。於此另一實施例中，作爲功函數金屬的p型金屬材料 1 16可以在約50至約1 000埃間的厚度。如同金屬NMOS 閘極電極，在包含功函數金屬及溝渠塡充金屬的溝渠150 中，所得金屬PMOS閘極電極可以被認爲包含功函數金屬 φ及溝渠塡充金屬之組合。 再者，介電層1 12可以移除，以形成如第1P圖所示 之結構。一新的氮化物蝕刻停止層1 8 1可以沉積在第1 q 圖所示。於一實施例中，該層181可以與層180相同。然 後，介電層21 4可以沉積如第1 R圖所示’以形成一內介 電層。該層2 1 4可以以層Π 2相同的材料及相同的方法形 成。 因爲氮化物蝕刻停止層1 8 0的部份於移除層1 0 4及 1 06時被移除，所以此一層可以提供有降低之應變的優點 -17- (14) 1277137 被免除。因此，藉由加入層181及層214，一應變降低層 及蝕刻停止層的優點可以被再度使用。於部份實施例中， 可以利用各種介電層2 1 4。例如’介電層2 1 4可以爲低k 介電層，例如多孔或非多孔摻碳氧化物，具有低於5的介 電常數，例如約3.2。 雖然本發明已經針對若干有限實施例加以說明，但熟 習於本技藝者可以想出各種修改及變化。吾人想到的附屬 φ 申請專利範圍涵蓋各種在本發明精神及範圍內的各修改及 變化。 【圖式簡單說明】 第1A-1R圖代表當執行本發明之一實施例時，所形成 之結構的剖面圖。 【主要元件之符號說明】
1 0 1 :第一部件 1 0 2 :第二部件 103 :隔離區 104 :犧牲層 105 :高k介電層 1 〇 6 :犧牲層 107 :高k介電層 1 〇 8 :側壁間隔層 -18- (15) 1277137
1 〇 9 :側壁間隔層 1 1 〇 :側壁間隔層 1 Π :側壁間隔層 1 12 :介電層 1 1 3 :溝渠 1 1 5 : η型金屬層 1 16 : ρ型金屬層 1 3 0 :硬罩 1 3 1 :硬罩 1 3 4 :氮化矽 1 3 5 :源極區 135a：佈植區 1 3 6 :汲極區 13 6a:佈植區 1 3 7 :源極區 137a：佈植區 1 3 8 :汲極區 13 8a：佈植區 1 3 9 :矽化物區 1 4 0 :矽化物區 1 4 1 :矽化物區 1 4 2 :矽化物區 1 5 0 :溝渠 1 6 9 :犧牲金屬層 -19- (16) (16)1277137 1 7 Ο :介電層 171 :犧牲層 1 72 :硬罩層 1 7 4 :曝露部 1 7 5 :覆蓋部 1 8 0 :蝕刻停止層 1 8 1 :蝕刻停止層 2 1 4 :介電質
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Claims (1)

1277137 - 、 咻年q月叫日修(更)正本： } L_— --—， M 十、申請專利範圍 附件2A: 第94 1 24356號專利申請案 中文申請專利範圍替換本 民國95年7月24日修正 1. 一種形成半導體結構的方法，包含： 形成一犧牲閘極結構； 1 Φ 移除該犧牲閘極結構； 以一金屬閘極電極替換該犧牲閘極結構； 以一氮化物層覆蓋該金屬閘極電極； 以一摻碳氧化物覆蓋該氮化物層。 2. 如申請專利範圍第1項所述之方法，更包含形成一 對犧牲閘極結構，以及，以該適用以形成NMOS及PMOS 電晶體的金屬閘極電極來替換該犧牲閘極結構。 3 .如申請專利範圍第1項所述之方法，其中該形成一 Φ 犧牲閘極結構的步驟包含形成具有側壁間隔層之多晶矽閘 極結構。 4.一種形成半導體結構的方法，包含： 形成一對犧牲閘極結構； 移除該犧牲閘極結構； 以金屬閘極電極，替換該犧牲閘極結構； 以氮化物層覆蓋該金屬閘極電極；及 以一摻碳氧化物覆蓋該氮化物層。 5 .如申請專利範圍第4項所述之方法，包含形成一對 1277137 f年q月叫日修(更)正替換頁 (2) 犧牲閘極結構及以適用以形成NMOS及PMOS電晶體的金 屬閘極電極，來替換該犧牲閘極結構。 6·如申請專利範圍第4項所述之方法，其中該形成一 犧牲閘極結構的步驟包含形成具有側壁間隔層之多晶矽閘 極結構。 7· —種半導體結構，包含： 一基材；
一金屬閘極電極，形成在該基材上； 一氮化物層，在該金屬閘極電極上； 一內介電層，在該氮化物層i ;及 一摻碳氧化物層，覆蓋在該氮化物層上。 8 ·如申請專利範圍第7項所述之半導體結構，其中該 內介電層具有一少於5的介電常數。 9·如申請專利範圍第7項所述之半導體結構，其中該 結構包含一對金屬閘極電極，一個電極用於NMOS電晶體 ，另一電極，用於PMOS電晶體。 1 0·如申請專利範圍第7項所述之半導體結構，其中 該氮化物層爲直接與該閘極電極接觸。 1 1 .如申請專利範圍第7項所述之半導體結構，其中 該內介電層塡充該等金屬閘極電極間之區域。 1 2·如申請專利範圍第7項所述之半導體結構，其中 該內介電層爲摻碳氧化物。
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