TWI260688B - Strained channel CMOS device with fully silicided gate electrode - Google Patents

Strained channel CMOS device with fully silicided gate electrode Download PDF

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TWI260688B
TWI260688B TW094117120A TW94117120A TWI260688B TW I260688 B TWI260688 B TW I260688B TW 094117120 A TW094117120 A TW 094117120A TW 94117120 A TW94117120 A TW 94117120A TW I260688 B TWI260688 B TW I260688B
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nmos
region
pair
pmos
gate electrode
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TW200623222A (en
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Bor-Wen Chan
Yuan-Hung Chiu
Hun-Jan Tao
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Taiwan Semiconductor Mfg
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
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    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/938—Lattice strain control or utilization

Description

1260688 九、發明說明： 【發明所屬之技術領域】 本發明大體上是有關於積體電路製程中形成MOSFET 裝置的方法，且更特別是有關於一種拉伸型通道NMOS和 PMOS裝置對，以及形成含有完全矽化閘電極之該裝置對 之方法，俾改良驅動電流。
【先前技術】 如眾所熟知，增加的裝置密度以及較高速率效能及較 低能耗係為積體電路製程中之主要驅動力。供高速數位應 用之CMOS #考s通常係透過每—個別閘的上拉時間及 下拉時間來決定。個別閘與供信號傳播於pM〇s和nm〇s 閘電極中之延遲期間有關。延遲期間亦與驅動電流（idrive) 成反比。因此，當可明白，使驅動電流最大化將提高 裝置的效能速率或優值（F0M)。 率扮演一角色，係影 已知機械應力對於電荷載子 ;右干重要參數，包含間值電_τ)偏移、驅動電流飽和 (Dsat)及⑽Off m信誘發的機械應力拉伸刪阳 裝置通道㈣效應以及對於電荷載子遷移率的效應，係受 :與聲響及光學聲子散射有關之複雜物理程序影響。理相 上，電何載子遷移率增加亦提高了驅動地電流。 - 的片二!動=受到閘極片電阻影響，，_ 蔹中降低二：ί5虎傳播中之延遲期間愈大。於先前技 電極片電阻方法包形成石夕化物於多晶石夕閉電極 5 1260688 的上方部分，以及形成導電金屬的閘電極。 此外，由於矽化物厚度（保持與裝置尺度大約固定）與 C Μ 0 S裝置（例如含有源極和沒極區的接合深度）的尺度縮 小之間之複雜關係、，漏電流（二極體漏電）之問題於較小裝置 '自界尺度下逐漸變為問題。因此，先前技藝形成矽化的閘 " 電極及汲㈣之方法逐漸造成短通道效應（包含漏電流）。 先前技藝之習用的矽化閘電極具有遭受到多晶矽空乏 • 效應（P〇ly_depletion effects)之增加的傾向。舉例來說，當 施加一閑偏壓於CMOS裝置時，於閘介電層上形成的電場 牙入閘電極中，造成電極/閘界面處之電荷載子空乏，因而 減少驅動電流且降低CMOS速率效能。 此等及其他缺點證明，於半導體積體製造技藝中需要 改良的CMOS裝置及製造彼之方法，俾獲致改良的CM〇s 裝置效率（包含增加的驅動電流）。 因此，本發明的目的就是在提供改良的CMOS裝置及 Φ 製造彼之方法，俾獲致改良的CMOS裝置效率（包含增加的 驅動電流），同時克服先前技藝的其他缺點。 _ 【發明内容】 為了達成上述及其他目的以及根據本發明的目的，如 此中所具體化且廣泛說明者，本發明係提供一種含有完全 矽化閘電極之拉伸型通道NMOS和PMOS裝置對，以及製 造彼之方法。 根據第一實施例，該方法包含一種具有完全矽化閘電 1260688 極之拉伸型通道NM0S和PMOS裝置對以及其形成方法。 該方法包含提供一半導體基板，該半導體基板包含具有個 別閘結構之NMOS和PMOS裝置區，該個別閘結構包含多 晶矽閘電極；於具有該NM〇s和pm〇S裝置區中至少_者 之通道區的任一侧上形成凹槽區；以一半導體矽合金回 填部分該凹槽區，俾施加一應變予該通道區；於該閘結構 的任一側上形成間隔片；將該多晶矽閘電極弄薄為矽^厚 度俾谷°午透過矽化厚度之完全金屬矽化作用；離子佈植 該多晶㈣電極’以調整功函數；以及透過财化厚度形 成金屬矽化物，俾形成金屬矽化物閘電極。 本發明之此等及其他實施例、態樣及特徵，於考量隨 後進v σ兒明之本發明較佳實施例的詳細說明及以下圖 式，當可更加明白。 【實施方式】 雖：' 本孓月之方法係參照例示的Nm〇s和PMOS MOSFET ☆置來闡釋，但將可理解本發明之態樣可應用於 幵v成任種MOSFET褒置，係包含雙閘或雙重閘CM〇s反 相叩/、中幵y成70全矽化的閘電極，以降低閘電極電阻且 避免多晶#乏效應。將可理解藉形成拉伸型通道區以改 良電荷載子遷私率*以實現其他優勢，其中兩方法有利地 改良：置…係包含驅動電流σ “及裝置价 月看第ΙΑ 1H SI，於一種用於形成本發明完全石夕化的 問電極CMOS結構之例示製程流程中，其係顯示於例示的 1260688 製造階段之一部分半導體晶圓的斷面示意圖。 舉例來說’請看第1A圖，其顯示一半導體基板12(可 包含石夕、拉伸型半導體、化合物半導體、多層半導體或其 組合）。舉/列來說，基板12可包含（但不限於）絕緣體矽 (SOI)、堆疊 SOI (SSOI)、堆疊絕緣 SiGe (s_SiGe〇I)、siGe〇i 及GeOI或其組σ。舉例來說’基板可包含構成個別 和PM〇S裝置區之摻雜井區12A及12B，其係經由 法(例如遮蔽法，接著為離子佈植m退火）形成。電絕緣 區視情況分開NMOS # PM0S裝置區，例如用以形成單一 閘裝置’並且較佳為藉溝渠蝕刻及回填介電氧化物（例如 TEOS氧切），接著進行平坦化仙而形成之淺溝渠絕緣 (STI)結構14。將可理解亦可形成雙或雙重閘結構。 +請再看第1A圖’閘結構係藉習知方法形成，包含閘介 电P刀16A和16B以及覆盍閑電極部分，例如裝置 閘電極18A及PMOS裝置閑電極削。於本發明之一重要 態樣中’多晶石夕閘電極係透過首先形成閘介電層，接著沉 積未摻雜多晶石夕層而形成。接著藉習用的㈣法（例如 LPCVD或PECVD)，將氮化石夕及/或氧基氮化石夕之硬遮罩層 :積於未摻雜多晶石夕層上方’之後進行微影圖案化及電漿 辅助姓刻（例如RIE)，俾形成具有剩餘覆蓋的硬遮罩層部分 2〇A和20B之個別的NM〇s和pM〇s閑結構。 閘介電部分16A和16B可由氧化石夕、氧基氮化矽、氮 、摻氮的氧切、高κ電介質或其組合所形成。高κ 介質可包含金屬氧化物、金屬矽酸鹽、金屬氮化物、過

Claims (1)

1260688 ^ :t' + 十、申請專利範圍： 1· 一種形成具有完全矽化閘電極之NM〇s和pM〇s裝 置對的方法，其包含下列步驟： 提供-半導體基板，該半導體基板包含具有個別問結 - 狀職⑽和_s裝置區，該個別問結構包含多晶石夕問 . 電極； 於具有該NMOS和PMOS裝置區中至少一者之一通道 藝 區的任一側上形成凹槽區； 以一半導體石夕合金回填部分該凹槽區，俾施加一應變 予該通道區； 於。亥閘結構的任一側上形成間隔片； 將該多晶石夕間電極弄薄為石夕化厚度，俾容許透過石夕化 厚度之完全金屬石夕化作用； 離子佈植該多晶石夕閘電極，以調整功函數；以及 透過該石夕化厚度形成金屬石夕化物，俾形成 k 閘電極。 J 2·如申請專龍㈣丨韻述之方法，其中該金屬石夕 化物閘電極的厚度小於最大間隔片寬度。 ?一如”專利範圍第丨項所述之方法，其中該間隔片 、自由氮切、氧基氮切及氧切所組成之群 16 1260688 4·如申請專利範圍第1項所述之方法，其中於形成凹 槽區步驟之确，於該閘結構的相鄰任一側形成間隔片。 / 5如中請專利範圍第！項所述之方法，於回填步驟之 後，尚包含步驟為形成一矽層於該半導體矽合金上方。 6·如申請專利範圍帛！項所述之方法，其中該凹槽區 係僅相鄰該PMOS通道區而形成。 7·如中請專利範圍第！項所述之方法，其中該半導體 石夕合金包含相當於⑨之延展晶格參數，以形成壓縮應變。 8 ·如申明專利範圍第1項所述之方法，其中該半導體 石夕合金包含矽及鍺。 9.如申請專利範圍第1項所述之方法，其中於弄薄步 驟之幻’將源極及汲極金屬矽化物形成於含有個別裝置區 之個別源極及汲極區上方。 1〇*如申請專利範圍第1項所述之方法，其中該弄薄 步驟包含以下步驟： 於該閘結構上方形成一第_ ILD層； 進仃一 CMP程序以露出含有該多晶矽閘電極的上方部 分之多晶矽；以及 17 1260688 回餘該多晶矽閘電極至該矽化厚度。 如申請專利範圍第i π"丨〜〜々忒，复由认王 步驟之二 其中於弄薄 則，將一氮化物接觸蝕刻終止層形成於個 區上方。 4叫衣罝 12·如巾請專㈣圍第㈣所述之方法，氮化物接觸 Χ、；止層係以壓縮和拉伸應力中之一所形成。 13·如申請專利範圍第1項所述之方法，其中該凹梯 區的深度為10埃至800埃。 曰 14.如申請專利範圍第1項所述之方法，其中該 區的深度為10埃至50 凹槽 埃 15·如申請專利範圍第1項所述之方法，其中該矽 厚度為100埃至1000埃。 16·如申請專利範圍第1項所述之方法，其中該矽 厚度為200埃至500埃。 17·如申請專利範圍第丨項所述之方法，其中該 NMOS多晶矽閘電極的功函數係調整為介於4 〇 二 之間。 /、 ·）eV 18 1260688 少曰*中1專利圍第1項所述之方法，其中該PMOS 夕曰曰石夕閑電極的功函數係調整為介於4·5與5.0eV之間。 19·如申請專利範圍第i項所述之方法，其中該金屬 石夕化物閘電極大體上肖冬_ 菔上包3種選自由矽化鈦、矽化鈷、矽 化鎳、矽化鎢及矽化鉑組成之群之材料。 2〇·如申請專利範圍帛！項所述之方法，其中於離子 佈植步驟月ί】’該多晶石夕閘電極包含未換雜的多晶矽。 21. 一種形成具有完全矽化閘電極之nm〇S和PMOS 裝置對的方法，其包含下列步驟： 提供一半導體基板，該半導體基板包含具有個別閘結 構之NMOS和PMOS裝置區，該個別閘結構包含未摻雜的 多晶矽閘電極； 於具有該NMOS和PMOS閘結構中至少一者之一通道 區的任一側上形成凹槽區； 以一半導體矽合金回填部分該凹槽區，俾施加—應變 予該通道區； 於該半導體矽合金上方形成一矽層； 於該閘結構的任一側上形成間隔片； 於個別的NMOS和PMOS源極及汲極區上方形成第一 金屬矽化區； 19 1260688 將該多晶㈣電極弄薄切化厚度 厚度之完全金屬矽化作用； ，俾容許透過矽化
延伸透過該矽化厚度形成第 以調整功函數；以及 二金屬矽化物區，俾形成 金屬矽化物閘電極。 22· 一種具有完全矽化閘電極之拉伸型通道NM〇s和 PMOS裝置對，其包含： 一半導體基板，係包含具有間隔片於金屬矽化物閘電 極側上之NMOS和PMOS裝置區；以及 經回填的凹槽區，係於該NMOS和PMOS區中至少一 者之一通道區的任一側上具有拉伸型半導體矽合金，俾形 成拉伸型通道區。 23·如申請專利範圍第22項所述之拉伸型通道 NMOS和PMOS裝置對，其中該間隔片係由一種選自由氮 化石夕、氧基氮化矽及氧化矽所組成之群所形成。 24·如申請專利範圍第22項所述之拉伸型通道 NMOS和PMOS裝置對，其中該金屬矽化物閘電極的厚度 小於最大間隔片寬度。 25·如申請專利範圍第22項所述之拉伸型通道 NMOS和PMOS裝置對，其中進一步包含金屬矽化物源極 20 1260688 及汲極接觸區。 26·如申清專利範圍第22項所述之拉伸型通道 NMOS和PMOS萝罟m ^丄 衣置對，其中僅該PM〇s裝置區包含一拉 伸型通道區。 27·如申請專利範圍第22項所述之拉伸型通道 NMOS和PMQS裝置對，其中該半導财合金包含相當於 石夕之延展晶格參數，以形成壓縮應變。 28·如申請專利範圍第22項所述之拉伸型通道 NMOS和PMOS裝置對，其中該半導體石夕合金包含石夕及錯。 29. 如申請專利範圍第22項所述之拉伸型通道 NMOS和PMOS裝置對，除該金屬石夕化物間電極外，尚於 個別的裝置區上包含-氮化物接觸蚀刻終止層。 30. 如申請專利範圍第29項所述之拉伸型通 NMOS和PMOS裝置對，豆由兮& ， T其中该鼠化物接觸蝕刻終止層係 以壓縮和拉伸應力中之一所形成。 曰’' 項所述之拉伸型通道 凹槽區的深度為10埃至 31.如申請專利範圍第22 NMOS和PMOS裝置對，其中該該 800 埃 〇 21 1260688 32.如申請專利範圍第22項所述之拉伸型通道 NMOS和PMOS裝置對，其中該凹槽區的深度為ι〇埃至 50 埃。 、 33. 如申請專利範圍第22項所述之拉伸型通道 NMOS和PM0S裝置對，其中該金屬矽化物閘電極具厚度 為100埃至1000埃。 34. 如申請專利範圍第22項所述之拉伸型通道 NMOS和PMOS裝置對，其中該金屬石夕化物閘電極具厚度 為200埃至500埃。 35·如申明專利範圍第22項所述之拉伸型通道 NMOS和PMOS裝置對，其中該NM〇s金屬矽化物具功函 數為介於4.0與4.5 eV之間。 36. 如申請專利範圍第22項所述之拉伸型通道 NMOS和PMOS裝置對，其中該PM〇s金屬矽化物具功函 數為介於4.5與5.0 eV之間。 37. 如申請專利範圍第22項所述之拉伸型通道 NMOS和PMOS裝置對，其中該金屬矽化物閘電極大體上 包含一種選自由矽化鈦、矽化鈷、矽化鎳、矽化鎢及矽化 22 1260688 顧組成之群之材料。
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Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100629267B1 (ko) * 2004-08-09 2006-09-29 삼성전자주식회사 듀얼-게이트 구조를 갖는 집적회로 소자 및 그 제조 방법
US20070026682A1 (en) * 2005-02-10 2007-02-01 Hochberg Michael J Method for advanced time-multiplexed etching
US7545004B2 (en) * 2005-04-12 2009-06-09 International Business Machines Corporation Method and structure for forming strained devices
US7446350B2 (en) * 2005-05-10 2008-11-04 International Business Machine Corporation Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer
US7544584B2 (en) 2006-02-16 2009-06-09 Micron Technology, Inc. Localized compressive strained semiconductor
US8294224B2 (en) * 2006-04-06 2012-10-23 Micron Technology, Inc. Devices and methods to improve carrier mobility
US7473594B2 (en) * 2006-07-25 2009-01-06 International Business Machines Corporation Raised STI structure and superdamascene technique for NMOSFET performance enhancement with embedded silicon carbon
US7485544B2 (en) * 2006-08-02 2009-02-03 Micron Technology, Inc. Strained semiconductor, devices and systems and methods of formation
US7968960B2 (en) 2006-08-18 2011-06-28 Micron Technology, Inc. Methods of forming strained semiconductor channels
US20080237743A1 (en) * 2007-03-30 2008-10-02 Texas Instruments Incorporated Integration Scheme for Dual Work Function Metal Gates
US20080116578A1 (en) * 2006-11-21 2008-05-22 Kuan-Chen Wang Initiation layer for reducing stress transition due to curing
JP5380827B2 (ja) 2006-12-11 2014-01-08 ソニー株式会社 半導体装置の製造方法
US7510940B2 (en) * 2007-02-16 2009-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating dual-gate semiconductor device
US7781288B2 (en) * 2007-02-21 2010-08-24 International Business Machines Corporation Semiconductor structure including gate electrode having laterally variable work function
US20090014807A1 (en) * 2007-07-13 2009-01-15 Chartered Semiconductor Manufacturing, Ltd. Dual stress liners for integrated circuits
US7927989B2 (en) * 2007-07-27 2011-04-19 Freescale Semiconductor, Inc. Method for forming a transistor having gate dielectric protection and structure
JP2009038103A (ja) * 2007-07-31 2009-02-19 Fujitsu Microelectronics Ltd 半導体装置の製造方法と半導体装置
US7892906B2 (en) * 2008-01-30 2011-02-22 Texas Instruments Incorporated Method for forming CMOS transistors having FUSI gate electrodes and targeted work functions
DE102008011813B4 (de) * 2008-02-29 2010-03-04 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement mit einem Metallgatestapel mit reduzierter Höhe und Verfahren zur Herstellung des Bauelements
JP5309619B2 (ja) * 2008-03-07 2013-10-09 ソニー株式会社 半導体装置およびその製造方法
US7754559B2 (en) * 2008-03-19 2010-07-13 Tower Semiconductor Ltd. Method for fabricating capacitor structures using the first contact metal
DE102008046400B4 (de) * 2008-06-30 2011-05-19 Amd Fab 36 Limited Liability Company & Co. Kg Verfahren zur Herstellung eines CMOS-Bauelements mit MOS-Transistoren mit abgesenkten Drain- und Sourcebereichen und einem Si/Ge-Material in den Drain- und Sourcebereichen des PMOS-Transistors
US7833853B2 (en) * 2008-09-12 2010-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method of defining gate structure height for semiconductor devices
US8304841B2 (en) * 2009-09-14 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate transistor, integrated circuits, systems, and fabrication methods thereof
US8357603B2 (en) * 2009-12-18 2013-01-22 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate fill and method of making
DE102009055435B4 (de) * 2009-12-31 2017-11-09 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Verstärkter Einschluss von Metallgateelektrodenstrukturen mit großem ε durch Verringern der Materialerosion einer dielektrischen Deckschicht beim Erzeugen einer verformungsinduzierenden Halbleiterlegierung
US8609495B2 (en) 2010-04-08 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid gate process for fabricating finfet device
US9263556B2 (en) 2012-06-29 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Silicide process using OD spacers
CN103914217B (zh) * 2013-01-09 2018-11-09 腾讯科技（深圳）有限公司 对象显示的方法及装置
US9059095B2 (en) * 2013-04-22 2015-06-16 International Business Machines Corporation Self-aligned borderless contacts using a photo-patternable dielectric material as a replacement contact
US9018066B2 (en) * 2013-09-30 2015-04-28 United Microelectronics Corp. Method of fabricating semiconductor device structure
US9425048B2 (en) 2013-11-06 2016-08-23 Taiwan Semiconductor Manufacturing Co., Ltd. Mechanisms for semiconductor device structure
WO2015142357A1 (en) 2014-03-21 2015-09-24 Intel Corporation Techniques for integration of ge-rich p-mos source/drain contacts
US11133226B2 (en) 2018-10-22 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. FUSI gated device formation
CN112581626B (zh) * 2021-02-23 2021-06-08 之江实验室 一种基于非参数化和多注意力机制的复杂曲面测量系统

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6258648B1 (en) * 1999-02-08 2001-07-10 Chartered Semiconductor Manufacturing Ltd. Selective salicide process by reformation of silicon nitride sidewall spacers
WO2002043151A1 (en) * 2000-11-22 2002-05-30 Hitachi, Ltd Semiconductor device and method for fabricating the same
CN1245760C (zh) * 2002-11-04 2006-03-15 台湾积体电路制造股份有限公司 Cmos元件及其制造方法
CN1301556C (zh) * 2003-03-31 2007-02-21 台湾积体电路制造股份有限公司 Cmos组件及其制造方法
JP4557508B2 (ja) * 2003-06-16 2010-10-06 パナソニック株式会社 半導体装置
US6939814B2 (en) * 2003-10-30 2005-09-06 International Business Machines Corporation Increasing carrier mobility in NFET and PFET transistors on a common wafer
US6929992B1 (en) * 2003-12-17 2005-08-16 Advanced Micro Devices, Inc. Strained silicon MOSFETs having NMOS gates with work functions for compensating NMOS threshold voltage shift

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