TWI258174B - Method for manufacturing semiconductor device and method for deciding position of semiconductor element - Google Patents

Method for manufacturing semiconductor device and method for deciding position of semiconductor element Download PDF

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Publication number
TWI258174B
TWI258174B TW094106195A TW94106195A TWI258174B TW I258174 B TWI258174 B TW I258174B TW 094106195 A TW094106195 A TW 094106195A TW 94106195 A TW94106195 A TW 94106195A TW I258174 B TWI258174 B TW I258174B
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Taiwan
Prior art keywords
substrate
alignment mark
semiconductor element
item
semiconductor
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TW094106195A
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English (en)
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TW200535944A (en
Inventor
Ryosuke Usui
Yasunori Inoue
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Sanyo Electric Co
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Publication of TW200535944A publication Critical patent/TW200535944A/zh
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Publication of TWI258174B publication Critical patent/TWI258174B/zh

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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Description

1258174 九、發明說明： 【發明所屬之技術區域】 本發明係關於使用對位標記（allgnment mark)掌握 . 半導體元件的位置之半導體裝置之製造者。 【先前技術】 在行動電話、PDA(Personai Digital Assistant，個 人數位助理）、DVC(Digital Video Camera，數位攝影機）、 ⑩DSC(Digital Still Camera，數位相機）等可攜式電子機器 迅速的高機能化當中，K吏此種製品能為市場所接受則: /員加以小型、輕量化’且為加以實現而產生對高集成之系 統LSI (Large Scale Integration，大型積體電路）之需 求。 另一方面，對於該等之電子機器亦要求更易於使用又 方便的產品，而相對於機輯使料LSI則要求高機能 化、高性能化。因此’隨著LSI晶片之高集餘，不僅其 # 1/〇(輸入/輸出）數大增，另一方面，封裳件本身之小型化 要求亦增強，故為兼顧此二者而強烈要求開發適合於半導 月丑令件之尚岔度的基板安裝之半導體封裝件。 為符合如上述之要求，而開發有各種稱為csp (chip Scale package，晶片尺寸封裝）的封裝技術。 活用晶圓製程及上述之csp技術以及裝置於實現多重 本統封汆（Multi System In Package)時，係藉由真空黏 貼法等方法’在複數的LSI上—併形成絕緣膜及銅配線。 因此，可形成無凸塊（B⑽pless)的構造，且可作高速信號 316820 5 1258174 傳送，並可使封裝件薄型化。 然而，日本專利特開2002-94247號公報所記載之技 術，以及習知多重系統封裝製造技術中，係使用晶片安裝 機（chip mounter)等使複數晶片對位，故難以提高晶片的 對位知度因此’亦難以提高依存於晶片的對位精度之配 線精度，而需要較大的配線範圍（Margin)。因而，存在有 使用LSI等半導體積體電路之多重系統封裝等之半導體裝 置中提高高集成化時之配線等的正確性之技術性旦衣 【發明内容】 一本發明係有鑑於上述情事*研創者，其目的在於
於咼集成化的半導體裝置中，π:被从A , 戒置中正確地掌握半導體元件位置 之技術。 本發明半導體裝置之製造方法係具有：在基材上設置 -有對位標記之半導體元件的步驟；以覆蓋 ::方式形成表面設有金屬膜之絕緣膜的步驟二及= '緣::金屬r一部分，而使前述對位標記露出的步: 本舍明之決定基材上的半導體元件位置之 法’係藉由檢測設於半導體元件且露出之對^方 行，對位標記係以覆蓋半導體元件表面之^^進 有金屬膜之絕緣膜之後，去㈣# ; ~成表面設 露出。 除、、巴、錢及金屬膜之—部分而 對位標記可設在半導體元件的上面， 位標記。此外，亦可藉由檢測露出之對個對 材上的半導體元件之電極。 不° ’來掌握基 316820 6 1258174 =該等之方法，以露出之半導體元件上的對位標記 ^ 的測定晶片的位置。因而，可降低配線範圍， 九成被細的配線。結果，可在高崔 ^ , 牡呵木成化之多重系統封 表甲’提供藉由正確地掌握半導 ^ „ τ ^ 手？至牛兀件的位置而提升配線 寺的正確性之半導體裝置。 【實施方式】 =_至第％圖係用以說明本實施形態之半導體襄 ^的不意圖。如第1A圖所示’在晶圓iq2上形成有 LSI/42。在此，在未設置有LSI 142之電極的區域（未圖 不）的兩個部位設置如第1B圖所示之對位標記15〇。在未 設置有電極的區域設置對位標記15〇是因為在設置有電極 的區域設置對位標記15G時，由於使對位標記⑽露出後 所施行的使用導電性材料之電鑛，電極會產生電性連接之 /又，對位標記150係藉由組合以下的材料加以積層而 形成，該材料使用例如··梦與氧化残、多結晶㈣氧化 石夕膜、氧化鶴膜與TEGS(Tetraethoxysilane，四乙基正石夕 酸鹽）、銅與S〇G(Spin-0nGlass，旋塗式玻璃成膜）膜及 I呂與SOG膜等的組合。 此外，設置對位標記150的位置只要係可從Lsi 142 表面側確認對位標記的形狀之位置即可，最好設在lsi 142 的最上層。在此，藉由對位標記150設在LSi 142的最上 層’系統封裝製造裝置將可容洲後述之雷射鑽孔 法（Laser Trepanning)所露出之對位標記15〇的位置。 316820 7 1258174 於設置此兩個部位之對位標記15〇時，各個對位標記 150之中心位置及以例如5〇//m間隔設在上之例 如接合銲墊（Bonding Pad)l52等之LSI 142的電極之中心 位置ϋ用以LSI 142之任意一點為原點的χ軸、y軸 來決定位在LSI M2上的哪個位置。又，使用角度0決定 如第2A圖所示的對位標記15〇間的傾斜。然後，先將該等 對位標記150及接合銲* 152的位置資訊記憶在後述之系 ⑩統封裝製造裝置。接著，藉由切割晶圓1〇2而分割成⑶ 142 (未圖示）。 如第3A圖所示，在經拉伸的基材14〇上設置複數個 LSI U2及被動元件144等之電路元件。在此，基材14〇 具有黏著性’可作為得將LSI 142及被動元件144固定在 表面之可伸縮的帶狀(Tape)基材。此外，被動元件144係 為例如晶片電容器、晶片電阻等。在基材⑷上設置電路 兀件之後，將設置有複數個LSI 142及被動元件144等電 路兀件之基材14G回復到未拉伸的原來的狀態。 接者’如第3β圖所示，如上述在固定複數個LSI 142 ^動元件144之狀態下’將由金屬膜m及絕緣樹脂膜 所構成之附有金屬膜的絕緣樹脂膜124配置在基材140 使附有孟屬Μ的絕緣樹脂膜j 24抵接於基材“〇，而 使LSy 142及被動兀件144嵌入絕緣樹脂膜⑵内。 口二構成絶緣膜樹脂.122之樹脂種類，將絕緣 樹脂膜1 22加埶，在直* Τ々☆ r 樹脂請厂繼λ材；ΓΛ 附有金屬膜的料
基材140。猎此，如第3C圖所示，將[SI 316820 8 1258174 142及被動元件丨44埋入絕緣樹脂膜丨&内，並將ls i } 及被動tl件144壓接於絕緣樹脂膜丨22内。 藉由上述，利用附有金屬膜的絕緣樹脂膜i24將LSI 142予以覆蓋，使亦將設於LSI 142上之對位標記覆 蓋住而無法從附有金屬膜的絕緣樹脂膜124的表面看見。
在此，金屬膜120係為例如壓延銅箔等之壓延金屬。 ^絕緣樹賴122來說，只要是可藉由加熱㈣化之材料 皆可加以採用，例如可採用環氧樹脂、BT樹脂 (^=maleimideTriazineResin)，聚二丁烯樹脂等之三聚 ?胺衍生物(Me—Derivative)、液晶聚合物、ppE樹 脂（Polyphenylene etherResin，聚苯撐醚樹脂）、聚亞醯 ㈣脂 ' 氣樹脂' 旨 '氨基雙馬來醯亞胺（pabm)等材 料，並且構成絕緣樹脂膜122之材料中的填充材之含有量 可因應材料加以適當地設定。 以附有金屬膜的絕緣樹脂膜124來說，可使用在薄膜 籲狀絕緣樹脂膜122上附著有金屬膜12〇的材料。又，附有 金屬膜的絕緣樹脂膜124 φ可藉由在金屬膜12〇上以構成 絕緣樹脂膜122之樹脂組成物進行塗布、並加以乾燥而形 ^本實施形態中’樹脂組成物係在不違反本發明目的的 範圍中，可包含硬化劑、硬化促進劑及其他成分。 此外’在B階段化之狀態下將薄膜狀絕緣樹脂膜122 配置在基材14〇上，並在其上配置金屬膜12〇而將絕緣樹 脂膜m與LSI 142及被動元件144進行熱壓接時，藉由 將金屬膜120熱壓接在絕緣樹脂膜122亦可形成附有金屬 316820 9 !258174 膜的絕緣樹脂膜124。 、一其次，如第4A圖所示，藉由使用二氧化碳氣體雷射所 ，订的雷射鑽孔法，在附有金屬膜的絕緣樹脂膜1 24之一 部份開設鑽孔154，而使LSI 142表面的兩個部位之對位 標記150露出。 不 μ另外，二氧化碳氣體雷射以第一條件及變更脈波寬度 的乐二條件之兩階段進行照射，其照射條件係例如以下所 脈波週期· 〇. 2 5 in s 輸
出：1· 0W 第一條件： 脈波寬度·· 8至1 〇 # s 短路數：1 第二條件： 脈波寬度：3至5/zs 短路數：3 藉此，形成具有直徑隨著從金屬膜12〇往絕緣膜 之方向越縮小的錐形形狀之側壁的鑽孔。 在此，對位標記150係呈例如第2B圖所示之形狀。 :’以對位標記15〇之中心為原點，取X軸與y軸，例如 =別在每10/^設置刻度。因而，在進行雷射鑽孔法時， 错由在對位標記15Q附近開孔，使對位標記i5Q之刻度露 出該刻度藉由系統封裝製造裝置所具備之光學顯^二 加以讀取，即可掌握對位標記150之中心位置。 316820 10 1258174 在此’在附有金屬膜的絕緣樹脂膜12 4之一部份使用 雷射鑽孔法所開之孔的大小太小時，難以使對位標記J 5 〇 露出，而太大時則LSI 142容易受到熱的影響，因此最好 使用從30// m至50// m之直徑，而使用直徑40# m更好。 如上所述，設在LS I 1 42上的兩個部位之對位標記1 $〇 之中心位置及接合銲墊152之中心位置的位置關係，係在
壓接附有金屬膜的絕緣樹脂膜124前即已記憶在系統封裝 製造裝置。 因此，藉由以系統封裝製造裝置所具備之光學顯微鏡 讀取對位標記150之刻度，即可掌握對位標記15〇之中心 位置，亚可藉以掌握在LSI 142上之接合銲墊152的位置。 因而’可減少在後述之LSI 142與其他電路元件間進行配 線時所需的配線範圍，而得以達成使用已完成配線微細化 之LSI 142的多重系統封裝之高集成化。 上述之位置資訊為基礎，如第4β圖所示，使用 化石反氣體雷射所進行的帝射禮 之方切鑽孔法，以露出接合銲墊152 "^ 5〇貝牙孔156。在此，貫穿孔的直徑最好使用30 長度為小：爪。此外’貫穿孔的直徑最好比銲塾電極的一邊 ^另t ’二氧化碳氣體雷射以第-條件及變更脈波宽产 的第二條件之兩階段千及-更脈波見度 不 …、、/、知、射條件係例如以下所 脈波週期：〇. 25咖 輸 出：1.⑽ 316820 11 1258174 第一條件：
至 1 0 // S 脈波寬度： 短路數： 第二條件： 3至 脈波寬度： 短路數：3 I /成具有直徑隨著從金屬膜12 0往絕緣膜12 2 。，鈿小的錐形形狀之側壁的貫穿孔156。 接著，如H ς _ 从 7 bA圖所不，猎由使用與在附有金屬膜的絕 二:4表面構成金屬請之金屬為相同的金屬進 將導電性物質158埋入貫穿孔156。在此，電鐘 的厚度設為例如15„左右。繼之，如第5B圖所示 =微影法aaserLlthc)graphy)直接描繪金屬膜斷用 电路兀件間的配線部分，將複數個lsi 142及被動元件 144等之電路元件間加以電性連接。再者，如帛5C圖所示， 在配、表°卩刀之上形成附有金屬膜的絕緣樹脂膜124。 如上述所形成之半導體模組係在附有金屬膜的絕緣樹 脂膜124之金屬膜12〇±重疊其他附有金屬膜的絕緣樹脂 朕124而形成配線層，可將複數個⑶142及被動元件⑷ 間予以電性連接’或與其他之裝置電性連接。 以上，說明了發明之較佳實施形態。然而，本發明並 不限疋於上述實施形態，本業界之業者當然可在本發明之 範圍内將上述實施形態加以改變。 例如，上述實施形態中，雖說明使用LSI 142作為半 3]6820 12 1258174 2兀件之形態，但亦可為仰_gratedCircults，積 ::路)寺其他半導體元件。此外，上述實施形態中 ::使用銅作為構成金屬膜120之材料之形態，但亦可使用 ”5以夕之金屬’或為鋁、金等導電率高的金屬。 5述’'%形恶巾’雖說明將附有金屬膜的絕緣樹 1= 接於基材14G之形態，但亦可在基材Η◦上形 八：：膜樹月曰122之後’復在絕緣膜樹脂122之表面形成 =膜12G。此外，上述實施形態中，雖說明使用第 =之形狀作為對位標記15G的形m但只要為例
=心®露出時可從對位標記15G之位置掌握接合 1干墊1 52之位置的形狀可。 D .，又’上述貫施形態中’雖說明使用10"作為對位標 ΐ對5二刻度單位之形態，但只要為藉由掌握例如5二 單二=之位置即得以掌握接合料152之位置_ 對位；實施形態中’雖說明形成LSI142之後設置 位但只要在所形成之⑶142出現對 肩-置對位二τ ’例如’亦可自LSI142之形成初期在每 二置對位“150。此外，上述實施形態中，電鑛材料 :=構成金屬謂之金屬相同的金屬，但只要為導 電性優異的金屬即可。 命 二’上述實施形態中’雖說明在LSI H2上設置兩個 ^己150之形態，但亦可設置三個或三個以上的對位 標記150。藉由如上所述’可更正確地測定接合輝塾之位 316S20 ]3 1258174 置，並可將配線更加微細化。因此，得以達成多重系統封 裝之高集成化，而可藉以提供高集成化之多重系統封裝。 又，只要可測定LSI 142及接合銲墊152之位置，如 第6A圖所不，藉由在加大接合銲墊丨6〇尺寸的同時，在表 面設置刻度，即可具有與對位標記相同的功能，藉此，僅 在LSI+142上設置一個對位標記15〇亦可，而如第6β圖所 2，藉由使複數個接合銲墊16〇具有與對位標記相同的功 能，而不在LSI 142上另外設置對位標記15〇亦可。藉由 如上所述，不僅可省略設置對位標記150的步驟以及對於 對位標記150附近進行雷射鑽孔法的步驟，並且可提供藉 由將配線微細化而得以達成高集成化之多重系統封裝:、曰 又，上述實施形態中，雖說明藉由將作為LSI 142的 =極之料銲墊152的位置f訊先記憶在线封裝製造裝 ，而羊握利用雷射鑽孔法所露出之對位標記15〇的位 置士亚藉以掌握接合銲塾152之位置資訊之形態， 错由將接合鋅墊152以外的LSI 142之電極的位置^先 4在糸統料製㈣置，而掌握所露出之對位標記15〇 之位置，亚糟以掌握接合銲墊152 的位置資訊。此外，上述•施带能Φ 之電極 Γ 述貝轭形恶中，雖說明佶用且你w 性材料作為基材14〇之形態 § 料。 便用不具伸縮性之材 【圖式簡單說明】 第1Α圖與第圖係用以說明 體裝置的示意圓。 月戶、知形恐之半導 316820 14 1258174 弟2A圖與苐2B圖係用以說明本發明實施形態之半導 體裝置的示意圖。 第3A圖至第3C圖係用以說明本發明實施形態之半導 體裝置之製私的剖視圖。 第4A圖與弟4B圖係用以說明本發明實施形態之半導 體裝置之製程的剖視圖。 弟5 A圖至弟5 C圖係用以说明本發明實施形態之半導 體裝置之製程的剖視圖。 第6 A圖及第6B圖係用以說明本發明實施形態之半導 體裝置的示意圖。 【主要元件符號說明】 102晶圓 120 金屬膜 122絕緣樹脂膜 124 附有金屬膜之絕緣樹脂 140基材 142 LSI 144被動元件 150 對位標記 152、160 接合銲墊 154 鑽孔 156貫穿孔 158 導電性物質 316820 15

Claims (1)

1258174 十、申請專利範圍： 1. 一種半導體裝置之製造方法，係具有： 驟；在基材上設置設有對位標記之半導體元科 以覆蓋前述半導體元件表面之方 有金屬膜之絕緣膜的步驟，·以及 前ΐ絕緣膜及前述金屬膜之-部分，- k子位t 5己路出的步驟。 2:申範圍*丨項之半導體 二：=半導體元件之上 中义、+、丄圍罘1項之半導體裝置之製造方^ "申= = 有複數個前述對位標^ 中，前述半導:'1項之半導體裝置之製造p 5. 如申請專利範二==個前述對位標犯; I材更具有藉—前述二^ 基材上的半導體元件之 ^對則“己’ I 6. 如申請專利範 “。位置的步驟。 中，更-有:：員之半導體裝置之製造方' 基材上：半二測前述露出之對位標記，掌揭 ?.如_ =;;:;電極位置的步驟。 中，更具有藉由:二:：導體裝置之製造方： 基材上的半導蝴剛攻露出之對位標記，掌揭 8.如申請專利範 包桎位置的步驟。 中，更具有由 > 項之半導體裝置之製造方$ 有錯由檢測前述露出之對位標記，掌擔 的步 &設 使前 •，其 •，其 ，其 ，其 前述 ，其 前述 ，，其 前述 ，其 前述 1258174 9. 基材上的半導體元件之電極位置的步驟 上的半導體元 一種位置決定方法，係用以決定在基材 件之位置者， 路出之對 其係藉由檢測設於前述半導體元件且 位標記來進行， 而前述對位標記係以覆蓋前述半導體元件表面 之方式形成表面設有金屬膜之絕緣膜之後， ^ 系巴緣膜及前述金屬膜之一部分而加以露出。/、引处 1 〇 ·如申凊專利範圍第9項之位置決定方法，其义 半‘體元件之上面具有前述對位標記。 处 SZ?專利範圍第9項之位置決定方法，其中，前述 干v肢几件具有複數個前述對位標記。 12.如申請專利範圍第1〇項之位置決定方法，其中，寸 述半導體元件具有複數個前述對位標記。 則 13^°、+申^專利範圍第9項之位置決定方法，其中，檢測 月J处路出之對位標記，而決定前述基材上的 件之電極位置。 兀* 14·、如^請專利範圍第10項之位置決定方法，其中，檢 測刚述露出之對位標記，而決定前述基材上的半導體 元件之電極位置。 旦 15·、如^請專利範圍第11項之位置決定方法，其中，檢 ^月述路出之複數個對位標記，而決定前述基材上的 半導體元件之電極位置。 16·、如2請專利範圍第12項之位置決定方法，其中，檢 f則述4出之複數個對位標記，而決定前述基材上的 半導體元件之電極位置。 316820
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