TWI255030B - Tunable ESD device for multi-power application - Google Patents

Tunable ESD device for multi-power application Download PDF

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TWI255030B
TWI255030B TW094100234A TW94100234A TWI255030B TW I255030 B TWI255030 B TW I255030B TW 094100234 A TW094100234 A TW 094100234A TW 94100234 A TW94100234 A TW 94100234A TW I255030 B TWI255030 B TW I255030B
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TW094100234A
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TW200625589A (en
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Chien-Chih Lu
Len-Yi Leu
Kuo-Shih Teng
Kun-Huan Shih
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Winbond Electronics Corp
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Priority to US11/177,568 priority patent/US20060145262A1/en
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    • H01L27/0203Particular design considerations for integrated circuits
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    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

1255030 九、發明說明: 【發明所屬之技術領域】 本發明係有關於靜電放電防護’且_是有關於—種使用於 多重電源應用之靜電放電元件。 【先前技術】 在諸如薄膜電晶體液晶顯示器(TFT_LCD)或超扭轉向列型 液晶顯示h(Stn_lcd)的高壓應用中,通f需要提供多重電源 供應以利電路運作,為了防止晶片受到靜電玫電的破壞,在晶 片設計過程中,分職不同Vee腳位與料(pad)型態置入有效 的靜電放電單元(ESD cell)便顯得十分重要。 傳統的高壓元件(以橫向雙擴散金氧半為例)之布局如第! ^所示,當其作為靜電放電防護元件時,元件尺寸需要夠大, 才能在短時間内將大量電流釋放,因此,元件布局的型能 ^車^的通道寬度,並由複數個單—元件並聯。帛2圖為沿 二】’虛線的元件截面圖,其中,每一没極區202位於 距離中,且從沒極2〇2邊緣到N型井區2〇4邊緣的 、〇必須夠大,才能避免接面崩潰電壓值過小。 而在未搭配其他靜電放電元件的情形下,高 電°單^?^半;LDMC)S)本身通f不適合作為靜電放 _*電—二: 203的接面甜、主币广 主开202對郇接之P型井 會大幅延緩靜;二:其典=為:伏特,這麼高的觸細 件的橫向雙:;放八:早應時間;第二’作為靜電放電元 擴散金氧半元件相同,因而無法防止内部電内路=== 1255030 電;淮:二板向雙擴散金氧半元件無法任意調整以保護不同 -的源聊位,為了使靜電放電單元可以及時反應,理 :的^電壓應該要比相對應的電源供應電屋準位高,且比内 =件之間極氧化層以及接面的崩潰㈣要低 過两,以防反應不及。 丁个」 使用H卜傳統上為了滿足多組電源之積體電路晶片的,便需要 :用:種不同觸發電屋值比電源供應電塵準位高 件,设計上較為複雜。 片敕具可變觸發電壓值的靜電放電元件對於確保晶 防護功能極有幫助,較佳而言,靜電放電元 值要 =¾ S壓值須比原本橫向雙擴散金氧半元件的觸發電壓 【發明内容】 本發明之實施例提供一具可變觸發電壓值 :、、’藉由調整靜電放電元件的觸發電壓值,可使觸發;壓二 2供應電堡準位高’但比内部元件之閘極氧化層以及接面的 ::電壓要低,並可提高靜電放電防護的反應速度,以 2路的Μ。本發明之實施例更可勒於多組電源之積體電路 曰曰片’使用同—種元件,但改變發生崩潰的及極區
=便可適用於多組電源線上,可以大幅簡化設計的複雜J + _本發明係揭露一種具可變觸發電壓的靜電放電元件,該靜 電件包括—基板、至少—導電型的第_井區以及—第 電型的摻雜區;第一導電型的第一井區位於該基板中,第二 型的摻雜區圍繞該第一導電型的該等第一井區;其中,該第二^ 電型的摻雜區為—金氧半電晶體的祕區,且其至該第—導電型 的第一井區之距離介於Ι 5μιη之間。 1255030 【實施方式 以下利用第3與4圖所示之橫向雙擴散金氧半電 (LDMOS)結構示意目,以詳細地說明本發明第一實施例。第3 圖為根據本發明第一實施例的橫向雙擴散金氧半電晶體結構 之布局圖。第4圖為沿著第3圖A-A,虛線之橫向雙擴散金氧丰 電晶體結構剖面圖。以下舉N型橫向雙擴散金氧半電晶 例,但並—非限定本發明結構為㈣橫向雙擴散金氧半電晶體。 如第3與4圖所示’橫向雙擴散金氧半電晶體觀包括一 ,板301、至少—p型的第—井區搬、—n型的第二井區如、 =的沒極區304、兩!>型的第三井區3〇5^n型的源極 Ρ\Γ通道區3〇7、—第一介電層则以及-閘極層_。 i的弟-井區3〇2位於該基板3〇1中;ν型的汲極區% 繞該等Ρ型的第一·弈ρ ^ ® 结 井°° 02此處所私之圍繞非為封閉式之環 而疋絲Ν型的汲極區304 1少位於該等ρ型的第—井區 3〇2之兩側;的該等源極區3〇6位於"的該等 : ^ ^該等通道區3〇7分別為^型的該等源極區现盘N 一 ^弟—井區3G3之間,且與N型的該等源極區306連接;第 兮’位於基板3〇1上,且位SN型的汲極區304盥 :亥:源極區之間,且於靠該源極區3〇6側有一第一部份,2
二3〇4側有一第二部份,該第二部份的介電層厚度里於 二弟-雜’較佳而言,該第二部份的介電層厚度大於」邱 份,閑極層3〇9位於第一介電層3〇 ( D ,至。型的第一井區3。2的距離l小到使中二 者之,面發生,較佳而言,此距離L介於Q•叫m至Η师之間。 如弟3與4圖所示,N型的第二并尸 第-井區302,此處所指之圍繞非為封閉式之環:= N型的第二井區303至少位於該等p型的第一二3二: 1255030 心八:、/开蓋了該㈣汲極區304與第一介電層308的第二 发= '二的該等第三井區3〇5位於N型的第二井區303兩側, 盥談第二了該Μ源㈣3〇6與第一介電層的第二部份 位料等2層烟的第一部份’且該等Ν型的通道區307分別 於6亥4 Ρ型的第三井區305中。 ^卜’如第4圖所示,橫向雙擴散金氧半電晶體觀可更 括-遮罩材質層31〇以及一 ρ ^ 3Η)位於該等Ρ型的第—井區3 ==貝層 以Α 一 π & ^心上,5亥遮罩材質層310可 於第-層、一般乳化層或複晶石夕層;Ρ型的佈植區311介 罩層31〇與該等Ρ型的第—井區3〇2 —製程中之光阻,使該等P型第-井區-與該N /木區之間形成一預定距離後,再加以去除。 化摻二=,!:=氧半電晶體贩更包括N型的淡 m ❹型的源/汲極下方。以上所述之實 :於明不以2指型(2_finger)橫向雙擴散金氧半電晶體為例,作 本發明不限於此,亦可以多指 J ^ 雙擴散金氧半電晶體。 tmge‘構建構橫向 3〇4時當壓脈衝(靜電放電)施於此靜電放電單冰及極 304移動型井/Ρ型井接面的空乏區邊界會往汲極 移動於疋,較小的距離L合扁、、芬杌方a ^ t山 並因此有較低的靜一曰在/及極產生較低的崩潰電壓, 可改電壓,於是藉由調整距離L的大小 觸發電塵的大小,並當元件崩潰發生時,靜電放電元2 被觸务將大量電流迅速放掉以避免損害。 t 如第5圖所示,其為星可鐵 ^ 改變N型的没極區3〇4至p 又^錢1^放電元件藉由 潰電壓_,由第5圖可r楚: 小的元件崩潰電壓;為了可以作為-個靜電放電元件,;::二 1255030 壓的最大值係由間極氧化 ]:值則击在時的崩潰電壓(二::潰所決定’而最 紅例中,靜電放電元件的觸發 γ、〜所衫’於此實 調整’為了提供有效的靜電;^可在25至5G伏特的範圍令 VDD提供適當的 “件,必須對每一供物 電放電防護而言,且2而言,對於伽,伏特的靜 發電…。伏特為^:=,伏特靜電放電… 之數據,參考下列表丨可以:二壓對距“ 電防護的準則。 〜^又计/、有夕电源供應的靜電放
鬥植口出弟圖所不,P型的第_井區302㈣型的汲極區304所 圍繞^於卩型的第-井區地兩側的㈣岐極區则仍有連 Ν型的汲極區304至ρ 型的第一井區302的距離 L(pm) ti:其處於相同的電位,當一巨幅的電壓脈衝(靜電放電)施於 此靜琶放電單元的錄3〇4時,p型的第—井區3()2兩側的N型 的沒極區304會同時反應,亦即非均勻啟動(麵_祕贿她⑽) 發生的機會大幅降低’使得靜電放電防護的性能可以改善。 本發明之另-實_提供前述橫向雙擴散金氧半電晶體之 變形,第6圖為根據本發明另一實施例的橫向雙擴散金氧半電 1255030 : = 局圖。第7圖為沿著第6圖A-A,虛線之横向雙擴 N型:第:晶體結構剖面圖。舆前一實施例主要不同之處在於 _井區303不僅包住了該汲極區3〇4與該第一介電層 共弟二部份,也同時涵蓋了 p型的第三料3 〇 $,此形式的 井區有時亦被稱為漂移區(ddft)。 件,明之貫施例提供-具可變觸發電壓值的靜電放電元 電源^雍=整靜電放電疋件的觸發電麼值’可使觸發電麼值比 以:壓準位高’但比内部元件之一層以及接面的 = 並可提高靜電放電防護的反應速度,以保護内 ^然本發明6以較佳實施例揭露如上,'然其並非用以限定 内^可Γ何,習此技藝者’在不脫離本發明之精神和範圍 附之之更動與潤飾,因此本發明之保護範圍當視後 附之申睛專利範圍所界定者為準。 【圖式簡單說明】 f 1圖為,統的橫向雙擴散金氧半電a日日體之布局。
面圖弟2圖為第1圖所示之傳統橫向雙擴散金氧半電晶體的截 結構根據本發明—實施例的橫向雙擴散金氧半電晶體 結構為沿著第3圖A_A,虛線之橫向雙擴散金氧半電晶體 沒極區至電堡的靜電放電元件藉由改㈣型的 的弟一井區的距離l所得之崩潰電壓數據圖。 體41:=據本發明另-實施例的橫向雙擴散金氧半電晶 弟7圖為沿著第6圖A-A,虛線之橫向雙擴散金氧半電 10 1255030 結構剖面圖。 【主要元件符號說明】 202〜汲極區;203〜P型井區;204〜N型井區 擴散金氧半電晶體;301〜基板;302〜P型的第一 型的第二井區;304〜N型的汲極區;305〜P型的第」 型的源極區;307〜通道區;30 8〜第一介電層;309〜 第二介電層;311〜P型的佈植區;312〜淡化摻雜區 ;300〜橫向雙 井區;303〜N 二井區;306〜N 閘極層;3 10〜
11

Claims (1)

1255030 、申請專利範圍: 電元件,包括: 1 · 一種具可變觸發電壓的靜電放 一基板,· 至少一第一導電型的第_株 —第-道十, 弟井£,位於該基板中;以及 弟一導电型的摻雜區, 區 图、v〇茨弟一導電型的該等第一井 區
放電IT申範圍第1項所述之具可變觸發電㈣靜電 兩苐_導電型的源極區;以及 ⑼^二導電型的通道區,分別位於該等第二導電型的源極 &與,及極區之間’且與該等第二導電型的源極區連接; -第-介電層’位於該基板上,且位於 該汲極區與該等源極區之間;以及 等4的
一閘極層,位於該第一介電層之上。 + 3」如中請專利範圍第2項所述之具可變觸發電壓的靜電 二電:件,其中,該第一介電層於靠該第二導電型的該等源: 區側有一第一部份,且靠該汲極區側有一第二部份,嗲 份的介電層厚度異於該第一部份。 μ 一邻 + 4.如申請專利範圍第3項所述之具可變觸發電壓的靜電 放黾元件,其中,該第一介電層的第二部份為一場氧化厣。、 5·如申請專利範圍第2項所述之具可變觸發電厣 姑带一从 J ^ % 现兒7L件,更包括: 12
1255030 一第二導電型的第二井區,其區域涵蓋了兮 核極區與該第—介電層的第二部份。μ弟一 ^型的 放電::申C第2項所述之具可變觸發電壓的靜電 第 &電型的第三井區,其區域涵蓋了兮笙笛-道+ 的源極區與該第-了5亥專弟-導電型 道[^八引, ;|电層的弟一部伤,且該等第二導電型的通 道&刀別位於該第—導電型的第三井區中。 通 放電::申範圍第2項所述之具可變觸發電壓的靜電 第_井^括—遮罩材質層,位於該第-導電型的該等 πσ上,並為該汲極區所圍繞。 放带8·=申請專利範圍第6項所述之具可變觸發電壓的靜電 更包括—第—導電型的佈植區,位於該遮罩材質層 遠弟一導電型的該等第—井區之間。 9·如巾請專利範圍第6項所述之具可變觸發㈣的靜電 石夕件1^遮罩材質層為—場氧化層、—般氧化層或複晶 4·泰ί〇.如申5月專利範圍帛2項所述之具可變觸發電塵的靜電 电兀件,更包括第二導電型的淡化推雜區,⑯於該第二導電 !的該等源極/汲極區下方。 13
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US4989057A (en) * 1988-05-26 1991-01-29 Texas Instruments Incorporated ESD protection for SOI circuits
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US6624495B2 (en) * 1997-04-23 2003-09-23 Altera Corporation Adjustable threshold isolation transistor
US6593621B2 (en) * 2001-08-23 2003-07-15 Micrel, Inc. LDMOS field effect transistor with improved ruggedness in narrow curved areas
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US7224560B2 (en) * 2003-02-13 2007-05-29 Medtronic, Inc. Destructive electrical transient protection
US6879003B1 (en) * 2004-06-18 2005-04-12 United Microelectronics Corp. Electrostatic discharge (ESD) protection MOS device and ESD circuitry thereof
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