US20140203368A1 - Electrostatic discharge protection device - Google Patents

Electrostatic discharge protection device Download PDF

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Publication number
US20140203368A1
US20140203368A1 US14/108,559 US201314108559A US2014203368A1 US 20140203368 A1 US20140203368 A1 US 20140203368A1 US 201314108559 A US201314108559 A US 201314108559A US 2014203368 A1 US2014203368 A1 US 2014203368A1
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Prior art keywords
region
protection device
metal contact
well region
esd protection
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Abandoned
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US14/108,559
Inventor
Zheng Zeng
Ching-Chung Ko
Bo-Shih Huang
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MediaTek Inc
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MediaTek Inc
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Priority to US14/108,559 priority Critical patent/US20140203368A1/en
Assigned to MEDIATEK INC. reassignment MEDIATEK INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HUANG, BO-SHIH, KO, CHING-CHUNG, ZENG, ZHENG
Priority to CN201410029613.8A priority patent/CN103943612B/en
Publication of US20140203368A1 publication Critical patent/US20140203368A1/en
Priority to US14/630,733 priority patent/US9893049B2/en
Priority to US15/469,846 priority patent/US9972673B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates

Definitions

  • An electrostatic discharge (ESD) protection device comprises a semiconductor substrate having an active region.
  • a first well region having a first conductive type is formed in the active region.
  • a first doped region having the first conductive type is formed in the first well region.
  • a first metal contact is disposed on the first doped region.
  • a second metal contact is disposed on the active region, connecting to the first well region, wherein the first metal contact and a second metal contact are separated by a poly pattern or an insulating layer pattern disposed on the first well region.
  • FIG. 2A is a top view showing a layout of one exemplary embodiment of an ESD protection device of the invention.
  • FIG. 2B is a cross section of one exemplary embodiment of an electrostatic discharge (ESD) protection device along line A-A′ of FIG. 2A .
  • ESD electrostatic discharge
  • FIG. 3A is a top view showing a layout of various exemplary embodiments of an ESD protection device of the invention.
  • FIGS. 3B and 3C are cross sections of various exemplary embodiments of an electrostatic discharge (ESD) protection device along line A-A′ of FIG. 3A .
  • ESD electrostatic discharge
  • FIGS. 4A and 5A are top views showing intermediate processes for fabricating another exemplary embodiment of an ESD protection device of the invention.
  • FIGS. 4B and 5B are cross sections of another exemplary embodiment of an electrostatic discharge (ESD) protection device along line A-A′ of FIGS. 4A and 5A .
  • ESD electrostatic discharge
  • FIGS. 6B , 7 B and 7 C are cross sections of other exemplary embodiments of an electrostatic discharge (ESD) protection device along line A-A′ of FIGS. 6A and 7A .
  • ESD electrostatic discharge
  • FIG. 1 is a circuit diagram of one exemplary embodiment of an electrostatic discharge (ESD) protection device 500 of the invention.
  • the circuit diagram as shown in FIG. 1 illustrate two electrostatic discharge (ESD) protection devices 500 used to protect an input/output (IO) device.
  • the ESD protection devices 500 are diode-typed ESD protection devices.
  • an anode of the ESD protection device 500 may be coupled to a high voltage power supply terminal VDD, and a cathode of the ESD protection device 500 may be coupled to a protected 10 device.
  • an anode of the ESD protection device 500 may be coupled to the protected 10 device, and a cathode of the ESD protection device 500 may be coupled to a low voltage power supply terminal VSS.
  • the IO device may comprise metal-oxide-semiconductor field-effect transistors (MOS transistors), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), static random access memories (SRAMs), dynamic random access memories (DRAMs), single electron transistors (SETs), diodes, capacitors, inductors or combinations thereof.
  • MOS transistors metal-oxide-semiconductor field-effect transistors
  • EPROMs erasable programmable read-only memories
  • EEPROMs electrically erasable programmable read-only memories
  • SRAMs static random access memories
  • DRAMs dynamic random access memories
  • SETs single electron transistors
  • FIG. 2A is a top view showing a layout of one exemplary embodiment of an ESD protection device 500 a of the invention.
  • FIG. 2B is a cross section of one exemplary embodiment of an electrostatic discharge (ESD) protection device along line A-A′ of FIG. 2A .
  • ESD electrostatic discharge
  • one exemplary embodiment of an ESD protection device 500 a comprises a semiconductor substrate 200 having an active region 400 .
  • the semiconductor substrate 200 may comprise silicon.
  • SiGe, bulk semiconductor, strained semiconductor, compound semiconductor, silicon on insulator (SOI), and other commonly used semiconductor substrates can be used for the semiconductor substrate 200 .
  • the semiconductor substrate 200 may have a desired conductive type by implanting p-type or n-type impurities.
  • a first well region 202 having a first conductive type is formed in the active region 400 .
  • a second well region 204 is formed in the active region 400 surrounding a boundary 205 of the first well region 202 .
  • a plurality of first doped regions 212 having the first conductive type is formed in the first well region 202 , adjacent to a surface of the semiconductor substrate 200 .
  • the first doped regions 212 are respectively separated from the boundary 205 of the first well region 202 by a plurality of shallow trench isolation (STI) features 201 .
  • STI shallow trench isolation
  • a dopant concentration of the first doped region 212 is larger than that of the first well region.
  • the ESD protection device 500 a further comprises at least two metal contacts for anode and cathode electrodes of a Schottky diode. As shown in FIGS. 2A and 2B , a first metal contact 216 is disposed on the first doped region 212 .
  • a second metal contact 214 is disposed on the active region 400 (adjacent to the surface of the semiconductor substrate 200 ), connecting to the first well region 202 without through any heavily (n+ or p+) doped region.
  • the first metal contact 214 and the second metal contact 214 are separated by a poly pattern 208 disposed on the first well region 202 .
  • the first metal contact 216 and the second metal contact 214 must be kept away from the poly pattern 208 by at least a designed distance (not shown).
  • an insulating pattern 206 is formed between the poly pattern 208 and the semiconductor substrate 200 before forming the poly pattern 208 .
  • insulating pattern 206 may collectively compose a gate structure 220 .
  • a first silicide pattern 224 and a second silicide pattern 222 may respectively cover different portions of the first well region 202 not covered by the gate structure 220 to improve conductivity between the first metal contact 216 /the second metal contact 214 and the semiconductor substrate 200 . As shown in FIGS.
  • the first silicide pattern 224 is disposed between the first metal contact 216 and the first doped region 212
  • the second silicide pattern 222 is disposed between the second metal contact 214 and the first well region 202 .
  • the ESD protection device 500 a is a Schottky diode composed by the second metal contact 214 and the first well region 222 .
  • the semiconductor substrate 200 , the first well region 202 and the first doped region 212 may have a conductive type the same as the second well region 204 .
  • the semiconductor substrate 200 serves as a p-type semiconductor substrate 200
  • the first well region 202 serves as a p-type well (PW) region 202
  • the second well region 204 also serves as a p-type well (PW) region 204
  • the first doped region 212 serves as a p-type heavily (p+) doped region.
  • the first metal contact 216 is coupled to a high voltage power supply terminal VDD and the second metal contact 214 is coupled to an input/output device (IO).
  • the semiconductor substrate 200 may have a conductive type different from the first well region 202 and the first doped region 212 .
  • the second well region 204 may have a conductive type different from the first well region 202 and the first doped region 212 .
  • the semiconductor substrate 200 serves as a p-type semiconductor substrate 200
  • the first well region 202 serves as an n-type well (NW) region 202
  • the second well region 204 serves as a p-type well (PW) region 204 .
  • the second well region 204 serves as a guard ring of the ESD protection device 500 a .
  • the first doped region 212 serves as an n-type heavily (n+) doped region.
  • the first metal contact 216 is coupled to an input/output device (IO) and the second metal contact 214 is coupled to a low voltage power supply terminal VSS.
  • the poly pattern 208 is electrically floating or optionally connected to another pin.
  • a second doped region 213 having the first conductive type is optionally formed in the first well region 202 .
  • the second metal contact 214 is disposed on the second doped region 213 .
  • the second doped region 213 may serve as a lightly doped region, and a dopant concentration of the second doped region 213 is less than that of the first doped region 212 .
  • the first doped region 212 serves as a p-type heavily (p+) doped region
  • the second doped region 213 may serve as a p-type lightly doped drain (PLDD) region.
  • PLDD lightly doped drain
  • the first doped region 212 serves as an n-type heavily (n+) doped region
  • the second doped region 213 may serve as an n-type lightly doped drain (NLDD) region.
  • FIG. 3A is a top view showing a layout of various exemplary embodiments of an ESD protection device 500 b and 500 c of the invention.
  • FIGS. 3B and 3C are cross sections of various exemplary embodiments of an electrostatic discharge (ESD) protection device along line A-A′ of FIG. 3A , showing cross sections of various exemplary embodiments of an ESD protection device 500 b and 500 c . Elements of this embodiment which are the same as those previously described in FIGS. 2A and 2B , are not repeated for brevity. As shown in FIGS.
  • ESD electrostatic discharge
  • the ESD protection device 500 b further comprises a third doped region 240 having the second conductive type opposite to the first conductive type formed in the second well region.
  • the third doped region 240 and the second doped region 212 are separated by the STI feature 201 . Further, a dopant concentration of the third doped region 240 is larger than that of the second well region 202 .
  • a third metal contact 232 is disposed on the third doped region 240 .
  • the third silicide pattern 236 is disposed between the third metal contact 232 and the third doped region 240 .
  • the semiconductor substrate 200 may have a conductive type different to the first well region 202 and the first doped region 212 .
  • the third doped region 240 may have a conductive type the same as the second well region 204 .
  • the semiconductor substrate 200 serves as a p-type semiconductor substrate 200
  • the first well region 202 serves as an n-type well (NW) region 202
  • the second well region 204 serves as a p-type well (PW) region 204 .
  • the second well region 204 serves as a guard ring 204 of the ESD protection device 500 b
  • the third doped region 240 serves as a pick-up doped region of the guard ring 204 of the ESD protection device 500 b
  • the first doped region 212 serves as an n-type heavily (n+) doped region 212
  • the third doped region 240 serves as a p-type heavily (p+) doped region 240
  • the first metal contact 216 is coupled to an input/output device (IO) and the second metal contact 214 is coupled to a low voltage power supply terminal VSS.
  • the poly pattern 208 is electrically floating or optionally connected to another pin.
  • a second doped region 213 having the first conductive type is optionally formed in the first well region 202 .
  • the second doped region 213 may serve as an n-type lightly doped drain (NLDD) region.
  • the ESD protection device 500 c further comprise a third well region 234 formed in the active region 400 , contacting a bottom 204 of the first well region 202 and a bottom 205 of the second well region 204 while the semiconductor substrate 200 has the first conductive type, which is the same as the first well region 202 and the first doped region 212 .
  • the first well region 202 may have a conductive type different to the second well region 204 .
  • the third well region 234 and the third doped region 240 may have a conductive type the same as the second well region 204 .
  • the semiconductor substrate 200 serves as a p-type semiconductor substrate 200
  • the first well region 202 serves as a p-type well (PW) region 202
  • the second well region 204 serves as an n-type well (NW) region 204
  • the third well region 234 serves as a deep n-type well (DNW) region 234
  • the second well region 204 serves as a guard ring 204 of the ESD protection device 500 c
  • the third doped region 240 serves as a pick-up doped region of the guard ring 204 of the ESD protection device 500 b .
  • the first doped region 212 serves as a p-type heavily (p+) doped region 212
  • the third doped region 240 serves as an n-type heavily (n+) doped region 240
  • the first metal contact 216 is coupled to a high voltage power supply terminal VDD and the second metal contact 214 is coupled to an input/output device (IO).
  • the poly pattern 208 is electrically floating or optionally connected to another pin.
  • a second doped region 213 having the first conductive type is optionally formed in the first well region 202 .
  • the second doped region 213 may serve as a p-type lightly doped drain (PLDD) region.
  • PLDD lightly doped drain
  • the ESD protection device 500 d is fabricated further using a resistor protection oxide (RPO) process to form at least one insulating layer pattern 230 on the first well region 202 , covering at least a portion of an upper surface 250 of the first well region 202 .
  • the insulating layer pattern 230 may serve as a mask to prevent a formation of a silicide pattern on the portion of the upper surface 250 of the first well region 202 covered by the insulating layer pattern 230 .
  • the insulating layer pattern 230 is a resistor protection oxide (RPO) pattern 230 .
  • first doped regions 212 having the first conductive type is formed in the first well region 202 , adjacent to a surface of the semiconductor substrate 200 .
  • one of the vertical sidewalls 242 of the insulating layer pattern 230 is aligned to a boundary 244 of the first doped region 212 .
  • a second doped region 213 having the first conductive type is optionally formed in the first well region 202 .
  • a silicide process is performed to form first silicide patterns 224 on other portions of the upper surface 250 of the first well region 202 without covered by the insulating layer pattern 230 .
  • the first silicide patterns 224 may respectively cover the first doped regions 212 .
  • one of the first silicide patterns 224 may cover the second doped region 213 .
  • a first metal contact 216 is formed on the first doped region 212 .
  • a second metal contact 214 is formed on the active region 400 (adjacent to the surface of the semiconductor substrate 200 ), connecting to the first well region 202 without through any heavily (n+ or p+) doped region.
  • the second metal contact 214 may be disposed on the second doped region 213 .
  • FIGS. 6A and 7A are top views showing intermediate processes for fabricating yet another exemplary embodiment of ESD protection devices 500 e and 500 f of the invention.
  • FIGS. 6B , 7 B and 7 C are cross sections of other exemplary embodiments of an electrostatic discharge (ESD) protection device along line A-A′ of FIGS. 6A and 7A , showing cross sections of various exemplary embodiments of the ESD protection devices 500 e and 500 f .
  • ESD electrostatic discharge
  • the ESD protection device 500 d is fabricated further using a resistor protection oxide (RPO) process to form at least one insulating layer pattern 230 on the first well region 202 , covering at least a portion of an upper surface 250 of the first well region 202 .
  • the insulating layer pattern 230 may serve as a mask to prevent a formation of a silicide pattern on the portion of the upper surface 250 of the first well region 202 covered by the insulating layer pattern 230 .
  • the insulating layer pattern 230 is a resistor protection oxide (RPO) pattern 230 .
  • first silicide process is performed to form first silicide patterns 224 on other portions of the upper surface 250 of the first well region 202 without covered by the insulating layer pattern 230 .
  • the first silicide patterns 224 may respectively cover the first doped regions 212 .
  • one of the first silicide patterns 224 may cover the second doped region 213 .
  • a first metal contact 216 is formed on the first doped region 212 .
  • a second metal contact 214 is formed on the active region 400 (adjacent to the surface of the semiconductor substrate 200 ), connecting to the first well region 202 without through any heavily (n+ or p+) doped region.
  • the second metal contact 214 may be disposed on the second doped region 213 .
  • the ESD protection device 500 f further comprises a third doped region 240 having the second conductive type opposite to the first conductive type formed in the second well region.
  • the third doped region 240 and the second doped region 212 are separated by the STI feature 201 .
  • a dopant concentration of the third doped region 240 is larger than that of the second well region 202 .
  • a third metal contact 232 is formed on the third doped region 240 .
  • a minimum distance between the first metal contact 216 and the second metal contact 214 of the ESD protection device 500 d - 500 f is less than a minimum distance between the first metal contact 216 and the second metal contact 214 separated by the poly pattern 208 of the ESD protection device 500 a - 500 c , because the design rule for the RPO pattern is narrower than the poly pattern.
  • Embodiments provide an electrostatic discharge (ESD) protection device.
  • the ESD protection device is composed by a Schottky diode to protect an input/output (IO) device
  • Advantages of the ESD protection device are that the ESD protection device has a lower threshold voltage (about 0.4V) at a forward turn on than the conventional gated or STI diode (about 0.7V).
  • the ESD protection device has a lower junction capacitance than the conventional gated or STI diode, resulting in a lower loading ESD protection device. Therefore, the ESD protection device is suitable to be used in a high speed circuit.
  • the ESD protection device uses a poly pattern or a RPO pattern (to replace the STI) to separate the anode and the cathode of the ESD protection device.
  • a minimum distance between the anode and the cathode of the ESD protection device can be further reduced.
  • the ESD protection device has a lower turn on resistance.

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

The invention provides an electrostatic discharge (ESD) protection device. The ESD protection device includes a semiconductor substrate having an active region. A first well region having a first conductive type is formed in the active region. A first doped region having the first conductive type is formed in the first well region. A first metal contact is disposed on the first doped region. A second metal contact is disposed on the active region, connecting to the first well region. The first metal contact and a second metal contact are separated by a poly pattern or an insulating layer pattern disposed on the first well region.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application claims the benefit of U.S. Provisional Application No. 61/755,248, filed on Jan. 22, 2013, the entirety of which is incorporated by reference herein.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to an electrostatic discharge (ESD) protection device, and in particular, to an ESD protection device formed by a Schottky diode for an input/output (I/O) device.
  • 2. Description of the Related Art
  • Requirements for electrostatic discharge (ESD) protection devices for an input/output (I/O) device are excellent ESD protection and low capacitive loading. The conventional ESD protection devices for an input/output (I/O) device include shallow trench isolation (STI) diodes or gated diodes. However, the design rule of STI limits the dimension shrinkage of the STI diodes. Also, the conventional ESD protection devices are not suited for high-speed circuits (such as RF interfaces) because the conventional STI diodes and gated diodes shunt a large part of the RF signal to supply (VDD/VSS) lines through high parasitic junction capacitance.
  • Thus, a novel ESD protection device structure for an input/output (I/O) device is desirable.
    • BRIEF SUMMARY OF INVENTION
  • An electrostatic discharge (ESD) protection device is provided. An exemplary embodiment of an ESD protection device comprises a semiconductor substrate having an active region. A first well region having a first conductive type is formed in the active region. A first doped region having the first conductive type is formed in the first well region. A first metal contact is disposed on the first doped region. A second metal contact is disposed on the active region, connecting to the first well region, wherein the first metal contact and a second metal contact are separated by a poly pattern or an insulating layer pattern disposed on the first well region.
  • A detailed description is given in the following embodiments with reference to the accompanying drawings.
    • BRIEF DESCRIPTION OF DRAWINGS
  • The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
  • FIG. 1 is a circuit diagram of one exemplary embodiment of an electrostatic discharge (ESD) protection device of the invention.
  • FIG. 2A is a top view showing a layout of one exemplary embodiment of an ESD protection device of the invention.
  • FIG. 2B is a cross section of one exemplary embodiment of an electrostatic discharge (ESD) protection device along line A-A′ of FIG. 2A.
  • FIG. 3A is a top view showing a layout of various exemplary embodiments of an ESD protection device of the invention.
  • FIGS. 3B and 3C are cross sections of various exemplary embodiments of an electrostatic discharge (ESD) protection device along line A-A′ of FIG. 3A.
  • FIGS. 4A and 5A are top views showing intermediate processes for fabricating another exemplary embodiment of an ESD protection device of the invention.
  • FIGS. 4B and 5B are cross sections of another exemplary embodiment of an electrostatic discharge (ESD) protection device along line A-A′ of FIGS. 4A and 5A.
  • FIGS. 6A and 7A are top views showing intermediate processes for fabricating yet another exemplary embodiment of an ESD protection device of the invention.
  • FIGS. 6B, 7B and 7C are cross sections of other exemplary embodiments of an electrostatic discharge (ESD) protection device along line A-A′ of FIGS. 6A and 7A.
    •  DETAILED DESCRIPTION OF INVENTION
  • The following description is a mode for carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. Wherever possible, the same reference numbers are used in the drawings and the descriptions to refer the same or like parts.
  • The present invention will be described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn to scale for illustrative purposes. The dimensions and the relative dimensions do not correspond to actual dimensions to practice the invention.
  • FIG. 1 is a circuit diagram of one exemplary embodiment of an electrostatic discharge (ESD) protection device 500 of the invention. The circuit diagram as shown in FIG. 1 illustrate two electrostatic discharge (ESD) protection devices 500 used to protect an input/output (IO) device. As shown in FIG. 1, the ESD protection devices 500 are diode-typed ESD protection devices. For IO device protection, an anode of the ESD protection device 500 may be coupled to a high voltage power supply terminal VDD, and a cathode of the ESD protection device 500 may be coupled to a protected 10 device. Alternatively, an anode of the ESD protection device 500 may be coupled to the protected 10 device, and a cathode of the ESD protection device 500 may be coupled to a low voltage power supply terminal VSS. The IO device may comprise metal-oxide-semiconductor field-effect transistors (MOS transistors), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), static random access memories (SRAMs), dynamic random access memories (DRAMs), single electron transistors (SETs), diodes, capacitors, inductors or combinations thereof.
  • FIG. 2A is a top view showing a layout of one exemplary embodiment of an ESD protection device 500 a of the invention. FIG. 2B is a cross section of one exemplary embodiment of an electrostatic discharge (ESD) protection device along line A-A′ of FIG. 2A. As shown in FIGS. 2A and 2B, one exemplary embodiment of an ESD protection device 500 a comprises a semiconductor substrate 200 having an active region 400. The semiconductor substrate 200 may comprise silicon. In alternative embodiments, SiGe, bulk semiconductor, strained semiconductor, compound semiconductor, silicon on insulator (SOI), and other commonly used semiconductor substrates can be used for the semiconductor substrate 200. The semiconductor substrate 200 may have a desired conductive type by implanting p-type or n-type impurities. A first well region 202 having a first conductive type is formed in the active region 400. A second well region 204 is formed in the active region 400 surrounding a boundary 205 of the first well region 202. A plurality of first doped regions 212 having the first conductive type is formed in the first well region 202, adjacent to a surface of the semiconductor substrate 200. In one embodiment, the first doped regions 212 are respectively separated from the boundary 205 of the first well region 202 by a plurality of shallow trench isolation (STI) features 201. In one embodiment, a dopant concentration of the first doped region 212 is larger than that of the first well region. Therefore, if the first well region 202 serves as an n-type well region 202, the first doped region 212 would serve as an n-type heavily (n+) doped region 212. Alternatively, if the first well region 202 serves as a p-type well region 202, the first doped region 212 would serve as a p-type heavily (p+) doped region 212. The ESD protection device 500 a further comprises at least two metal contacts for anode and cathode electrodes of a Schottky diode. As shown in FIGS. 2A and 2B, a first metal contact 216 is disposed on the first doped region 212. A second metal contact 214 is disposed on the active region 400 (adjacent to the surface of the semiconductor substrate 200), connecting to the first well region 202 without through any heavily (n+ or p+) doped region. In this embodiment, the first metal contact 214 and the second metal contact 214 are separated by a poly pattern 208 disposed on the first well region 202. Also, according to a design rule of standard semiconductor technology, the first metal contact 216 and the second metal contact 214 must be kept away from the poly pattern 208 by at least a designed distance (not shown). Further, according to standard semiconductor technology, an insulating pattern 206 is formed between the poly pattern 208 and the semiconductor substrate 200 before forming the poly pattern 208. Moreover, after forming the poly pattern 208, spacers 210 are disposed on two opposite sidewalls of the poly pattern 208, respectively. Therefore, the insulating pattern 206, the poly pattern 208 and the spacers 210 may collectively compose a gate structure 220. Also, according to standard semiconductor technology, a first silicide pattern 224 and a second silicide pattern 222 may respectively cover different portions of the first well region 202 not covered by the gate structure 220 to improve conductivity between the first metal contact 216/the second metal contact 214 and the semiconductor substrate 200. As shown in FIGS. 2A and 2B, the first silicide pattern 224 is disposed between the first metal contact 216 and the first doped region 212, and the second silicide pattern 222 is disposed between the second metal contact 214 and the first well region 202. In this embodiment, the ESD protection device 500 a is a Schottky diode composed by the second metal contact 214 and the first well region 222.
  • In one embodiment, the semiconductor substrate 200, the first well region 202 and the first doped region 212 may have a conductive type the same as the second well region 204. For example, the semiconductor substrate 200 serves as a p-type semiconductor substrate 200, the first well region 202 serves as a p-type well (PW) region 202, and the second well region 204 also serves as a p-type well (PW) region 204. Also, the first doped region 212 serves as a p-type heavily (p+) doped region. In this embodiment, the first metal contact 216 is coupled to a high voltage power supply terminal VDD and the second metal contact 214 is coupled to an input/output device (IO).
  • In another embodiment, the semiconductor substrate 200 may have a conductive type different from the first well region 202 and the first doped region 212. Also, the second well region 204 may have a conductive type different from the first well region 202 and the first doped region 212. For example, the semiconductor substrate 200 serves as a p-type semiconductor substrate 200, the first well region 202 serves as an n-type well (NW) region 202, and the second well region 204 serves as a p-type well (PW) region 204. The second well region 204 serves as a guard ring of the ESD protection device 500 a. Also, the first doped region 212 serves as an n-type heavily (n+) doped region. In this embodiment, the first metal contact 216 is coupled to an input/output device (IO) and the second metal contact 214 is coupled to a low voltage power supply terminal VSS. It is noted that the poly pattern 208 is electrically floating or optionally connected to another pin.
  • Additionally, in one embodiment, a second doped region 213 having the first conductive type is optionally formed in the first well region 202. Also, the second metal contact 214 is disposed on the second doped region 213. In this embodiment, the second doped region 213 may serve as a lightly doped region, and a dopant concentration of the second doped region 213 is less than that of the first doped region 212. For example, if the first doped region 212 serves as a p-type heavily (p+) doped region, the second doped region 213 may serve as a p-type lightly doped drain (PLDD) region. If the first doped region 212 serves as an n-type heavily (n+) doped region, the second doped region 213 may serve as an n-type lightly doped drain (NLDD) region.
  • FIG. 3A is a top view showing a layout of various exemplary embodiments of an ESD protection device 500 b and 500 c of the invention. FIGS. 3B and 3C are cross sections of various exemplary embodiments of an electrostatic discharge (ESD) protection device along line A-A′ of FIG. 3A, showing cross sections of various exemplary embodiments of an ESD protection device 500 b and 500 c. Elements of this embodiment which are the same as those previously described in FIGS. 2A and 2B, are not repeated for brevity. As shown in FIGS. 3A and 3B, differences between the ESD protection device 500 a and 500 b is that the ESD protection device 500 b further comprises a third doped region 240 having the second conductive type opposite to the first conductive type formed in the second well region. The third doped region 240 and the second doped region 212 are separated by the STI feature 201. Further, a dopant concentration of the third doped region 240 is larger than that of the second well region 202. A third metal contact 232 is disposed on the third doped region 240. As shown in FIGS. 3A and 3B, the third silicide pattern 236 is disposed between the third metal contact 232 and the third doped region 240.
  • In this embodiment as shown in FIGS. 3A and 3B, the semiconductor substrate 200 may have a conductive type different to the first well region 202 and the first doped region 212. Also, the third doped region 240 may have a conductive type the same as the second well region 204. For example, the semiconductor substrate 200 serves as a p-type semiconductor substrate 200, the first well region 202 serves as an n-type well (NW) region 202, and the second well region 204 serves as a p-type well (PW) region 204. The second well region 204 serves as a guard ring 204 of the ESD protection device 500 b, and the third doped region 240 serves as a pick-up doped region of the guard ring 204 of the ESD protection device 500 b. Also, the first doped region 212 serves as an n-type heavily (n+) doped region 212, and the third doped region 240 serves as a p-type heavily (p+) doped region 240. In this embodiment, the first metal contact 216 is coupled to an input/output device (IO) and the second metal contact 214 is coupled to a low voltage power supply terminal VSS. It is noted that the poly pattern 208 is electrically floating or optionally connected to another pin. Additionally, in one embodiment, a second doped region 213 having the first conductive type is optionally formed in the first well region 202. For example, the second doped region 213 may serve as an n-type lightly doped drain (NLDD) region.
  • As shown in FIGS. 3A and 3C, differences between the ESD protection device 500 b and 500 c is that the ESD protection device 500 c further comprise a third well region 234 formed in the active region 400, contacting a bottom 204 of the first well region 202 and a bottom 205 of the second well region 204 while the semiconductor substrate 200 has the first conductive type, which is the same as the first well region 202 and the first doped region 212. In this embodiment as shown in FIGS. 3A and 3C, the first well region 202 may have a conductive type different to the second well region 204. Also, the third well region 234 and the third doped region 240 may have a conductive type the same as the second well region 204. For example, the semiconductor substrate 200 serves as a p-type semiconductor substrate 200, the first well region 202 serves as a p-type well (PW) region 202, the second well region 204 serves as an n-type well (NW) region 204, and the third well region 234 serves as a deep n-type well (DNW) region 234. The second well region 204 serves as a guard ring 204 of the ESD protection device 500 c, and the third doped region 240 serves as a pick-up doped region of the guard ring 204 of the ESD protection device 500 b. Also, the first doped region 212 serves as a p-type heavily (p+) doped region 212, and the third doped region 240 serves as an n-type heavily (n+) doped region 240. In this embodiment, the first metal contact 216 is coupled to a high voltage power supply terminal VDD and the second metal contact 214 is coupled to an input/output device (IO). It is noted that the poly pattern 208 is electrically floating or optionally connected to another pin. Additionally, in one embodiment, a second doped region 213 having the first conductive type is optionally formed in the first well region 202. For example, the second doped region 213 may serve as a p-type lightly doped drain (PLDD) region.
  • FIGS. 4A and 5A are top views showing intermediate processes for fabricating another exemplary embodiment of an ESD protection device 500 d of the invention. FIGS. 4B and 5B are cross sections of one exemplary embodiment of an electrostatic discharge (ESD) protection device along line A-A′ of FIGS. 4A and 5A. Elements of this embodiment which are the same as those previously described in FIGS. 2A and 2B, are not repeated for brevity. As shown in FIGS. 4A, 4B, 5A and 5B, differences between the ESD protection devices 500 a and 500 d are that the ESD protection device 500 d is fabricated further using a resistor protection oxide (RPO) process to form at least one insulating layer pattern 230 on the first well region 202, covering at least a portion of an upper surface 250 of the first well region 202. The insulating layer pattern 230 may serve as a mask to prevent a formation of a silicide pattern on the portion of the upper surface 250 of the first well region 202 covered by the insulating layer pattern 230. In this embodiment, the insulating layer pattern 230 is a resistor protection oxide (RPO) pattern 230. Next, an implantation processes is performed to form first doped regions 212 having the first conductive type is formed in the first well region 202, adjacent to a surface of the semiconductor substrate 200. As shown in FIGS. 4A and 4B, one of the vertical sidewalls 242 of the insulating layer pattern 230 is aligned to a boundary 244 of the first doped region 212. Additionally, in one embodiment, a second doped region 213 having the first conductive type is optionally formed in the first well region 202. Next, a silicide process is performed to form first silicide patterns 224 on other portions of the upper surface 250 of the first well region 202 without covered by the insulating layer pattern 230. As shown in FIGS. 4A and 4B, the first silicide patterns 224 may respectively cover the first doped regions 212. Optionally, one of the first silicide patterns 224 may cover the second doped region 213.
  • As shown in FIGS. 5A and 5B, next, the insulating layer pattern 230 as shown in FIGS. 4A and 4B is removed. Next, a first metal contact 216 is formed on the first doped region 212. Also, a second metal contact 214 is formed on the active region 400 (adjacent to the surface of the semiconductor substrate 200), connecting to the first well region 202 without through any heavily (n+ or p+) doped region. In one embodiment with the second doped region 213 optionally formed in the first well region 202, the second metal contact 214 may be disposed on the second doped region 213. After the aforementioned processes, another exemplary embodiment of an ESD protection device 500 d is completely formed.
  • FIGS. 6A and 7A are top views showing intermediate processes for fabricating yet another exemplary embodiment of ESD protection devices 500 e and 500 f of the invention. FIGS. 6B, 7B and 7C are cross sections of other exemplary embodiments of an electrostatic discharge (ESD) protection device along line A-A′ of FIGS. 6A and 7A, showing cross sections of various exemplary embodiments of the ESD protection devices 500 e and 500 f. Elements of this embodiment which are the same as those previously described in FIGS. 3A to 3C, are not repeated for brevity. As shown in FIGS. 6A, 6B, 7A, 7B and 7C, differences between the ESD protection devices 500 b-500 c and 500 e-500 f are that the ESD protection device 500 d is fabricated further using a resistor protection oxide (RPO) process to form at least one insulating layer pattern 230 on the first well region 202, covering at least a portion of an upper surface 250 of the first well region 202. The insulating layer pattern 230 may serve as a mask to prevent a formation of a silicide pattern on the portion of the upper surface 250 of the first well region 202 covered by the insulating layer pattern 230. In this embodiment, the insulating layer pattern 230 is a resistor protection oxide (RPO) pattern 230. Next, an implantation processes is performed to form first doped regions 212 having the first conductive type is formed in the first well region 202, adjacent to a surface of the semiconductor substrate 200. Also, another implantation processes is performed to form a third doped region 240 having the second conductive type opposite to the first conductive type formed in the second well region 204. Next, a silicide process is performed to form first silicide patterns 224 on other portions of the upper surface 250 of the first well region 202 without covered by the insulating layer pattern 230. As shown in FIGS. 6A and 6B, the first silicide patterns 224 may respectively cover the first doped regions 212. Optionally, one of the first silicide patterns 224 may cover the second doped region 213.
  • As shown in FIGS. 7A, 7B and 7C, next, the insulating layer pattern 230 as shown in FIGS. 6A and 6B is removed. Next, a first metal contact 216 is formed on the first doped region 212. Also, a second metal contact 214 is formed on the active region 400 (adjacent to the surface of the semiconductor substrate 200), connecting to the first well region 202 without through any heavily (n+ or p+) doped region. In one embodiment with the second doped region 213 optionally formed in the first well region 202, the second metal contact 214 may be disposed on the second doped region 213. After the aforementioned processes, yet another exemplary embodiment of an ESD protection device 500 e/500 f is completely formed. As shown in FIGS. 7B and 7C, differences between the ESD protection device 500 e and 500 f is that the ESD protection device 500 f further comprises a third doped region 240 having the second conductive type opposite to the first conductive type formed in the second well region. The third doped region 240 and the second doped region 212 are separated by the STI feature 201. Further, a dopant concentration of the third doped region 240 is larger than that of the second well region 202. Moreover, a third metal contact 232 is formed on the third doped region 240. It is noted that a minimum distance between the first metal contact 216 and the second metal contact 214 of the ESD protection device 500 d-500 f is less than a minimum distance between the first metal contact 216 and the second metal contact 214 separated by the poly pattern 208 of the ESD protection device 500 a-500 c, because the design rule for the RPO pattern is narrower than the poly pattern.
  • Embodiments provide an electrostatic discharge (ESD) protection device. The ESD protection device is composed by a Schottky diode to protect an input/output (IO) device Advantages of the ESD protection device are that the ESD protection device has a lower threshold voltage (about 0.4V) at a forward turn on than the conventional gated or STI diode (about 0.7V). Also, the ESD protection device has a lower junction capacitance than the conventional gated or STI diode, resulting in a lower loading ESD protection device. Therefore, the ESD protection device is suitable to be used in a high speed circuit. Further, the ESD protection device uses a poly pattern or a RPO pattern (to replace the STI) to separate the anode and the cathode of the ESD protection device. A minimum distance between the anode and the cathode of the ESD protection device can be further reduced. Compared with the conventional STI diode, the ESD protection device has a lower turn on resistance.
  • While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims (19)

What is claimed is:
1. An electrostatic discharge (ESD) protection device, comprising:
a semiconductor substrate having an active region;
a first well region having a first conductive type formed in the active region;
a first doped region having the first conductive type formed in the first well region;
a first metal contact disposed on the first doped region; and
a second metal contact disposed on the active region, connecting to the first well region, wherein the first metal contact and a second metal contact are separated by a poly pattern disposed on the first well region.
2. The ESD protection device as claimed in claim 1, further comprising:
a first silicide pattern and a second silicide pattern respectively covering portions of the first well region, wherein the first silicide pattern is disposed between the first metal contact and the first doped region, and the second silicide pattern is disposed between the second metal contact and the first well region.
3. The ESD protection device as claimed in claim 2, wherein the first silicide pattern and the second silicide pattern are respectively adjacent to two opposite sides of the poly pattern.
4. The ESD protection device as claimed in claim 1, further comprising:
a second doped region having the first conductive type formed in the first well region, wherein the second metal contact is disposed on the second doped region.
5. The ESD protection device as claimed in claim 4, wherein a dopant concentration of the second doped region is less than that of the first doped region.
6. The ESD protection device as claimed in claim 1, wherein a dopant concentration of the first doped region is larger than that of the first well region.
7. The ESD protection device as claimed in claim 1, further comprising:
a second well region having a second conductive type opposite to the first conductive type formed in the active region surrounding a boundary of the first well region;
a third doped region having the second conductive type formed in the second well region, wherein a dopant concentration of the third doped region is larger than that of the second well region; and
a third metal contact disposed on the third doped region.
8. The ESD protection device as claimed in claim 7, wherein the third doped region and the second doped region are separated by an isolation pattern.
9. The ESD protection device as claimed in claim 7, further comprising a third well region formed in the active region, contacting bottoms of the first and second well regions when the semiconductor substrate has the first conductive type.
10. The ESD protection device as claimed in claim 7, wherein the semiconductor substrate has the second conductive type.
11. The ESD protection device as claimed in claim 7, wherein a dopant concentration of the second doped region is larger than that of the second well region.
12. The ESD protection device as claimed in claim 1, further comprising:
a second well region having the first conductive type formed in the active region surrounding a boundary of the first well region.
13. The ESD protection device as claimed in claim 1, wherein the first conductive type is n-type and the semiconductor substrate is p-type, and the first metal contact is coupled to an input/output device and the second metal contact is coupled to a high voltage power supply terminal or the first metal contact is coupled to a low voltage power supply terminal and the second metal contact is coupled to an input/output device.
14. The ESD protection device as claimed in claim 1, wherein the first conductive type is p-type and the semiconductor substrate is p-type, and the first metal contact is coupled to a high voltage power supply terminal and the second metal contact is coupled to an input/output device or the first metal contact is coupled to an input/output device and the second metal contact is coupled to a low voltage power supply terminal.
15. The ESD protection device as claimed in claim 1, further comprising spacers disposed on two opposite sidewalls of the poly pattern, respectively.
16. The ESD protection device as claimed in claim 1, wherein the poly pattern or the insulating layer pattern is electrically floating.
17. The ESD protection device as claimed in claim 1, wherein the second metal contact and the first well region are formed as a Schottky diode.
18. An electrostatic discharge (ESD) protection device, comprising:
a semiconductor substrate having an active region;
a first well region having a first conductive type formed in the active region;
a first doped region having the first conductive type formed in the first well region;
a first metal contact disposed on the first doped region; and
a second metal contact disposed on the active region, connecting to the first well region, wherein at least a portion of an upper surface of the first well region does not have silicide.
19. An electrostatic discharge (ESD) protection device, comprising:
a semiconductor substrate having an active region;
a first well region having a first conductive type formed in the active region;
a first doped region having the first conductive type formed in the first well region;
a first metal contact disposed on the first doped region; and
a second metal contact disposed on the active region, connecting to the first well region, wherein no doped region is formed between the second metal contact and the first well region.
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