CN103943612B - Electrostatic discharge protective equipment - Google Patents
Electrostatic discharge protective equipment Download PDFInfo
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- CN103943612B CN103943612B CN201410029613.8A CN201410029613A CN103943612B CN 103943612 B CN103943612 B CN 103943612B CN 201410029613 A CN201410029613 A CN 201410029613A CN 103943612 B CN103943612 B CN 103943612B
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Abstract
The present invention provides a kind of electrostatic discharge protective equipment, and it includes：There is the Semiconductor substrate of active area；It is formed at first well region with the first conduction type of this active area；It is formed at first doped region with this first conduction type of this first well region；It is arranged in the first hard contact of this first doped region；It is formed at second doped region with the first conduction type of this first well region；And it is arranged in the second hard contact of this active area, it is connected to this first well region, wherein, the poly pattern that this first hard contact and this second hard contact are disposed in the first well region separates, this second hard contact is arranged on the second doped region, the doping content of this second doped region is less than the doping content of this first doped region, and the doping content of this first doped region is more than the doping content of this first well region.This electrostatic discharge protective equipment can use in high speed circuit.
Description
Technical field
The present invention relates to a kind of static discharge (electrostatic discharge, ESD) protection device, particularly to
The electrostatic discharge protective equipment being formed by a Schottky diode (Schottky diode), for input/output (I/O)
Device.
Background technology
Static discharge (ESD) protection device for input/output (I/O) device is outstanding ESD protection and has
Low capacitive load.The Esd protection device being traditionally used for input/output (I/O) device includes shallow trench isolation (shallow
Trench isolation, STI) diode OR gate control diode (gated diodes).However, the design rule of STI limits
The dimensional contraction of STI diode.And, traditional Esd protection device is not suitable for high speed circuit (as radio frequency interface), because
It is that traditional STI diode distributes most RF signal with gate diode, by high parasitic junction capacitance (parasitic
Junction capacitance) arrive power supply (VDD/VSS) line.
Accordingly, it would be desirable to a kind of new E SD protection device structure for input/output (I/O) device.
Content of the invention
The present invention discloses a kind of new electrostatic discharge protective equipment.
One embodiment of the invention provides a kind of electrostatic discharge protective equipment, including：There is the Semiconductor substrate of active area；Shape
Become first well region with the first conduction type in this active area；Be formed at this first well region has this first conduction type
The first doped region；It is arranged in the first hard contact of this first doped region；Be formed at this first well region has the first conduction
Second doped region of type；And it is arranged in the second hard contact of this active area, it is connected to this first well region, wherein, this
The poly pattern that one hard contact and this second hard contact are disposed in the first well region separates, and this second hard contact is set
Put in the second doped region, the doping content of this second doped region is less than the doping content of this first doped region, this first doped region
Doping content be more than this first well region doping content.
Another embodiment of the present invention provides a kind of electrostatic discharge protective equipment, including：There is the Semiconductor substrate of active area；
It is formed at first well region with the first conduction type of this active area；Be formed at this first well region has this first conductive-type
First doped region of type；It is arranged in the first hard contact of this first doped region；And it is arranged in the second metal of this active area
Contact, connects this first well region, wherein, this first well region upper surface positioned at this first hard contact and this second hard contact
Between at least a portion there is no silicide.
Further embodiment of this invention provides a kind of electrostatic discharge protective equipment, including：There is the Semiconductor substrate of active area；
It is formed at first well region with the first conduction type of this active area；Be formed at this first well region has this first conductive-type
First doped region of type；It is arranged in the first hard contact of this first doped region；And it is arranged in the second metal of this active area
Contact, connects this first well region, wherein, does not have doped region to be formed between this second hard contact and this first well region.
The above-mentioned electrostatic discharge protective equipment that the present invention provides is suitable for using in high speed circuit.
Brief description
Fig. 1 is the circuit diagram of the exemplary embodiment of Esd protection device that the present invention provides；
Fig. 2A is the top view of the exemplary embodiment layout of Esd protection device that the present invention provides；
Fig. 2 B is the cross section of the exemplary embodiment of the Esd protection device of A-A ' line along Fig. 2A that the present invention provides；
Fig. 3 A is the top view of the various exemplary embodiment layout of Esd protection device that the present invention provides；
Fig. 3 B and Fig. 3 C is that the various exemplary of the Esd protection device of the A-A ' line along Fig. 3 A that the present invention provides is implemented
The cross section of example；
Fig. 4 A and 5A shows the middle process of another kind of exemplary embodiment for manufacturing Esd protection device of the present invention
Top view；
Fig. 4 B and Fig. 5 B is the another exemplary embodiment of the Esd protection device of the A-A ' line along Fig. 4 A and Fig. 5 A
Cross section；
Fig. 6 A and 7A shows the middle process of another exemplary embodiment for manufacturing Esd protection device of the present invention
Top view；
Fig. 6 B, 7B and 7C are other exemplary embodiments of the Esd protection device of the A-A ' line along Fig. 6 A and Fig. 7 A
The cross section providing.
Specific embodiment
Description is performed for embodiments of the invention below.Explained below is the General Principle for the present invention is described
And be not be considered in a limiting sense.The scope of the present invention to be determined by reference to claims.Retouching in description
In stating, identical reference in the accompanying drawings and the description is used for referring to same or analogous part.
Below in conjunction with specific embodiment and with reference to the accompanying drawings to describe the present invention, but the invention is not restricted to this.Described
Accompanying drawing be only schematically to be not intended to limit the present invention.It should be noted that in the accompanying drawings, the size of some elements
Can be extended and be not drawn to scale.These sizes and related size can not correspond to the actual chi implementing the present invention
Very little.
Fig. 1 is the circuit diagram of the exemplary embodiment of Esd protection device 500 that the present invention provides.Shown in Fig. 1
Circuit diagram illustrates two Esd protection device 500 for protecting input/output (IO) device.As shown in figure 1, ESD protection dress
Put 500 be diode type (diode-typed) Esd protection device.For the protection of I/O device, Esd protection device 500
Anode (anode) can be couple to low-tension supply terminal VSS, and the negative electrode (cathode) of Esd protection device 500 can be couple to
Shielded I/O device.Optionally, the anode of this Esd protection device 500 can be couple to shielded I/O device, and ESD
The negative electrode of protection device 500 can be couple to high voltage power supply terminal VDD.I/O device may include Metal-oxide-semicondutor field effect
Transistor (metal-oxide-semiconductor field-effect transistors, MOS field-effect transistor), can
Erasable programmable read-only memory (EPROM) (erasable programmable read-only memories, EPROM), electric erasable
Programmable read only memory (electrically erasable programmable read-only memories,
EEPROM), static RAM (static random access memories, SRAM), dynamic randon access is deposited
Reservoir (dynamic random access memories, DRAM), single-electronic transistor (single electron
Transistors, SETs), diode, electric capacity, inductance or combinations thereof.
Fig. 2A is the top view of the layout of an exemplary embodiment of Esd protection device 500a that the present invention provides.Figure
2B is the cross section of an exemplary embodiment of the Esd protection device of the A-A ' line along Fig. 1.As shown in Figure 2 A and 2 B, ESD
One exemplary embodiment of protection device 500a includes the Semiconductor substrate with active area (active region) 400
(semiconductor substrate)200.Semiconductor substrate 200 can include silicon (silicon).In optional embodiment
In, SiGe (silicon-germanium, SiGe), bulk semiconductor (bulk semiconductor), strain semiconductor
(strained semiconductor), compound semiconductor (compound semiconductor), the silicon on insulator
(silicon on insulator, SOI), and other conventional Semiconductor substrate is used as Semiconductor substrate 200.Pass through
Implanted with p-type or p-type impurity, Semiconductor substrate 200 can have the conduction type wanted.There is the first trap of the first conduction type
Area 202 is formed on active area 400, and the bottom label 203 of the first well region 202 indicates.Second well region 204 is formed about
On the active area 400 on the border 205 of one well region 202.Multiple first doped regions 212 with the first conduction type are formed at first
Well region 202, this first well region 202 is adjacent to the surface of Semiconductor substrate 200.In one embodiment, multiple first doped regions 212
That distinguishes is isolated from the border 205 of the first well region 202 by multiple shallow trenchs isolation (STI) part 201.In an embodiment
In, the doping content (dopant concentration) of the first doped region 212 is bigger than the doping content of the first well region 202.Cause
This, if the first well region 202 is as N-shaped well region 202, the first doped region 212 will be used as N-shaped height (n+) doped region 212.Optional
, if the first well region 202 is as p-type well region 202, the first doped region 212 will be used as p-type height (p+) doped region 212.ESD protects
At least two for the anode of Schottky diode (Schottky diode) and cathode electrode are also included in protection unit 500a
Hard contact.As shown in Figure 2 A and 2B, the first hard contact 216 is disposed in the first doped region 212.Second hard contact 214
It is disposed in active area 400 (surface of neighbouring Semiconductor substrate 200), and does not pass through any high (n+ or p+) doped region and connect
To the first well region 202.In the present embodiment, the first metallic contact 216 and the second hard contact 214 are disposed in the first well region
202 poly pattern 208 separates.And, the design rule of the semiconductor technology according to standard, the first hard contact 216 He
Second hard contact 214 must with poly pattern 208 keep at least one design apart from (not shown).Additionally, according to standard
Semiconductor technology, formed poly pattern 208 before, insulation pattern 206 be formed at poly pattern 208 and quasiconductor lining
Between bottom 200.Additionally, after forming poly pattern 208, interval (spacer) 210 is mounted respectively polysilicon figure
Two relative side walls of sample 208.Therefore, insulate pattern 206, and poly pattern 208 and interval 210 can be commonly constructed grid
Pole structure (gate structure) 220.And, according to the semiconductor technology of standard, the first silicide pattern 224 and the second silicon
Compound pattern 222 can be covered each by the different piece of the first well region 202 not covered by grid structure 220, to improve
Electric conductivity between first hard contact 216/ second hard contact 214 and Semiconductor substrate 200.As shown in Figure 2 A and 2B,
One silicide pattern 224 is disposed between the first hard contact 216 and the first doped region 212, and the second silicide pattern 222
It is disposed between the second hard contact 214 and the first well region 202.In the present embodiment, Esd protection device 500a is by second
Hard contact 214 and the Schottky diode of the first well region 202 composition.
In one embodiment, Semiconductor substrate 200, the first well region 202 and the first doped region 212 can have and the second trap
Area 204 identical conduction type.For example, as p-type semiconductor substrate 200, the first well region 202 is as p-type for Semiconductor substrate 200
Trap (p-type well, PW) area 202, and the second well region 204 is as p-type trap (PW) area 204.Additionally, the first doped region 212 can
As p-type high concentration (p+) doped region.In one embodiment, this first hard contact 216 and low-tension supply terminal couple,
This second hard contact 214 is coupled with input/output device, and in other embodiments, the first hard contact 216 is coupled to
High voltage power supply terminal VDD and the second hard contact 214 are coupled to input/output (IO) device, or in other embodiment party
In formula, this first hard contact can be coupled with input/output device (IO), and this second hard contact and low tension source
Son couples, and wherein, above-mentioned other embodiment can include there is the situation shown in the 3rd well region (as Fig. 3 C).
In another embodiment, Semiconductor substrate 200 can have with the first well region 202 and the first doped region 212 not
Same conduction type.In addition, the second well region 204 also has the conductive-type different from the first well region 202 and the first doped region 212
Type.For example, Semiconductor substrate 200 is as p-type semiconductor substrate 200, the first well region 202 can as N-shaped trap (n-type well,
NW) region 202, and the second well region 204 is as p-type trap (p-type well, PW) area 204.Second well region 204 is protected as ESD
The protection ring (guard ring) of device 500a.Additionally, the first doped region 212 can be used as N-shaped height (n+) doped region.In this enforcement
In example, the first hard contact 216 is coupled to input/output (IO) device and the second hard contact 214 is coupled to low tension
Source terminal VSS, in other embodiments, this first hard contact 216 can also be coupled with high voltage power supply terminal, and this second
Hard contact 214 is coupled with input/output (IO) device, or, in other embodiments, this first hard contact and low tension
Source terminal couples, and this second hard contact is coupled with input/output device.It should be noted that poly pattern 208 is electricity floating
Dynamic, or optionally couple with the first well region, or the circuit beyond being optionally couple to electrostatic discharge protective equipment provided
Bias.
Additionally, in one embodiment, second doped region 213 with the first conduction type is optionally formed at the first trap
Area 202.In addition, the second hard contact 214 is disposed in the second doped region 213.In the present embodiment, the second doped region 213 can
As low (lightly) doped region, the doping content of the second doped region 213 is less than the doping content of the first doped region 212.Example
As if the first doped region 212 is as p-type height (p+) doped region, the second doped region 213 is as p-type low-doped drain (p-type
Lightly doped drain, PLDD) area.If the first doped region 212 is as N-shaped height (n+) doped region, the second doped region
213 can be used as N-shaped low-doped drain (NLDD) area.
Fig. 3 A be the present invention provide Esd protection device 500b and 500c the layout of various exemplary embodiment top
View.Fig. 3 B and 3C is the cross section of the various exemplary embodiment of the Esd protection device of the A-A ' line along Fig. 3 A, it illustrates
The cross section of the various exemplary embodiment of Esd protection device 500b and 500c.In this embodiment, for sake of simplicity, this enforcement
Description with those elements of identical in Fig. 2A and Fig. 2 B in example, here is not repeated.As shown in Figure 3 A and Figure 3 B, ESD protection
The difference of device 500a and 500b is, also includes thering is the 3rd doping being formed at the second well region in Esd protection device 500b
Area 240, the conduction type of the 3rd doped region 240 is the second conduction type, and it is contrary with the first conduction type.3rd doped region
240 and first doped region 212 be to be separated by STI part 201.Additionally, the doping content of the 3rd doped region 240 is than the second well region
202 doping content is big.3rd hard contact 232 is disposed in the 3rd doped region 240.As shown in Figure 3 A and Figure 3 B, the 3rd silicon
Compound pattern 236 is disposed between the 3rd hard contact 232 and the 3rd doped region 240.
In this embodiment shown by Fig. 3 A and 3B, Semiconductor substrate 200 can have and the first well region 202 and first
The different conduction type of doped region 212.And, the 3rd doped region 240 can have and the second well region 204 identical conduction type.
For example, in Semiconductor substrate 200 as p-type semiconductor substrate 200, the first well region 202 can as N-shaped trap (n-type well,
NW) area 202, and the second well region 204 is as p-type trap (p-type well, PW) area 204.Second well region 204 protects dress as ESD
Put the protection ring 204 of 500b, and the 3rd doped region 240 is as the pickup doped region of the protection ring 204 of Esd protection device 500b.
Additionally, the first doped region 212 can be used as N-shaped height (n+) doped region 212, and the 3rd doped region 240 can be used as p-type height (p+) doping
Area 240.In the present embodiment, the first hard contact 216 is coupled to input/output (IO) device and the second metallic contact 214
It is coupled to low-tension supply terminal VSS.It should be noted that poly pattern 208 is electrically floating, or optional with the first trap
Area couples, or the bias that the circuit beyond being optionally couple to electrostatic discharge protective equipment is provided.In addition, implementing at one
In example, second doped region 213 with the first conduction type is optionally formed at the first well region 202.For example, the second doped region
213 can be used as N-shaped low-doped drain (n-type lightly doped drain, NLDD) area.
As shown in Fig. 3 A and 3C, the difference between Esd protection device 500b and 500c is, Esd protection device 500c is entered
One step includes the 3rd well region 234 being formed in active area 400, when having and the first well region 202 and in Semiconductor substrate 200
During one doped region, 212 identical the first conduction type, the 3rd well region 234 contacts bottom 203 and second trap of the first well region 202
The bottom in area 204.In embodiment shown by Fig. 3 A and 3C, the first well region 202 can have and the second different leading of well region 204
Electric type.And, the 3rd well region 234 and the 3rd doped region 240 can have and the second well region 204 identical conduction type.For example,
Semiconductor substrate 200 as p-type semiconductor substrate 200, the first well region 202 as p-type trap (p-type well, PW) area 202,
Second well region 204 can be used as N-shaped trap (n-type well, NW) area 204, and the 3rd well region 234 is used as depth N-shaped trap (deep
N-type well, DNW) area 234.Second well region 204 is used as the protection ring 204 of Esd protection device 500c, and the 3rd doped region
240 as the protection ring 204 of Esd protection device 500b pickup doped region.Additionally, the first doped region 212 can be used as p-type height (p
+) doped region 212, and the 3rd doped region 240 can be used as N-shaped height (n+) doped region 240.In the present embodiment, the first hard contact
216 are coupled to high voltage power supply terminal VDD and the second hard contact 214 is coupled to input/output (IO) device.Merit attention
, poly pattern 208 is electrically floating, or optionally couples with the first well region, or be optionally couple to static discharge
The bias that circuit beyond protection device is provided.In addition, in one embodiment, having the second doping of the first conduction type
Area 213 is optionally formed at the first well region 202.For example, the second doped region 213 can be used as p-type low-doped drain (p-type
Lightly doped drain, PLDD) area.
Fig. 4 A and Fig. 5 A is to illustrate in the Esd protection device 500d another kind exemplary embodiment for manufacturing the present invention
Between technique top view.Fig. 4 B and 5B is the horizontal stroke of the exemplary embodiment of the Esd protection device of A-A ' line along along Fig. 4 A and 5A
Section.For sake of simplicity, the description with similar elements in the above embodiment of Fig. 2A and Fig. 2 B in this embodiment, it is not repeated.
As Fig. 4 A, shown in 4B, 5A and 5B, the difference between Esd protection device 500a and 500d is, by using resistance protection oxidation
(resistor protection oxide, RPO) technique, Esd protection device 500d is produced with shape in the first well region 202
Become at least one insulating barrier pattern 230, cover at least a portion of the upper surface 250 of the first well region 202.Insulating barrier pattern 230
Can be as mask (mask), to stop partly being gone up by what insulating barrier pattern 230 covered in the first well region 202 upper surface 250
Generate silicide drawing information.In this embodiment, insulating barrier pattern 230 is resistance protection oxidation (RPO) pattern 230.Then,
Execution injection technology, to form first doped region 212 with the first conduction type, this first well region on the first well region 202
202 adjacent to the surface of Semiconductor substrate 200.As shown in Figure 4 A and 4 B shown in FIG., in multiple vertical sidewalls 242 of insulating barrier pattern 230
One be aligned the first doped region 212 border 244.In addition, in one embodiment, have the first conduction type second mixes
Miscellaneous area 213 is optionally formed at the first well region 202.Then, execute silicide process, with the upper surface 250 in the first well region 202
Other parts (part not covered by insulating barrier pattern 230) formed silicide pattern, including the first silicide pattern
224 it is also possible to include the second silicide pattern 222.As shown in Figure 4 A and 4 B shown in FIG., the first silicide pattern 224 can cover first
Doped region 212.Optionally, the second silicide pattern 222 in multiple silicide patterns can cover the second doped region 213.
As shown in Figure 5 A and 5B, then, the insulating barrier pattern 230 shown in Fig. 4 A and 4B is removed.Then, the first metal
Contact 216 is formed on the first doped region 212.In addition, the second hard contact 214 is formed at active area 400 (neighbouring quasiconductor lining
The surface at bottom 200), connect the first well region 202 not over any high (n+ or p+) doped region.It is optionally formed at having
In the embodiment of the second doped region 213 of the first well region 202, this second hard contact 214 can be disposed in the second doped region
213.Through above-mentioned technique, another kind of exemplary embodiment of Esd protection device 500d is completely formed.
Fig. 6 A and 7A is the middle process illustrating for manufacturing Esd protection device 500e and 500f further example embodiment
Top view.Fig. 6 B, 7B and 7C are the horizontal strokes of the other examples embodiment of the Esd protection device of the A-A ' line along Fig. 6 A and Fig. 7 A
Section, it illustrates the cross section of the various exemplary embodiment of Esd protection device 500e and 500f.For sake of simplicity, this enforcement
Example in prior figures 3A and Fig. 3 C in identical element description, be not repeated herein.As Fig. 6 A, 6B, 7A, 7B and 7C institute
Show, the difference between Esd protection device 500b-500c and 500e-500f is to aoxidize (RPO) using resistance protection further
Technique, Esd protection device 500e/f is produced to form at least one insulating barrier pattern 230 on the first well region 202, covers the
At least a portion of the upper surface 250 of one well region 202.Insulating barrier pattern 230 can be as mask, to stop in the first well region
The partly upper generation silicide drawing information being covered by insulating barrier pattern 230 of 202 upper surfaces 250.In this embodiment, insulate
Layer pattern 230 is resistance protection oxidation (resistor protection oxide, RPO) pattern 230.Then, execution injection work
Skill, has the first doped region 212 of the first conduction type to be formed on the first well region 202, and first well region 202 is neighbouring partly leads for this
The surface of body substrate 200.Additionally, another kind of injection technology of execution, to form the 3rd doped region 240, the 3rd doped region 240 shape
Become on the second well region 204 and there is the second conduction type, this second conduction type is contrary with the first conduction type.Then, hold
Row silicide process, with the other parts (portion not covered by insulating barrier pattern 230 of the upper surface in the first well region 202
Point) the multiple silicide patterns of upper formation, it includes the first silicide pattern 224 it is also possible to include the second silicide pattern 222.
As shown in Figure 6 A and 6 B, multiple first silicide patterns 224 can cover multiple first doped regions 212.Optionally, the plurality of silicon
The second silicide pattern 222 in compound pattern can cover the second doped region 213.
As Fig. 7 A, shown in 7B and 7C, then, the insulating barrier pattern 230 in Fig. 6 A and Fig. 6 B is removed.Then, the first gold medal
Belong to contact 216 and be formed at this first doped region 212.In addition, the second hard contact 214 is formed at active area 400 (neighbouring quasiconductor
The surface of substrate 200), it is connected to the first well region 202 not over any high (n+ or p+) doped region.There is optional shape
Become in the embodiment of the second doped region 213 of the first well region 202, the second hard contact 214 can be disposed in the second doping
Area 213.Through above-mentioned technique, another kind of exemplary embodiment of Esd protection device 500e/500f is completed into.As Fig. 7 B
With shown in 7C, the difference between Esd protection device 500e and 500f is, Esd protection device 500f further includes to be formed at
The 3rd well region 234 in active area 400.In addition, Esd protection device 500e and 500f also include being formed at the second well region and having
3rd doped region 240 of the second conduction type, this second conduction type is contrary with the first conduction type.3rd doped region 240 He
First doped region 212 is to be separated by STI part 201.Additionally, doping content the mixing than the second well region 202 of the 3rd doped region 240
Miscellaneous concentration is big.In addition, the 3rd hard contact 232 is formed on the 3rd doped region 240.It should be noted that because for RPO
The design rule of pattern is narrower than poly pattern, in the first hard contact 216 and second of Esd protection device 500d-500f
Minimum range between metallic contact 214 is less than the first gold medal being separated by the poly pattern of Esd protection device 500a-500c
Belong to the minimum range between contact 216 and the second hard contact 214.
Above mentioned embodiment provide Esd protection device.Esd protection device is made up of Schottky diode, defeated to protect
Enter/export (IO) device.The advantage of Esd protection device is, compared to traditional gate or STI diode, (threshold voltage is about
0.7V), this Esd protection device has relatively low threshold voltage (about 0.4V) on forward conduction.In addition, compared to traditional door
Control or STI diode, Esd protection device has relatively low junction capacity, forms the Esd protection device of low-load.Therefore, ESD protects
Protection unit is suitable for using in high speed circuit.In addition, Esd protection device uses poly pattern or RPO pattern (replacing STI)
To separate anode and the negative electrode of Esd protection device.Minimum range between the anode of Esd protection device and negative electrode can be further
Minimizing.Compared with traditional STI diode, Esd protection device has relatively low conducting resistance.
Although the present invention is disclosed above with preferred embodiment, so it is not limited to the present invention, any this area skill
Art personnel, without departing from the spirit and scope of the present invention, when can make a little change and retouching, therefore the protection model of the present invention
Enclose to work as and be defined by claims.
Claims (15)
1. a kind of electrostatic discharge protective equipment is it is characterised in that this electrostatic discharge protective equipment includes：There is partly leading of active area
Body substrate；
It is formed at first well region with the first conduction type of this active area；
It is formed at first doped region with this first conduction type of this first well region；
It is arranged in the first hard contact of this first doped region；
It is formed at second doped region with the first conduction type of this first well region；And
Be arranged in the second hard contact of this active area, be connected to this first well region, wherein, this first hard contact and this second
The poly pattern that hard contact is disposed in this first well region separates, and this second hard contact is arranged on this second doping
Area, the doping content of this second doped region is less than the doping content of this first doped region, and the doping content of this first doped region is big
Doping content in this first well region.
2. electrostatic discharge protective equipment according to claim 1 is it is characterised in that further include：
The subregion of the first silicide pattern and the second silicide pattern this first well region of covering respectively, wherein, this
One silicide pattern is disposed between this first hard contact and this first doped region, and this second silicide pattern is by cloth
Put between this second hard contact and this first well region.
3. electrostatic discharge protective equipment according to claim 2 it is characterised in that this first silicide pattern with this second
Silicide pattern two opposite ends adjoining this poly pattern respectively.
4. electrostatic discharge protective equipment according to claim 1 is it is characterised in that also include：
It is formed on the active area on border around the first well region and has the second well region of the second conduction type, this second is led
Electric type is contrary with this first conduction type；
It is formed at the 3rd doped region with this second conduction type of the second well region, and
It is disposed in the 3rd hard contact on the 3rd doped region.
5. electrostatic discharge protective equipment according to claim 4 it is characterised in that the 3rd doped region and this first mix
Miscellaneous area is isolated pattern and separates.
6. electrostatic discharge protective equipment according to claim 4 is it is characterised in that further include：
It is formed at the 3rd well region of this active area, when this Semiconductor substrate has the first conduction type, the 3rd well region contact
This first well region and the bottom of this second well region.
7. electrostatic discharge protective equipment according to claim 4 is it is characterised in that this Semiconductor substrate has this second leads
Electric type.
8. electrostatic discharge protective equipment according to claim 4 is it is characterised in that the doping content of the 3rd doped region is big
Doping content in this second well region.
9. electrostatic discharge protective equipment according to claim 1 is it is characterised in that further include：
It is formed about on the active area on this first well region border, and there is the second well region of this first conduction type.
10. electrostatic discharge protective equipment according to claim 1 it is characterised in that
This first conduction type is N-shaped, and this Semiconductor substrate is p-type, and this first hard contact is filled with input/output
Put and couple and the second hard contact is coupled with low-tension supply terminal；Or, this first hard contact and low-tension supply terminal coupling
Connect, this second hard contact is coupled with input/output device；
Or,
This first conduction type is N-shaped, and this Semiconductor substrate is p-type, and this first hard contact and high voltage power supply terminal couple, with
And this second hard contact is coupled with input/output device；
Or,
This first conduction type is p-type, and this Semiconductor substrate is p-type, and this first hard contact and high voltage power supply terminal couple, with
And this second hard contact is coupled with input/output device；
Or,
This first conduction type is p-type, and this Semiconductor substrate is p-type, and this first hard contact is coupled with input/output device,
And this second hard contact is coupled with low-tension supply terminal；
Or,
This first conduction type is p-type, and this Semiconductor substrate is p-type, and this first hard contact and low-tension supply terminal couple, should
Second hard contact and input/output device couple.
11. electrostatic discharge protective equipments according to claim 1 are it is characterised in that be arranged in the two of this poly pattern
The interval of individual opposing sidewalls.
12. electrostatic discharge protective equipments according to claim 1 it is characterised in that this poly pattern be electrically floating or
Couple with this first well region.
13. electrostatic discharge protective equipment according to claim 1 it is characterised in that this second hard contact and this
One well region forms Schottky diode.
A kind of 14. electrostatic discharge protective equipments are it is characterised in that this electrostatic discharge protective equipment includes：
There is the Semiconductor substrate of active area；
It is formed at first well region with the first conduction type of this active area；
It is formed at first doped region with this first conduction type of this first well region；
It is arranged in the first hard contact of this first doped region；
It is formed at second doped region with the first conduction type of this first well region；And
Be arranged in the second hard contact of this active area, connect this first well region, wherein, this first well region upper surface positioned at this
At least a portion between first hard contact and this second hard contact does not have silicide, and this second hard contact is set
In this second doped region, the doping content of this second doped region is less than the doping content of this first doped region, this first doped region
Doping content be more than this first well region doping content.
A kind of 15. electrostatic discharge protective equipments are it is characterised in that this electrostatic discharge protective equipment includes：
There is the Semiconductor substrate of active area；
It is formed at first well region with the first conduction type of this active area；
It is formed at first doped region with this first conduction type of this first well region；
It is arranged in the first hard contact of this first doped region；
It is formed at second doped region with the first conduction type of this first well region；And
It is arranged in the second hard contact of this active area, connects this first well region, wherein, do not have doped region to be formed at this second gold medal
Belong between contact and this first well region, this second hard contact is arranged on this second doped region, the mixing of this second doped region
Miscellaneous concentration is less than the doping content of this first doped region, and the doping content of this first doped region is dense more than the doping of this first well region
Degree.
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| US201361755248P | 2013-01-22 | 2013-01-22 | |
| US61/755,248 | 2013-01-22 | ||
| US14/108,559 US20140203368A1 (en) | 2013-01-22 | 2013-12-17 | Electrostatic discharge protection device |
| US14/108,559 | 2013-12-17 |
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| US9437590B2 (en) * | 2015-01-29 | 2016-09-06 | Mediatek Inc. | Electrostatic discharge protection device and electrostatic discharge protection system |
| JP7021414B2 (en) * | 2016-06-30 | 2022-02-17 | テキサス インスツルメンツ インコーポレイテッド | Contact array optimization for ESD devices |
| US10020381B1 (en) * | 2017-05-17 | 2018-07-10 | International Business Machines Corporation | Embedded bottom metal contact formed by a self-aligned contact process for vertical transistors |
| CN115995459B (en) * | 2023-03-24 | 2023-07-25 | 长鑫存储技术有限公司 | Charge guiding-out structure, guiding-out method, preparation method and semiconductor structure thereof |
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