TWI253155B - Thermally enhanced semiconductor package and fabrication method thereof - Google Patents

Thermally enhanced semiconductor package and fabrication method thereof Download PDF

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Publication number
TWI253155B
TWI253155B TW092114343A TW92114343A TWI253155B TW I253155 B TWI253155 B TW I253155B TW 092114343 A TW092114343 A TW 092114343A TW 92114343 A TW92114343 A TW 92114343A TW I253155 B TWI253155 B TW I253155B
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Taiwan
Prior art keywords
wafer
conductive
heat sink
exposed
bump
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TW092114343A
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English (en)
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TW200427029A (en
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Chien-Ping Huang
Cheng-Hsu Hsiao
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Siliconware Precision Industries Co Ltd
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Priority to TW092114343A priority Critical patent/TWI253155B/zh
Priority to US10/635,168 priority patent/US7019406B2/en
Publication of TW200427029A publication Critical patent/TW200427029A/zh
Priority to US11/362,419 priority patent/US7364944B2/en
Application granted granted Critical
Publication of TWI253155B publication Critical patent/TWI253155B/zh

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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

1253155 五、發明說明α) 【發明所屬之技術領域】 本發明係有關一種半導體封裝件及其製法，尤指一種 具有高散熱效能之半導體封裝件，以及製造該半導體封裝 件之方法。 【先前技術】 半導體封裝件係用以承載至少一積體電路元件例如半 導體晶片，且其尺寸係朝輕薄短小發展。針對此目的，遂 發展出一種晶片級封裝件（chip scale package，CSP)， 其尺寸係等於或略大於晶片之尺寸。 第5圖係如美國專利第6，2 8 7，8 9 3號案所揭露之晶片級 封裝件，其直接於晶片上形成增層（build-up layers)， 而無需使用例如基板或導線架等晶片承載件（ch i p c a r r i e r )以供承載半導體晶片之用。如圖所示，多數形成 於晶片1 0之作用表面（active surface)10 0上的增層，包 括：一介電層1 1，敷設於晶片1 0之作用表面1 0 0上並開設 有多數貫孔1 1 0，以使晶片1 0上的銲墊1 0 1藉該貫孔1 1 0外 露；以及多數導電跡線1 2，形成於該介電層1 1上並電性連 接至晶片1 0上外露的銲墊1 0 1。然後，敷設一拒銲劑層1 3 於導電跡線1 2上並開設多數貫穿該拒銲劑層1 3之開孔 1 3 0，以使導電跡線1 2之預定部分藉該開孔1 3 0外露而與銲 球1 4銲連，該銲球1 4則作為封裝件之輸入/輸出 (input/output， I/O)端以與外界裝置（未圖示）電性連 接。然而，是種晶片級封裝結構之缺點在於因受限於晶片 之尺寸或大小而無法提供更多表面區域以承載更多數量之
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17332矽品.ptd 第6頁 1253155 五、發明說明（2) 銲球供與外界電性連接之用。 鑑此，美國專利第6，2 7 1，4 6 9號案揭露另一種具有形 成於晶片上之增層的封裝結構，以提供額外或較多的表面 區域供與外界電性連接之用。如第6圖所示，是種封裝結 構利用一封裝膠體1 5遮覆住晶片1 0之非作用表面1 0 2及側 面1 0 3，而使晶片1 0之作用表面1 0 0外露且與封裝膠體1 5之 一表面1 5 0齊平。當晶片1 0上形成介電層1 1 (下稱”第一介 電層π )及導電跡線1 2 (下稱π第一導電跡線”）後，於該第一 導電跡線1 2上敷設一第二介電層1 6並開設多數貫穿第二介 電層1 6之貫孔1 6 0，以使第一導電跡線1 2的預定部分藉該 貫孔1 6 0外露。接著，於第二介電層1 6上形成多數第二導 電跡線1 7，而使第二導電跡線1 7與第一導電跡線1 2的外露 部分電性連接。然後，於第二導電跡線1 7上敷設拒銲劑層 1 3，使第二導電跡線1 7的預定部分藉拒銲劑層1 3之開孔 1 3 0外露而與銲球1 4銲連。 然而，上揭封裝結構之缺點在於當使用雷射鑽孔 (laser dr i 1 1 ing)技術開設貫穿第一介電層之貫孔以露出 晶片上的銲墊時，晶片上的銲墊為第一介電層所遮覆，而 使雷射通常難以準確地辨認出銲墊的位置，因而無法使所 開設的貫孔精確地對應至銲墊的位置。因此，由於晶片上 的銲墊無法完全露出，故難以確保導電跡線與銲墊間之電 性連接品質及製成之封裝成品的良率。同時，上揭封裝結 構（第6圖）中，晶片完全為封裝膠體所包覆，而未提供用 以散逸晶片運作所產生之熱量的機制，可能導致因過熱而
]7332 矽品.ptd 第7頁 1253155 五、發明說明（3) 使晶片受損等問題。 有鑑於此，如何提供一種具有高散熱效能之半導體封 裝件，以有效散逸晶片產生之熱量且能確保導電跡線與銲 墊間之電性連接品質，實為一重要課題。 【發明内容】 本發明之主要目的在於提供一種具有高散熱效能之半 導體封裝件及其製法，係使晶片黏接有一散熱片，且該散 熱片之面積與封裝件之面積相同而能有效散逸晶片所產生 之熱量，因而提昇封裝件之散熱效率。 本發明之另一目的在於提供一種具有高散熱效能之半 導體封裝件及其製法，係於晶片之銲墊上形成多數導電凸 塊以突顯出銲墊的位置，俾確保導電跡線與銲墊間之電性 連接，而能改善製成之封裝成品的良率。 為達成上揭及其他目的，本發明揭露一種具有高散熱 效能之半導體封裝件，包括：至少一晶片，具有一作用表 面及一相對之非作用表面，並於該作用表面上形成有多數 銲墊；多數導電凸塊，分別形成於該晶片之銲墊上；一散 熱片，與該晶片之非作用表面黏接，且該散熱片之面積大 於該晶片之面積；一封裝膠體，用以包覆該散熱片之與晶 片黏接的表面、晶片及導電凸塊，並使該散熱片之非用以 與晶片黏接的表面及該導電凸塊之端部外露出該封裝膠 體；多數導電跡線，形成於該封裝膠體上並電性連接至該 導電凸塊之外露端部；一拒銲劑層，敷設於該導電跡線上 並開設有多數開孔’以使該導電跡線之預定部分錯該開孔
17332 矽品.ptd 第8頁 1253155 五、發明說明（4) 外露；以及多數銲球，分別形成於該導電跡線之外露部分 上。 上揭半導體封裝件之製程步驟，包括下列步驟：製備 一晶圓，由多數晶片構成，各該晶片具有一作用表面及一 相對之非作用表面，並於該作用表面上形成有多數銲墊； 分別形成多數導電凸塊於各該晶片之輝塾上，切割該晶圓 以形成多數單離之晶片，而各該晶片具有多數導電凸塊； 提供一散熱片模組板，由多數散熱片構成，而使各該散熱 片與至少一該晶片之非作用表面黏接，且該散熱片之面積 大於該晶片之面積；形成一封裝膠體，用以包覆該散熱片 模組板之與晶片黏接的表面以及所有該晶片與導電凸塊， 並使該散熱片模組板之非用以與晶片黏接的表面及該導電 凸塊之端部外露出該封裝膠體；形成多數導電跡線於該封 裝膠體上，並使該導電跡線電性連接至該導電凸塊之外露 端部；敷設一拒銲劑層於該導電跡線上，並開設有多數貫 穿該拒銲劑層之開孔，以使該導電跡線之預定部分藉該開 孔外露；分別形成多數銲球於該導電跡線之外露部分上； 以及切割該封裝膠體及散熱片模組板，以分離各該散熱 片，而形成多數具有單離之散熱片的半導體封裝件。 上述半導體封裝件係使一散熱片直接與晶片黏接，該 散熱片外露出用以包覆晶片之封裝膠體且具有與封裝件面 積相同之面積，故能有效散逸晶片所產生之熱量，因而提 昇封裝件之散熱效率。再者，多數導電凸塊係直接形成於 晶片之銲墊上，並使導電凸塊之端部露出包覆晶片之封裝
]7332矽品.ptd 第9頁 1253155 五、發明說明（5) 膠體外；藉導電凸塊之外露端部得突顯出晶片上銲墊的位 置以供辨識，而使形成於封裝膠體上之導電跡線得藉導電 凸塊良好地電性連接至銲墊，因而改善製成之封裝成品的 良率。因此，該半導體封裝件無需如習知技術（第5及6圖） 中藉形成於第一介電層中之貫孔以露出晶片上之銲墊，而 能摒除因用以開設第一介電層之貫孔的雷射鑽孔技術難以 準確地辨識出銲墊位置而無法使銲墊精確或完整地外露因 而導致銲墊與導電跡線間電性連接不良等缺點。 【實施方式】 第一實施例 以下即配合所附圖式第1、2 A至2 F、3及4圖詳細說明 本發明所揭露之具有高散熱效能之半導體封裝件及其製法 的實施例。 如第1圖所示，本發明之半導體封裝件包括：至少一 晶片20，具有一作用表面20 0及一相對之非作用表面2 0 1， 並於該作用表面2 0 0上形成有多數銲墊2 0 2 ;多數導電凸塊 2 1，分別形成於晶片2 0之銲墊2 0 2上；一散熱片2 2 0，與晶 片2 0之非作用表面2 0 1黏接，且散熱片2 2 0之面積大於晶片 2 0之面積；一封裝膠體2 3，用以包覆散熱片2 2 0、晶片2 0 及導電凸塊2 1，並使散熱片2 2 0之底部2 2 1及導電凸塊2 1之 端部2 1 0外露出封裝膠體2 3 ;多數導電跡線2 4，形成於封 裝膠體2 3上並電性連接至導電凸塊2 1之外露端部2 1 0 ; — 拒銲劑層2 5，敷設於導電跡線2 4上並開設有多數開孔 2 5 0，以使導電跡線2 4之預定部分藉該開孔2 5 0外露；以及
17332 矽品.ptd 第10頁 1253155 五、發明說明（6) 多數銲球2 6，分別形成於導電跡線2 4之外露部分 述半導體封裝件得以第2A-2F圖所示之製程步驟製 得 首先，如第2 A圖所示’製備一晶圓1，其由多數晶片 2 0構成，各晶片2 0具有一作用表面2 0 0及一相對之非作用 表面2 0 1，並於各晶片2 〇之作用表面2 0 0上形成有多數銲墊 202。接著，進行一銲塊或栓塊形成（bumping or stud b u m p i n g )步驟，以於晶片2 0之各銲塾2 0 2上形成一導電凸 塊21，該導電凸塊21可為銲錫凸塊（solder bump)、高船 含量鋅錫凸塊（high lead solder bump)、金質銲塊（gold bump)、或金質栓塊（gold stud bump)等。 接著，如第2 B圖所示，進行一切單（s i n g u 1 a t i ο η )作 業切割晶圓2以形成多數單離之晶片2 0，而各晶片2 0具有 多數導電凸塊2 1。 如第2 C圖所示’提供一散熱片模組板（h e a t s i n k module plate)22，由多數散熱片22 〇構成，而使各散熱片 BK1
第11頁 17332 矽品.ptd 1 2 0藉一膠黏劑（adhesive) 2 7與至少一該單離之晶片20的 非作用表面2 0 1黏接，且各散熱片2 2 〇之面積大於對應之晶 片2 0的面積；散熱片模組板2 2係以一具導電性之金屬材料 例如銅等製成’而膠黏劑2 7較佳為一具導熱性的黏膠。 然後’進行一模壓（mo丨d丨ng )製程利用一習知樹脂材 料（例如環氧樹脂等）形成一封裝膠體2 3，用以包覆散熱片 模組板2 2及所有晶片2 0與導電凸塊2 j，並使散熱片模組板 2 2之底部2 2 1 (或非用以與晶片2 〇黏接之表面）外露出封裝 1253155 五、發明說明（7) 膠體23。 如第2 D圖所示，採用研磨（g r i n d i n g，例如機械研磨） 等方式移除部分之封裝膠體2 3，以使導電凸塊2 1之端部 2 1 0露出並與封裝膠體2 3之表面2 3 0齊平，俾得進行後續製 程以於外露之導電凸塊21上形成增層（build-up layer); 而面積較大之散熱片2 2 0或散熱片模組板2 2使形成其上之 封裝膠體2 3得提供較多的表面區域（即封裝膠體2 3之表面 2 3 0 )以供後續形成增層及更多數量的輸入/輸出 (input/output， I/O)端（未圖示）之用。 接著，利用習知例如光微影（P h 〇 t ο li t h 〇 g r a p h y )技術讀^ 於封裝膠體2 3之表面2 3 0上形成多數導電跡線2 4，並使各 導電跡線2 4與至少一導電凸塊2 1之外露端部2 1 0電性連 接，該導電跡線2 4係以一例如銅、鋁、或其合金等之導電 材料製成。 如第2 E圖所示，於封裝膠體2 3上形成導電跡線2 4後， 於該導電跡線2 4上敷設一拒銲劑層2 5，並開設多數貫穿拒 銲劑層2 5之開孔2 5 0，以使導電跡線2 4之預定部分藉該開 孔2 5 0外露，而該導電跡線2 4之外露部分可為終端部位 (terminal)。接著，進行一習知網印(screen printing) 作業於各導電跡線2 4之外露部分（終端）上形成一銲球2 6， ^ 該銲球2 6作為半導體封裝件之輸入/輸出端，以使晶片2 0 藉之與外界裝置（未圖示，如印刷電路板等）成電性連接關 係。 最後，如第2F圖所示，進行一切單作業切割封裝膠體
17332 矽品.ptd 第12頁 1253155 五、發明說明（8) 2 3及散熱片模組板2 2，以分離各散熱片2 2 0，而形成多數 具有單離之散熱片2 2 0的半導體封裝件。 上述半導體封裝件係使一散熱片直接與晶片黏接，該 散熱片外露出用以包覆晶片之封裝膠體且具有與封裝件面 積相同之面積，故能有效散逸晶片所產生之熱量，因而提 昇封裝件之散熱效率。再者，多數導電凸塊係直接形成於 晶片之銲墊上，並使導電凸塊之端部露出包覆晶片之封裝 膠體外；藉導電凸塊之外露端部得突顯出晶片上銲墊的位 置以供辨識，而使形成於封裝膠體上之導電跡線得藉導電 凸塊良好地電性連接至銲墊，因而改善製成之封裝成品的 良率。因此，該半導體封裝件無需如習知技術（第5及6圖） 中藉形成於第一介電層中之貫孔以露出晶片上之銲墊，而 能摒除因用以開設第一介電層之貫孔的雷射鑽孔技術難以 準確地辨識出銲墊位置而無法使銲墊精確或完整地外露因 而導致銲墊與導電跡線間電性連接不良等缺點。 第二實施例 第3圖顯示本發明之第二實施例半導體封裝件。如圖 所示，該半導體封裝件之結構大致與上述第一實施例所揭 露之半導體封裝件相同，其不同處在於形成導電跡線 2 4 (下稱π第一導電跡線”）於封裝膠體2 3上後，先敷設一介 電層2 8於該第一導電跡線2 4上，並利用例如雷射鑽孔 (1 a s e r d r i 1 1 i n g )技術開設多數貫穿介電層2 8之貫孔 (v i a ) 2 8 0，以使第一導電跡線2 4之預定部分藉該貫孔2 8 0 外露。接著，於該介電層2 8上形成多數第二導電跡線2 9，
17332 矽品.ptd 第13頁 1253155 五、發明說明（9) 並使各第二導電跡線2 9與至少一第一導電跡線2 4之外露部 分電性連接。 然後，再於第二導電跡線2 9上敷設拒銲劑層2 5，並開 設多數貫穿拒銲劑層2 5之開孔2 5 0，以使第二導電跡線2 9 之預定部分藉該開孔2 5 0外露，而該第二導電跡線2 9之外 露部分可為終端部位（t e r m i n a 1 )。接著，進行習知網印 (screen printing)作業於各第二導電跡線2 9之外露部分 (終端）上形成作為半導體封裝件之輸入/輸出端之銲球 2 6，以與外界裝置（未圖示）成電性連接關係。 因此，除上述第一實施例之半導體封裝件所達成之功 4 效外，介電層及第二導電跡線之形成得增加晶片上之增層 而能提昇封裝件中導電跡線佈設的彈性，以使晶片更能有 效地電性連接至銲球及外界裝置俾進行運作。 第三實施例 第4圖顯示本發明之第三實施例半導體封裝件。如圖 所示，該半導體封裝件之結構大致與上述第一實施例所揭 露之半導體封裝件相同，其不同處在於散熱片2 2 0之與晶 片2 0黏接的表面2 2 3形成有多數凹槽2 2 2，以使用以形成封 裝膠體2 3之樹脂材料及用以黏接晶片2 0與散熱片2 2 0之膠 黏劑2 7得填入該凹槽2 2 2中，而能增加散熱片2 2 0之表面 _ 2 2 3與封裝膠體2 3及晶片2 0間之附著力；或者，使該散熱 片2 2 0之表面2 2 3呈粗糙化（未圖示）亦有助於增進散熱片2 2 與封裝膠體2 3及晶片2 0間之附著力。 惟以上所述者，僅係用以說明本發明之具體實施例而
]7332矽品.ptd 第14頁 1253155 五、發明說明（10) 已，並非用以限定本發明之可實施範圍，舉凡熟習該項技 藝者在未脫離本發明所指示之精神與原理下所完成之一切 等效改變或修飾，仍應皆由後述之專利範圍所涵蓋。
]7332 矽品.ptd 第15頁 1253155 圖式簡單說明 【圖式簡單說明】 為讓本發明之上述及其他目的、特徵以及優點能更明 顯易懂，將與較佳實施例，並配合所附圖示，詳細說明本 發明之實施例，所附圖示之内容簡述如下： 第1圖係本發明之第一實施例半導體封裝件之剖視 圖， 第2 A至2 F圖係第1圖之半導體封裝件之製造過程步驟 示意圖； 第3圖係本發明之第二實施例半導體封裝件之剖視 ® ； # 第4圖係本發明之第三實施例半導體封裝件之剖視 圖； 第5圖係一習知半導體封裝件之剖視圖；以及 第6圖係另一習知半導體封裝件之剖視圖。 10 晶 片 100 作 用 表 面 101 銲 墊 102 非 作 用 表 面 103 側 面 11 (第一 )介 電 層 110 貝 12 (第- )導 電 跡線 13 拒 銲劑層 130 開 孔 14 銲 球 15 封 裝 膠 體 150 表 面 16 第 二 介 電 層 160 貫 17 第 二 導 電 跡 線 2 晶 圓 20 晶 片
17332矽品.ptd 第16頁 1253155 圖式簡單說明 200 作 用 表 面 201 非 作 用 表 面 202 銲 墊 21 導 電 凸 塊 210 端 部 22 散 熱 片 模 組 板 220 散 敎 4 片 221 底 部 222 凹 槽 223 表 面 23 封 裝 膠 體 230 表 面 24 (第- )導電跡線 25 拒 銲 劑 層 250 開 孔 26 銲 球 27 膠 黏 劑 28 介 電 層 280 貫 孔 29 第 二 導 電 跡 線 ❹
I iiilip 17332石夕品.ptd 第]7頁

Claims (1)

1253155 案號 92Π4343 修正 六、申請專利範圍 1. 一種具有高散熱效能之半導體封裝件，包括： 至少一晶片，具有一作用表面及一相對之非作用 表面，並於該作用表面上形成有多數銲墊； 多數導電凸塊，分別形成於該晶片之銲墊上； 一散熱片，與該晶片之非作用表面黏接，且該散 熱片之面積大於該晶片之面積； 一封裝膠體，用以包覆該散熱片、晶片及導電凸 塊，並使該散熱片之非用以與晶片黏接的表面及該導 電凸塊之端部外露出該封裝膠體； 多數第一導電跡線，形成於該封裝膠體上並電性 連接至該導電凸塊之外露端部； 一拒銲劑層，敷設於該第一導電跡線上並開設有 多數開孔，以使該第一導電跡線之預定部分藉該開孔 外露；以及 多數銲球，分別形成於該第一導電跡線之外露部 分上。 2. 如申請專利範圍第1項之半導體封裝件，復包括：一介 電層，敷設於該第一導電跡線上並開設有多數貫孔， 以使該第一導電跡線之預定部分藉該貫孔外露。 3. 如申請專利範圍第2項之半導體封裝件，復包括：多數 第二導電跡線，形成於該介電層上並電性連接至該第 一導電跡線之外露部分。 4. 如申請專利範圍第3項之半導體封裝件，其中，該拒銲 劑層係敷設於該第二導電跡線上並開設有多數開孔，
17332石夕品.ptc 第18頁 1253155 案號 92114343 修正 六、申請專利範圍 以使該第二 5. 如申請專利 係分別形成 6. 如申請專利 片之與晶片 面與該封裝 7. 如申請專利 片之與晶片 該封裝膠體 8. 如申請專利 凸塊係選自 塊、及金質 9. 一種具有高 列步驟： 作用表面及 形成有多數 分別形 切割該 具有多數導 提供一 各該散熱片 散熱片之面 形成一 鮮塾； 成多數 晶圓以 電凸塊 散熱片 與至少 積大於 封裝膠 導電跡線之預定部分藉該開孔外露。 範圍第4項之半導體封裝件，其中，該銲球 於該第二導電跡線之外露部分上。 範圍第1項之半導體封裝件，其中，該散熱 黏接的表面形成有多數凹槽，以增加該表 膠體及晶片間之附著力。 範圍第1項之半導體封裝件，其中，該散熱 黏接的表面係呈粗糙化，以增加該表面與 及晶片間之附著力。 範圍第1項之半導體封裝件，其中，該導電 銲錫凸塊、高鉛含量銲錫凸塊、金質銲 栓塊所組成之組群。 散熱效能之半導體封裝件之製法，包括下 製備一晶圓，由多數晶片構成，各該晶片具有一 一相對之非作用表面，並於該作用表面上 導電凸塊於各該晶片之銲墊上； 形成多數早離之晶片，而各该晶片 模組板，由多數散熱片構成，而使 一該晶片之非作用表面黏接，且該 該晶片之面積； 體，用以包覆該散熱片模組板及所
17332矽品.ptc 第19頁 年 > 月厂曰 修正 1253155 _案號 92114343 六、申請專利範圍 有該晶片與導電凸塊’並使該散熱片模組板之非用以 與晶片黏接的表面及該導電凸塊之端部外露出該封裝 膠體； 形成多數導電跡線於該封裝膠體上，並使該導電 跡線電性連接至該導電凸塊之外露端部； 敷設一拒銲劑層於該導電跡線上，並開設有多數 貫穿該拒銲劑層之開孔，以使該導電跡線之預定部分 藉該開孔外露； 分別形成多數銲球於該導電跡線之外露部分上； 以及 切割該封裝膠體及散熱片模組板，以分離各該散 熱片，而形成多數具有單離之散熱片的半導體封裝 件。 1 0 .如申請專利範圍第9項之製法，其中，部分之該封裝膠 體係利用研磨技術移除，以使該導電凸塊之端部外 露。 1 1.如申請專利範圍第9項之製法，其中，該導電凸塊係選 自鲜錫凸塊、高錯含量銲錫凸塊、金質銲塊、及金質 栓塊所組成之組群。 1 2 .如申請專利範圍第9項之製法，其中，該散熱片模組板 之與晶片黏接的表面形成有多數凹槽，以增加該表面 與該封裝膠體及晶片間之附著力。 1 3 .如申請專利範圍第9項之製法，其中，該散熱片模組板 之與晶片黏接的表面係呈粗糙化，以增加該表面與該
17332矽品.ptc 第20頁 1253155 _案號92114343 <7、—年上月日 修正_ 六、申請專利範圍 封裝膠體及晶片間之附著力。 1 4. 一種具有高散熱效能之半導體封裝件之製法，包括下 列步驟： 製備一晶圓，由多數晶片構成，各該晶片具有一 作用表面及一相對之非作用表面，並於該作用表面上 形成有多數銲墊； 分別形成多數導電凸塊於各該晶片之銲墊上； 切割該晶圓以形成多數早離之晶片’而各该晶片 具有多數導電凸塊； 提供一散熱片模組板，由多數散熱片構成，而使 各該散熱片與至少一該晶片之非作用表面黏接，且該 散熱片之面積大於該晶片之面積； 形成一封裝膠體，用以包覆該散熱片模組板及所 有該晶片與導電凸塊^並使該散熱片模組板之非用以 與晶片黏接的表面及該導電凸塊之端部外露出該封裝 膠體； 形成多數第一導電跡線於該封裝膠體上，並使該 第一導電跡線電性連接至該導電凸塊之外露端部； 敷設一介電層於該第一導電跡線上，並開設多數 貫穿該介電層之貫孔，以使該第一導電跡線之預定部 分藉該貫孔外露； 形成多數第二導電跡線於該介電層上，並使該第 二導電跡線電性連接至該第一導電跡線之外露部分； 敷設一拒銲劑層於該第二導電跡線上，並開設有
17332石夕品.ptc 第21頁 1253155 案號 92114343 修正 六、申請專利範圍 多數貫穿該拒銲劑層之開孔，以使該第二導電跡線之 預定部分藉該開孔外露； 分別形成多數銲球於該第二導電跡線之外露部分 上；以及 切割該封裝膠體及散熱片模組板，以分離各該散 熱片，而形成多數具有單離之散熱片的半導體封裝 件。 1 5 .如申請專利範圍第1 4項之製法，其中，部分之該封裝 膠體係利用研磨技術移除，以使該導電凸塊之端部外 露。 1 6 .如申請專利範圍第1 4項之製法，其中，該導電凸塊係 選自銲錫凸塊、高鉛含量銲錫凸塊、金質銲塊、及金 質栓塊所組成之組群。 1 7.如申請專利範圍第1 4項之製法，其中，該散熱片模組 板之與晶片黏接的表面形成有多數凹槽，以增加該表 面與該封裝膠體及晶片間之附著力。 1 8 .如申請專利範圍第1 4項之製法，其中，該散熱片模組 板之與晶片黏接的表面係呈粗糙化，以增加該表面與 該封裝膠體及晶片間之附著力。
17332矽品.ptc 第22頁
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