TWI243332B - Registers for 2-D matrix processing - Google Patents

Registers for 2-D matrix processing Download PDF

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Publication number
TWI243332B
TWI243332B TW089112946A TW89112946A TWI243332B TW I243332 B TWI243332 B TW I243332B TW 089112946 A TW089112946 A TW 089112946A TW 89112946 A TW89112946 A TW 89112946A TW I243332 B TWI243332 B TW I243332B
Authority
TW
Taiwan
Prior art keywords
register
matrix
registers
data
processor
Prior art date
Application number
TW089112946A
Other languages
English (en)
Chinese (zh)
Inventor
George K Chen
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of TWI243332B publication Critical patent/TWI243332B/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30109—Register structure having multiple operands in a single register
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30141—Implementation provisions of register files, e.g. ports

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Complex Calculations (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
TW089112946A 1999-07-26 2000-06-30 Registers for 2-D matrix processing TWI243332B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/360,612 US6625721B1 (en) 1999-07-26 1999-07-26 Registers for 2-D matrix processing

Publications (1)

Publication Number Publication Date
TWI243332B true TWI243332B (en) 2005-11-11

Family

ID=23418740

Family Applications (1)

Application Number Title Priority Date Filing Date
TW089112946A TWI243332B (en) 1999-07-26 2000-06-30 Registers for 2-D matrix processing

Country Status (9)

Country Link
US (1) US6625721B1 (enExample)
EP (1) EP1212677B1 (enExample)
JP (2) JP4979169B2 (enExample)
CN (2) CN1532686B (enExample)
AU (1) AU5640400A (enExample)
DE (1) DE60022206T2 (enExample)
HK (1) HK1043850B (enExample)
TW (1) TWI243332B (enExample)
WO (1) WO2001008005A1 (enExample)

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US7386703B2 (en) * 2003-11-18 2008-06-10 International Business Machines Corporation Two dimensional addressing of a matrix-vector register array
US20060190517A1 (en) * 2005-02-02 2006-08-24 Guerrero Miguel A Techniques for transposition of a matrix arranged in a memory as multiple items per word
US20070011442A1 (en) * 2005-07-06 2007-01-11 Via Technologies, Inc. Systems and methods of providing indexed load and store operations in a dual-mode computer processing environment
US8661394B1 (en) 2008-09-24 2014-02-25 Iowa State University Research Foundation, Inc. Depth-optimal mapping of logic chains in reconfigurable fabrics
US8438522B1 (en) 2008-09-24 2013-05-07 Iowa State University Research Foundation, Inc. Logic element architecture for generic logic chains in programmable devices
US8484276B2 (en) * 2009-03-18 2013-07-09 International Business Machines Corporation Processing array data on SIMD multi-core processor architectures
JP5633122B2 (ja) * 2009-06-16 2014-12-03 富士通セミコンダクター株式会社 プロセッサ及び情報処理システム
CN101706760B (zh) * 2009-10-20 2013-07-31 龙芯中科技术有限公司 矩阵转置自动控制电路系统及矩阵转置方法
US8539201B2 (en) * 2009-11-04 2013-09-17 International Business Machines Corporation Transposing array data on SIMD multi-core processor architectures
CN103827814B (zh) * 2011-09-26 2017-04-19 英特尔公司 用于提供利用跨越功能的向量加载操作/存储操作的指令和逻辑
GB2507018B (en) 2011-09-26 2020-04-22 Intel Corp Instruction and logic to provide vector loads and stores with strides and masking functionality
US9292221B2 (en) 2011-09-29 2016-03-22 Intel Corporation Bi-directional copying of register content into shadow registers
US9946541B2 (en) * 2015-12-18 2018-04-17 Intel Corporation Systems, apparatuses, and method for strided access
KR102586173B1 (ko) * 2017-10-31 2023-10-10 삼성전자주식회사 프로세서 및 그 제어 방법
CN111429346A (zh) * 2020-03-16 2020-07-17 广州兴森快捷电路科技有限公司 一种基于fpga的实时视频图像放大方法
CN114546328B (zh) * 2022-03-01 2025-02-11 上海壁仞科技股份有限公司 用于实现数据排列的方法、设备和介质
US12373214B2 (en) 2022-12-28 2025-07-29 Meta Platforms Technologies, Llc Data parallelism

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8150901B2 (en) 2006-10-25 2012-04-03 Industrial Technology Research Institute Integrated conversion method and apparatus

Also Published As

Publication number Publication date
CN1160621C (zh) 2004-08-04
CN1532686A (zh) 2004-09-29
JP5466211B2 (ja) 2014-04-09
DE60022206D1 (de) 2005-09-29
DE60022206T2 (de) 2006-03-30
HK1043850A1 (en) 2002-09-27
HK1043850B (en) 2006-02-24
JP2012009055A (ja) 2012-01-12
EP1212677A1 (en) 2002-06-12
AU5640400A (en) 2001-02-13
EP1212677B1 (en) 2005-08-24
CN1532686B (zh) 2012-11-28
WO2001008005A1 (en) 2001-02-01
US6625721B1 (en) 2003-09-23
CN1365463A (zh) 2002-08-21
JP4979169B2 (ja) 2012-07-18
JP2003505786A (ja) 2003-02-12

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