TWI239620B - Method for forming ball pads of ball grid array package substrate - Google Patents

Method for forming ball pads of ball grid array package substrate Download PDF

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Publication number
TWI239620B
TWI239620B TW092124680A TW92124680A TWI239620B TW I239620 B TWI239620 B TW I239620B TW 092124680 A TW092124680 A TW 092124680A TW 92124680 A TW92124680 A TW 92124680A TW I239620 B TWI239620 B TW I239620B
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Taiwan
Prior art keywords
ball
package substrate
grid array
pads
array package
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TW092124680A
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English (en)
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TW200511547A (en
Inventor
Yi-Chuan Ding
Shun-Fu Ko
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Advanced Semiconductor Eng
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Priority to TW092124680A priority Critical patent/TWI239620B/zh
Priority to US10/933,350 priority patent/US20050054187A1/en
Publication of TW200511547A publication Critical patent/TW200511547A/zh
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Publication of TWI239620B publication Critical patent/TWI239620B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/421—Blind plated via connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09436—Pads or lands on permanent coating which covers the other conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/0969—Apertured conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0502—Patterning and lithography
    • H05K2203/054—Continuous temporary metal layer over resist, e.g. for selective electroplating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H05K3/062—Etching masks consisting of metals or alloys or metallic inorganic compounds
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3485—Applying solder paste, slurry or powder

Description

1239620 五、發明說明（1) 發明所屬之技術領域 本發明係有關於一種球格陣列封裝基板之製造方法 特別係有關於一種球格陣列封裝基板之接球墊形成方法 【先前技術】 I知之球格陣列封裝基板係作為球格陣列封裝結構之 晶片載板，該球格陣列封裝基板具有複數個由銅箔S合並 姓刻成格狀陣列之接球墊（ball pad)，以植接銲球作為該 球格陣列封裝結構之外部電性連接，習知該封裝基板之接 球表面上被覆有一防銲層〔solder mask〕，以覆蓋該基 板之線路結構並顯露該些接球墊，習知防銲層係製作在該 些接球墊形成之後，依防銲層之開口設計不同，該些接球Φ 墊，區分為NSMD墊〔None Solder Mask Define，非防銲層 界疋〕與SMD墊〔Solder Mask Define,防銲層界定〕， NSMj塾係指防銲層之開口大於接球墊，不由防銲層之開口 界定接球墊之顯露面積，使得接球墊對銲球有較佳的結合 面f ’但接球墊在該基板之結合固定較差；反之，SMD墊 係札防鋒層之開口小於接球墊，由防銲層之開口界定接球 塾之顯露面積，接球墊在該基板之結合固定較佳，但接球 ^對鲜球之結合較差，然而該些銲球與該防銲層有極弱之 結合，當銲球接合在…!）4NSMD型態之接球墊時，該防銲❿ 層與該些銲球之接觸界面過大時會影響銲球之結合。 凊參閱第4圖，例舉一種習知之球格陣列封裝結構，
其係包含有一具有複數個連接墊114之封裝基板11 〇，該封 裝基板110之黏晶表面112係黏設有一具有複數個銲墊1；H
第6頁 1239620
之晶片130，並以複數個銲線1 32電性連接該晶片13〇之該 些銲墊131與該基板11〇之連接墊114，習知該球袼陣列g 裝結構係以一封膠體140密封該晶片130及該些銲墊131， 而該封裝基板11〇在接球表面ιη係具有複數個SMD型態接 球墊113，該些接球墊113在製造上係與該封裝基板之 線路層〈圖未繪出〉為同層結構，並以一防銲層丨2 〇被覆 ，該封裝基板110之接球表面m，以覆蓋該線路層，該防 ，層1 2 0並具有複數個開口〗2 }，以顯露該些接球墊丨丨3， 該些接球墊1 1 3係結合有複數個銲球1 5 〇，然而該些接合在 接球墊113之銲球150常因與防銲層12〇接觸，而導致銲球 150之接合力較差，影響整體封裝結構之可靠度。 姓美國專利第6 3 9 6 7 0 7號揭示有另一種習知球格陣列封 裝…+冓’封裝基板之接球表面形成有NSMD型態之接球墊， =接球表面之防銲層之開孔係微大於該些接球墊，然而結 合在接球墊之銲球仍接觸該防銲層，對銲球之結合力無實 質幫助，若僅簡單地將該防銲層之開口放大，將使得該封 裝基板在接球表面之導電層線路為裸露，可能導致不當之 電〖生短路，故使得該基板之線路配置將顯得更困難。 【發明内容】 本發明之主要目的係在於提供一種球格陣列封裝基板4 =接，墊形成方法，其係利用在一防銲層形成之後形成一 $疋接球面之金屬層於該防銲層，再將複數個抗蝕罩幕 炎埶於f金屬層’以供#刻該金屬層形成複數個重界定接 1 ’该些重界定接球墊係覆蓋於該防銲層之該些開口且
1239620
五、發明說明（3) ___ ，接=些接球端，使得該些重界定接球墊之周邊 ^防銲層上，以在該防銲層上形成重^ 積，以增進對鮮球之結卜 ^球之接合面 之接提供：；球格陣列封裝基板 球面之金ϋ 基板之防銲層上覆蓋-重界定接 利用該些重界定接墊係覆蓋於兮防録屉夕疋接球塾’ 該些接破诚1=蛩係復盍於°亥防如層之该些開口且連接 防銲層_L，以=Ϊ ΐ重界定接球塾之周彡係可延伸至該 該防銲層，廿4新界:對銲球之接合面，避免銲球接觸至 增加銲球之接合力及結構之可靠产。 包含:m之ϊ格陣列封裝基板之接球墊形：方法，其 :驟為·首先所提供之封裝基板係具有一接 銲層：形成有複數個接球端與一防銲層，該防 ir 以顯露該些接球端；-重界定接 端；複數個^ ^ #屬層係經由該些開口連接該些接球 幕係；形：Γ金屬層上方，該些抗料 ϋϊίϊΐίίΐί層形成為複數個重界定接球塾，該 接球：該些開口且連接該些 銲層上。 一界疋接球墊之周邊係延伸至該防 【實施方式】 參閱所附圖式，本發明將列舉以下之實施例說明。 五、發明說明（4) 依本發明之球格陣列封裝基板之接球墊形成方法，請 =，第1A圖，首先提供—封裝基板i Q，該封裝基板1〇係具 接球表面1 1及一黏晶表面丨2，該黏晶表面丨2係供黏設 ^導體晶片6 0〔如第3圖所示〕，該黏晶表面丨2係形成 數個連接墊14，以電性連接該晶片6〇，而該接球表面 上糸用以接合外部電性連接之銲球8 〇〔如第3圖所示〕， 4接球表面1 1係形成有複數個接球端丨3與一防銲層2 〇 ,該 些，球端13係彳與該封裝&板1〇之線路層之複數個線路^ 係，同層結構’如第2圖所示’該些接球端13係一體連接 至4線路1 5，其可為線端或如方形或圓形之各式塾片，而 H，於如習^封裝基板必須$為圓％之接球塾，該防銲 :二t具有複數個開口21，以顯露該些接球端13〔該些接 係依防銲層20之開口21界定可為s〇型態及nsmd-型 之後，请參閱第1B圖，利用無電鍍〔electr〇less '。二^^或濺鍵^叫^^^以方式在該防銲層“上形 接球面之金屬層3〇，該金屬層30係經由該防銲 二^ #二"開口 21連接該些接球端1 3，該金屬層30係覆蓋 二妹微米’其材質較佳為選自銅與銅合金之群組·，接 了 ：月一 W第1C圖’複數個由乾膜形成之抗蝕罩幕4〇 二= ΜΑ〕係形成於該金屬層30上方，該些 應於該些接球端13，該些由乾膜形成之一抗 罩幕之具體作法係可為貼附一乾膜〔dry film〕在該 Η
國 第9頁 1239620 五、發明說明（5) =屬層30 ’並曝光顯影該乾膜’以形成為該些抗姓罩幕 =後，請參閱第1DB圖，钱刻該金屬層3〇，使得 敍罩幕40下方的金屬層3〇形成為複數個重界定接 墊31，該些重界定接球墊31係覆蓋於 口 21且連接該些接球端13，並且該些重界；Π:; 申至該防辉層20上，以避免在形成鲜；8二二周b 鈐球80與該防銲層2〇之接觸〔如第3圖所示〕，在 =中，該些重界定接球塾之厚度係介於3. 〇〜5 〇微 =習知之接球墊厚度，其具有達到輕質不脫落之功效； :外’凊參閱第1E圖，較佳地，制電鍍方式在該些 定接球墊31上形成一鎳/金層50，使該些重界定接球墊31 於封裝過程中不易被氧化並且容易與銲球8〇 銲球80之接合力及結構之可靠度。 曰加 因此，依本發明之球格陣列封裝基板之接球墊形成方 =，能在該封裝基板1〇之防銲層2〇上形成複數個重界定接 球墊31，該些重界定接球墊31係與被覆蓋該防銲層2〇之内 層線路1 5為非同層結構，利用該些重界定接球墊3丨係完全 覆蓋於該防銲層20之該些開口21且連接該些接球端13，並 且該些重界定接球墊31之周邊延伸至該防銲層2〇上，以避丨 免銲球80與該防銲層2〇接觸之功效，再請參閱第3圖，一 種具有上述重界定連接墊31之封裝基板1〇之半導體封裝結 構’其係包含一具有複數個銲墊61之半導體晶片6〇，，該^ 導體晶片60係黏設在該封裝基板1〇之黏晶表面12，並以複
1239620 五、發明說明（6) 數個銲線62電性 1〇之連接墊14， 62，而該封裝基 封’以及複數個 些銲球80係不與 計上其防銲層2 〇 小’以保護高密 層2 〇，而增加該 之球格陣列封裝 本發明之保 為準，任何熟知 圍内所作之任何 之該些 密封該 面11係 在該些 觸，因 需要擴 且因該 力及結 之產品 附之申 在不脫 均屬於 銲墊61與 晶片6 0及 不被該封 重界定接 此該封裝 大，甚至 些銲球80 構之可靠 信賴度。 請專利範 離本發明 本發明之 連接該晶片6 0 一封膠體70係 板1 0之接球表 銲球80係接合 該防銲層2 0接 之開口 2 1係不 度線路層，並 些銲球80接合 結構具有較佳 護範圍當視後 此項技藝者， 變化與修改， 該封裝基板 該些銲線 膠體70密 球塾31，該 基板1 0在設 有更為縮 不接觸防銲 度使得製作 圍所界定者 之精神和範 保護範圍。
1239620
圖弍簡單說明】 j據本發明之球格陣列封裝基板之接球墊形 .^ ^在製程中封裝基板之截面示意圖； 本發明之球格陣列封裝基板之接球墊形 法，重界定接球墊在封裝基板上之示意 第1A至1E圖 第2 圖 第 圖 第 圖 Γίΐ發：Γ求格陣列封裝基板之接物 裝4士構之之ϊ裝基板運用在一半導趙者 衣、，、σ構之截面示意圖；及 習知球格陣列封裝結構之截面示意圖。
元件符號簡單說明： 10 封裝基板 11 13 接球端 14 20 防銲層 21 30 金屬層 31 50 鎳/金層 60 晶片 61 70 封膠體 80 110 封裝基板 111 113 接球墊 114 120 防銲層 121 130 晶片 131 140 封膠體 150 接球表面 12黏晶表面 連接塾 15線路 開口 ‘ 重界定接球墊40抗蝕罩幕 銲墊 銲球 接球表面 連接墊 開口 銲線 銲球 62 銲線 11 2黏晶表面

Claims (1)

1239620
六、申請專利範圍 申請專利範圍 1、 一種球格陣 有： 提供一封裝 接球表面係形 係具有複數個 形成一重界 係由該防銲層 形成複數個 係對應於該些 蝕刻該金屬 成為複數個重 該防銲層之該 2、 如申請專利 球墊形成方法 該防銲層上。 3、 如申請專利 球墊形成方法 3 · 〇〜5 · 0微米， 4、 如申請專利 球墊形成方法 鍍與濺鍍之其 5、 如申請專利 球墊形成方法 列封裝基板之接球墊形成方法，其包含 基板，該封裝基板係具有一接球表面該 成有複數個接球端與一防銲層，該防銲層 開口，以顯露該些接球端； 疋接球面之金屬層於該防銲層，該金屬 之開口連接該些接球端； 抗蝕罩幕於該金屬層上方，該些抗蝕罩幕 接球端；及 旱奉 :二使得在該些抗蝕I幕下方的金屬層形 ，定接球墊，該些4界定接球墊係覆蓋於 些開口且連接該些接球端。 、 範圍第1項所述之球格陣列封裝基板之接 ，其中该些重界定接球墊之周邊係延伸至 範圍第1項所述之球格陣列封裝基板之接 ，其中該些重界定接球墊之厚度係介於 範，第1項所述之球格陣列封裝基板之接 ，其中該金屬層之形成方法係選自於無電 中之一。 … 範=項所述之球袼陣列封裝基板之接 ，、戎些重界定接球墊之材質係選自於
1239620
、申請專利範圍 銅與銅合金之組群。 6球inn範=1項所述之球格陣列封裝基板之接 =七成方法，其中該些重界定接球墊上形成有一錄/ 7球範圍第1項所述之球格陣列封裝基板之接 其中該些抗姓罩幕係由-乾膜經曝光顯 8、一種球格陣列封裝基板，其包含有： <1 旎赵:其係具有一接球表面，該接球表面係形成有 複數個接球端； ~ 層’其係形成於該接球表面上，該防銲層具有 複數個開口，以顯露該些接球端；及 1复數個重界定接球墊，設於該防銲層之該些開口且係 連接於該些接球端上，用以結合銲球。 9如申明專利範圍第8項所述之球格陣列封裝基板，其 中該些重界疋接球墊之周邊係延伸至該防銲層上。 1 〇、如申請專利範圍第8項所述之球格陣列封裝基板，其 中4些重界定接球墊之厚度係介於3 · 〇〜5 · 〇微米。 11、如申請專利範圍第8或丨〇項所述之球格陣列封裝基 板’其中該些重界定接球墊係由一無電鍍金屬層所形 成。 1 2、如申請專利範圍第8或丨〇項所述之球格陣列封裝基 板’其中該些重界定接球墊係由一濺鍍金屬層所形 成0
第14頁 1239620
、申請專利範圍 13 中#1 =專利範圍第8項所述之球格陣列封裝基板，其 群。二界疋接球塾之材質係選自於銅與銅合金之組 4 2 ”奢專利範圍第8項所述之球格陣列封裝基板，其中 U些重界定接球墊上形成有一鎳/金層。
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