TWI239576B - Packaging of stack-type flash memory chip and the method thereof - Google Patents

Packaging of stack-type flash memory chip and the method thereof Download PDF

Info

Publication number
TWI239576B
TWI239576B TW093122554A TW93122554A TWI239576B TW I239576 B TWI239576 B TW I239576B TW 093122554 A TW093122554 A TW 093122554A TW 93122554 A TW93122554 A TW 93122554A TW I239576 B TWI239576 B TW I239576B
Authority
TW
Taiwan
Prior art keywords
flash memory
substrate
memory chip
chip
connection
Prior art date
Application number
TW093122554A
Other languages
English (en)
Other versions
TW200605239A (en
Inventor
Jin-Lung Yu
Hung-Yau Liou
Rung-Hua Shiang
Tzung-Gan Jeng
Original Assignee
C One Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by C One Technology Co Ltd filed Critical C One Technology Co Ltd
Priority to TW093122554A priority Critical patent/TWI239576B/zh
Priority to US11/024,440 priority patent/US20060022324A1/en
Application granted granted Critical
Publication of TWI239576B publication Critical patent/TWI239576B/zh
Publication of TW200605239A publication Critical patent/TW200605239A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06575—Auxiliary carrier between devices, the carrier having no electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)

Description

1239576 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種積體電路晶片封裝，尤指一種堆疊 快閃記憶體晶片封裝及其方法。 且x 5 【先前技術】 積體電路一般係將晶片密封一封裝體中，據以保護晶且 使積體電路易於搞帶及處理’圖i顯示一種稱之為球拇陣列 (Ball Grid Array，BGA)之積體電路封裝，其中，晶片^係 10 5又置在一基板12上，基板12下方設有多個錫球13，並且晶片' 11是以其非作用（inactive)面與基板12相接，而晶片丨丨之作用 (inactive)面之兩側則具有打線墊（b〇nd pad)14，以藉由打線 15將打線墊14連接至基板12之連接線路16，進而電性連接至 錫球13，且以封膠17密封晶片π及打線15等，而構成一積體 15 電路封裝。 ' 版 而為了提升積體電路封裝之密度，如圖2所示，遂有將 兩曰曰片1 1 1及112重豐並密封在一封裝體之設計，為使晶片 111或112之作用（inactive)面不會因堆疊之架構而被遮蔽，一 般係將兩晶片m及112以背對背之方式將其非作用（mactive) 20面疊置在一起，在此一架構下，下面之晶片112的打線墊21 必須直接設在基板12上，故難以藉由打線來電性連接基板 12,因此，而必須使用覆晶（flip chip)形式之晶片，因此導 致價格昂貴之缺失。 Ϊ239576 【發明内容】 片封ίΓΓ之主要目的係在提供一種堆疊式快閃記憶體晶 及其方法，俾能實現低成本及高密度之晶片封裝。 10 15 3本發明之-特色，所提出之堆疊式快閃記憶體晶片 2方法包括步驟：⑷提供—基板’該基板中預設有連接 :，(Β)將一第一快閃記憶體晶片設置於該基板上，1中， ^ 第一快閃記憶體晶片係以其非作用面黏著於基板，且該快 ^己憶體晶片所具有之多數打線墊均設置於其作用面上之 (C)將弟一快閃5己憶體晶片錯位地設置於該第一快 閃記憶體晶片上’以使該第二快閃記憶體晶片僅遮蓋住該第 -快閃記憶體晶片之一部份作用面，但不遮蓋住該該第一快 閃記憶體晶片之多數打線墊’其中，該第二快閃記憶體晶片 係以其非作用面黏著於該第_快閃記憶體晶片上，且該第二 快閃記憶體晶片所具有之多數打線塾均設置於其作用面I 之一側；以及⑼以打線分別將該第—快閃記憶體晶片之打 線塾及該第二快閃記憶體晶片之打線塾連接至基板之連接 線路。 依據本發明之另-特色，所提出之堆疊式快閃記憶體晶 片封裝包括：一基板，其中預設有連接線路；一第一快閃記 20憶體晶片，係設置於該基板上，其中，該第一快閃記憶體晶 片係以其非作用面黏著於基板，且該快閃記憶體晶片所且有 之多數打線㈣設置於其作用面上之_側；—第二快閃記憶 體晶片，係錯位地設置於該第一快閃記憶體晶片上，以使該 第二快閃記憶體晶片僅遮蓋住該第—快閃記憶體晶片之一 1239576 部份作用面，但不遮蓋住該該第一快閃記憶體晶片之多數打 線墊，其中，该第二快閃記憶體晶片係以其非作用面黏著於 孩第一快閃記憶體晶片上，且該第二快閃記憶體晶片所具有 之多數打線墊均設置於其作用面上之一側；以及，打線了其 分別將該第一快閃記憶體晶片之打線墊及該第二快閃記憶 體晶片之打線墊連接至基板之連接線路。 10 依據本發明之再-肖色，戶斤提出之堆疊式快閃記憶體晶 片封裝方法包括步驟··（A)提供一基板，基板中預設有連接 、、、良路/、中，邛为連接線路係位於基板之内圍處、而其餘部 分連接線路則位於基板之外圍處；（B)將一控制晶片設置於 基板上，其中，該控制晶片上具有多數打線墊，·（C)以打線 將該控制晶片之打線墊連接至位於基板之内圍處的連接線 ，’·（D)以封膠局部地灌注於設有該控制晶片之基板處，而 密封該控^晶m線，但不遮蓋住位於基板之外圍處之連 接線路，並將封膠固化；（E)將一快閃記憶體晶片設置於.該 化之封膠上’其中’该快閃記憶體晶片上具有多數打線墊； ⑺以打線將該快閃記憶體晶片之打線墊連接至位於基板之 外圍處的連接線路；以及（G)以封膠密封該快閃記憶體晶片 及打線，並將封膠固化而構成一積體電路封裝。 依據本發明之又-特色，所提出之堆疊式快閃記憶體晶 片封裝包括：-基板，其中預設有連接線路，部分連接線路 係位於基板之内圍處'而其餘部分連接線路則位於基板之外 圍處；-控制晶片，係設置於基板上，其中，該控制晶片上 具有多數打線墊；-快閃記憶體晶片，係設置於該控制晶片 20 1239576 上，其中，該快閃記憶體晶片上具有多數打線墊；打線，係 分別將該控制晶片之打線墊連接至位於基板之内圍處的連 接線路，及將該快閃記憶體晶片之打線塾連接至位於基板之 外圍處的連接線路；以及，封膠，其密封該控制晶片、快閃 5記憶體晶片及打線。 【實施方式】 為月匕讓貝審查委員能更瞭解本發明之技術内容，特舉 較佳具體實施例說明如下。 10 有關本發明之堆疊式快閃記憶體晶片封裝及其方法，請 先參照圖3所示之一較佳實施例，其中圖从〜邛說明了形成 此堆豐式快閃記憶體晶片封裝之步驟。 如圖3A，其首先提供一基板3〇1，基板％下之兩側設 有多數連接墊302’且基板3()1中預設有連接於該等連接塾 15搬之連接線路303，基板如上之中央部分係印設有黏著體 (elastomer)304 〇 如圖3B ’其將一第一快閃記憶體晶片305置於印設有黏 著體304處之基板3〇1上，並將黏著體3〇4固化，而使該第一 快閃記憶體晶片305固設於基板3〇1上。其中，快閃記憶體晶 20片3〇5係以其非作用面則黏著於基板3〇1，且此快閃記憶體 晶片305所具有之多數打線墊3〇6均設置於其作用面”“上 之一側，此種快閃記憶體晶片3〇5係例如為抓麵型快閃 記憶體晶片。 1239576 如圖3C，其將黏著體3〇4印設於該第一快閃記憶體 305之作用面3051上。 a —如圖3D，其將一第二快閃記憶體晶片3〇7置於印設有黏 著體3〇4處之第一快閃記憶體晶片305上，並將黏著體3〇4固 5化，而使該第二快閃記憶體晶片3〇7固設於第一快閃記憶體 曰曰片305上。其中，第二快閃記憶體晶片3〇7係錯位地置於嗲 ^峨憶體晶片305上，而僅遮蓋住該第一快閃記二 晶片305之一部份作用面3〇51，但不遮蓋住該第一快閃記憶 體晶片305之多數打線塾3〇6。又第二快閃記憶體晶片則= 10以其非作用面3072黏著於第一快閃記憶體晶片3〇5上，同樣 地，第二快閃記憶體晶片3〇7所具有之多數打線墊308均設置 於其作用面3071上之一側（例如為AG_AND型快閃記憶體晶 片），而由於第二快閃記憶體晶片3〇7係以其非作用面別”黏 接於第一快閃記憶體晶片3〇5之作用面3〇51，因此，第二快 15閃記憶體晶片307之打線墊308係對向於該第一快閃記憶體 晶片305之打線墊306。 如圖3E，其以打線309分別將第一快閃記憶體晶片3〇5 之打線墊306及第二快閃記憶體晶片3〇7之打線墊3〇8連接至 基板301之連接線路303，進而電性連接至連接墊3〇2。 2〇 如圖奸，最後以封膠310密封第―、第二快閃記憶體晶 片305、307及打線309等，並將封膠31〇固化而構成一積體電 路封裝。 、一 二快閃記憶體晶 且由於第一、第 以前述之積體電路封裝，由於第一、第 片305、307係疊置在一起而可縮減其面積， 1239576 一快閃記憶體晶片305、3 07之打線墊306、308均朝同一方向 (背向基板301)，因此，可以使用打線3〇9輕易地將第一、三 二快閃記憶體晶片305、307電性連接至基板3〇1，而無須= 用覆晶形式之晶片，因而有效降低之製造之成本。 5 再請參照圖4所示之另一較佳實施例，其中圖4八〜好說
明了形成此堆疊式快閃記憶體晶片封裝之步驟。 W 如圖4A，其首先提供一基板4〇丨，基板4〇丨下之兩側設 有多數連接墊402,且基板401中預設有互相連接及於該等連 接墊402之連接線路4〇3，且部分連接線路4〇3係位於基板 ίο之較内圍處、而其餘部分連接線路4〇3則位於基板4〇1之較外 圍處，基板401上之中央部分係印設有黏著體4〇4。 如圖4B，其將一控制晶片4〇5置於印設有黏著體4〇4處 之基板401上，並將黏著體404固化，而使該控制晶片4〇5固 設於基板401上。其中，此控制晶片4〇5上具有多數打線墊 15 406，其係設置於控制晶片4〇5上之兩側（或四周），於此步 驟，亦可將其他電子元件411設置於基板4〇1上。 如圖4C，其以打線4〇9分別將控制晶片4〇5之打線墊4〇6 及電子兀件411連接至位於基板4〇1之較内圍處的連接線路 403，進而電性連接至連接墊4〇2。 10 如圖4D ’其將封膠410局部地灌注於設有控制晶片405 之基板401處，而僅密封該控制晶片4〇5、電子元件411及打 線409等，使得封膠41〇不遮蓋住位於基板4〇1之較外圍處之 連接線路403，並將封膠41〇固化。 如圖4E ’其將黏著體404’印設於該固化之封膠41 〇上。 10 1239576 如圖4F，一快閃記憶體晶片4〇7置於印設有黏著體4〇4, 之固化封膠410上，並將黏著體4〇4，固化，而使該快閃記憶 體晶片407固设於控制晶片405及電子元件411之上，此快閃 記憶體晶片407上具有多數打線墊4〇8，其係設置於快閃記憶 5 體晶片407上之兩側（或四周）。 如圖4G，其以打線409，將快閃記憶體晶片4〇7之打線墊 408連接至位於基板401之較外圍處的連接線路4〇3，進而電 性連接至連接墊402及該控制晶片4〇5與電子元件411。 10 15 20 如圖4H，其以封膠410,密封該快閃記憶體晶片4〇7及打 線409等，並將封膠41〇,固化而構成一積體電路封裝。 以前述之積體電路封裝，由於控制晶片4〇5與快閃記憶 體晶片407係疊置在一起而可縮減其面積，且因相對於控制 晶片405,快閃記憶體晶片4〇7具有相當大之面積，因此，將 快閃記憶體晶片407疊置於控制晶片彻上q允許控制曰片 4〇5之打線連接及其他電子元件411之設置均在快心憶 體晶片術所涵蓋之面積下，使得整體面積之使用率更為有 效，且以使用打線409、4〇9，輕易地將控制晶片彻及快閃圮 憶體晶片407電性連接至基板，而無須採用覆晶形式之°曰 片，因而有效降低之製造之成本。 曰曰 上述實施例僅係為了方便說明而舉例而已，本發 張之權利範圍自應以巾請專利範圍所述為準，而非僅 述實施例。 、上 【圖式簡單說明】 11 1239576
體晶片封裝之步驟。 較佳實施例以形成堆疊式快 閃記憶 較佳實施例以形成堆疊式快 5圖4A〜4H係本發明之另一 憶體晶片封裝之步驟。 【主要元件符號說明】 晶片 11、111、112 基板 12、301、401 10 锡球 13 打線墊 14、306、308、406、408 打線 15、309、409、409， 連接線路16、303、403 封膠 17、310、410、410， 連接墊302、402 黏著體304、404、404， 15 快閃記憶體晶片305、307、407 非作用面3052、3072 作用面3051 、3071 控制晶片405 電子元件41 1 12

Claims (1)

1239576 亥弗一、第二快閃記憶體晶片及打線， 亚將封.口化而構成一積體電路封裝。 中：·:;申二專/]範圍第1項所述之方法，其中，於步驟㈧ 中，該基板下设有多數連接塾， 於該等連㈣。 且基板中之ϋ接線路係連接 6一一種堆疊式快閃記憶體晶片封裝，包括： 一基板，該基板中預設有連接線路； ίο 15 20 -第-快閃記憶體晶片，設置於該基板上，其中，該第 一快閃記憶體晶片係以其非作用面黏著於基板，且躲 憶體晶片所具有之多數打線墊均設置於其作用面上U側. 體一快閃記憶體晶片，錯位地設置於該第一快閃記憶 記情體曰/r 一=—快閃記憶體晶片僅遮蓋住該第一快閃 声曰Η阳。卩份作用面，但不遮蓋住該該第一快閃記情 體日日片之多數打線墊，其中，該 ^ ，作用面黏著於該第一快閃記 其 :體：所具有之多數打線墊均設置於其二= 打線’其分別將該第—快閃記憶體晶片之打線墊及 —'閃記憶體日日日片之打線塾連接至基板之連接、線路。χ 二如申請專利範圍第6項所述之堆疊式 其更包含封膠以密封該第-、第二快閃記憶體:： 14 1239576 8.如申請專利範圍第6項所述之堆疊式快閃記憶體晶 片封裝，其中，該基板下設有多數連接墊，且基板中之連接 線路係連接於該等連接墊。 9· 一種堆疊式快閃記憶體晶片封裝方法，包括步驟： 5 (A)提供一基板，基板中預設有連接線路，其中，部分 連接線路係位於基板之内圍處、而其餘部分連接線路則位於 基板之外圍處； (B)將一控制晶片設置於基板上，其中，該控制晶片上 具有多數打線塾； 10 (c)以打線將該控制晶片之打線墊連接至位於基板之内 圍處的連接線路； —(D)以封膠局部地灌注於設有該控制晶片之基板處，而 密封該控制晶片及打線’但不遮蓋住位於基板之外圍處之連 接線路，並將封膠固化； 15 (E)將一快閃記憶體晶片設置於該固化之封膠上，其 中，該快閃記憶體晶片上具有多數打線墊； (F)以打線將該快閃記憶體晶片之打線墊連接至位於基 板之外圍處的連接線路；以及 ⑼以封膠密封該快閃記憶體晶片及打線，並將封膠固 20化而構成一積體電路封裴。 '如中請專利範圍第9項所述之方法，其中，於步驟 °亥控制晶片係藉由黏著體而固設於該基板上。 15 1239576 11·如申請專利範圍第9項 、之方法，立中，於舟驟 (E)中，該快閃記憶體晶片係葬 T 於々驟 月係错由黏著體而固設於該固化之 封膠上。 12·如申請專利範圍第9項 5 10 、丄 沿^入 万法，其中，於步驟 (Β)中，更包含將至少一電子元件机 ^ 丁兀仟叹置於該基板上。 13. 如申請專利範圍第9項 丄 丨4 <方法，其中，於步驟 (Α)中，該基板下設有多數連接墊， ^ ^ ^ ^ , 且基板中之連接線路係 互相連接及連接於該等連接墊。 14. 一種堆疊式快閃記憶體晶片封裝，包括·· 一基板’該基板巾預财連接線路，其巾，部分連接線 路係位於基板之内圍處、*其餘部分連接線路則位 外圍處； -控制晶片，設置於基板上，其中，該控制晶片 多數打線墊； 15 一快閃記憶體晶片，設置於該控制晶片上，其中，該快 閃㊂己憶體晶片上具有多數打線塾； 打線，係分別將該控制晶片之打線墊連接至位於基板之 内圍處的連接線路，及將該快閃記憶體晶片之打線墊二接至 位於基板之外圍處的連接線路；以及 20 封膠’密封該控制晶片、快閃記憶體晶片及打線。 15·如申請專利範圍第14項所述之堆疊式快閃記憶體 晶片封裝，其更包含設置於該基板上且位於該快閃記憶體晶 片所涵蓋之面積下之至少一電子元件。 16 1239576 16.如申請專利範圍第14項所述之堆疊式快閃記憶體 晶片封裝，其中，該基板下設有多數連接墊，且基板中之連 接線路係互相連接及連接於該等連接墊。 17
TW093122554A 2004-07-28 2004-07-28 Packaging of stack-type flash memory chip and the method thereof TWI239576B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW093122554A TWI239576B (en) 2004-07-28 2004-07-28 Packaging of stack-type flash memory chip and the method thereof
US11/024,440 US20060022324A1 (en) 2004-07-28 2004-12-30 Stacked flash memory chip package and method therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW093122554A TWI239576B (en) 2004-07-28 2004-07-28 Packaging of stack-type flash memory chip and the method thereof

Publications (2)

Publication Number Publication Date
TWI239576B true TWI239576B (en) 2005-09-11
TW200605239A TW200605239A (en) 2006-02-01

Family

ID=35731195

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093122554A TWI239576B (en) 2004-07-28 2004-07-28 Packaging of stack-type flash memory chip and the method thereof

Country Status (2)

Country Link
US (1) US20060022324A1 (zh)
TW (1) TWI239576B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI401783B (zh) * 2007-07-09 2013-07-11 Micron Technology Inc 封裝半導體組件及製造該組件之方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI481002B (zh) * 2012-06-26 2015-04-11 矽品精密工業股份有限公司 具堆疊結構之封裝件及其製法
US11301151B2 (en) * 2020-05-08 2022-04-12 Macronix International Co., Ltd. Multi-die memory apparatus and identification method thereof
CN113823604A (zh) * 2021-08-06 2021-12-21 紫光宏茂微电子(上海)有限公司 芯片堆叠封装件及其制作方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4103796B2 (ja) * 2003-12-25 2008-06-18 沖電気工業株式会社 半導体チップパッケージ及びマルチチップパッケージ

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI401783B (zh) * 2007-07-09 2013-07-11 Micron Technology Inc 封裝半導體組件及製造該組件之方法
US8629054B2 (en) 2007-07-09 2014-01-14 Micron Technology, Inc. Packaged semiconductor assemblies and methods for manufacturing such assemblies
US9911696B2 (en) 2007-07-09 2018-03-06 Micron Technology, Inc. Packaged semiconductor assemblies and methods for manufacturing such assemblies
US10622308B2 (en) 2007-07-09 2020-04-14 Micron Technology, Inc. Packaged semiconductor assemblies and methods for manufacturing such assemblies

Also Published As

Publication number Publication date
TW200605239A (en) 2006-02-01
US20060022324A1 (en) 2006-02-02

Similar Documents

Publication Publication Date Title
US6462412B2 (en) Foldable, flexible laminate type semiconductor apparatus with reinforcing and heat-radiating plates
US7408245B2 (en) IC package encapsulating a chip under asymmetric single-side leads
TW557556B (en) Window-type multi-chip semiconductor package
TWI260076B (en) Semiconductor package device and method of formation and testing
TW432558B (en) Dual-chip packaging process and method for forming the package
JP2007243196A (ja) 複数のチップ構成を有する集積デバイス及びその製造方法
US20080009096A1 (en) Package-on-package and method of fabricating the same
TWI239576B (en) Packaging of stack-type flash memory chip and the method thereof
US20030015803A1 (en) High-density multichip module and method for manufacturing the same
TW200807682A (en) Semiconductor package and method for manufacturing the same
JP2010147225A (ja) 半導体装置及びその製造方法
TWI711131B (zh) 晶片封裝結構
TWI260069B (en) Memory module and method for manufacturing the same
TW200836306A (en) Multi-chip stack package
TW201330220A (zh) 具凹槽之封裝結構及其製造方法
CN216871946U (zh) Bga芯片的粘结结构
TWI250597B (en) Method for manufacturing multi-chip package having encapsulated bond-wires between stack chips
TW200810036A (en) IC stack package having a plurality of encapsulants sharing a same substrate
TW200537658A (en) Semiconductor package
TWI501379B (zh) 共用封膠體之封裝層疊構造
TWI227554B (en) Flip-chip package with integration of passive component
US7781898B2 (en) IC package reducing wiring layers on substrate and its chip carrier
TW200926389A (en) Back-to-back stacked multi-chip package and method for fabricating the same
TW200828561A (en) Stacked-chip package structure
KR20230016089A (ko) 반도체 패키지

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees