TWI237886B - Bonding pad and chip structure - Google Patents

Bonding pad and chip structure Download PDF

Info

Publication number
TWI237886B
TWI237886B TW093120184A TW93120184A TWI237886B TW I237886 B TWI237886 B TW I237886B TW 093120184 A TW093120184 A TW 093120184A TW 93120184 A TW93120184 A TW 93120184A TW I237886 B TWI237886 B TW I237886B
Authority
TW
Taiwan
Prior art keywords
bonding pad
wafer
item
patent application
scope
Prior art date
Application number
TW093120184A
Other languages
English (en)
Other versions
TW200603364A (en
Inventor
Chiu-Shun Lin
Guan-Jou Lin
Chia-Hui Wu
Pai-Sheng Cheng
Original Assignee
Himax Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Himax Tech Inc filed Critical Himax Tech Inc
Priority to TW093120184A priority Critical patent/TWI237886B/zh
Priority to US10/711,674 priority patent/US7064449B2/en
Priority to JP2004295273A priority patent/JP2006024877A/ja
Priority to KR1020040080692A priority patent/KR20060003801A/ko
Application granted granted Critical
Publication of TWI237886B publication Critical patent/TWI237886B/zh
Publication of TW200603364A publication Critical patent/TW200603364A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Description

1237886 13689twf.doc 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種接合墊(b0nding pad)及晶片結 構，且特別是有關於一種具有不同幾何形狀的接合墊及晶 片結構。#， 【先前技術】 近數十年來，電子技術發展的速度令人驚奇。尤其 是在積體電路(Integrated Circuit，1C)的製程技術上，進步 更疋神速，這使得電子元件的功能快速上昇，然而成本卻 能快速下降。 一般來說，半導體製程可分為前段製程及後段製程， 前段製程包括光罩(Mask)的製作、氧化(〇xidati〇n)、微影 (Photolithography)、蝕刻（Etching)、沈積(Dep〇siti〇n)、摻 雜(Doping)等。為建立晶片的輸入/輸出(111邮/〇_叭ι/〇) 通路，目前較普遍的作法是在晶片的輸入/輸出接合墊上 形成一凸塊，用以和外部電路相連接。 圖1、、’a示為4知晶片結構的剖面示意圖。請來昭 圖1，此晶片結構100包括一晶片12〇、一接合墊14〇了 一凸塊180以及一保護層160。接合墊14〇配置於晶片 之主動表面122上’用於晶片12G之訊號的輸入/輸出。 保護層16(H系配置於主動表自122上且暴露接合墊14〇。 凸塊180係配置於接合墊14〇上並與其電性連接。 圖2繪示為圖1之接合墊的示意圖。請同時參昭圖工 與圖2 ’習知技射接合塾14〇之形狀皆為平板狀。以液 1237886 13689twf.doc 晶顯不器之驅動晶片為例，其通常係以熱壓著（therm〇 compression)之方式接合至液晶顯示器的玻璃'基板（圖未示) 上。在晶片120以熱壓著方式接合至玻璃基板時，由於凸 塊ISO、·接合墊M0以及保護層16〇之間存在熱膨脹係數 (Coefficient of Thermal Expansion，CTE)的差異，因此很容 易導致熱應力產生在三者之間。其巾，尤哺合墊i4〇之 轉角處特別容易產生應力集中現象。 因此 畜接令蟄14〇以平整的上表面與保護層160、 凸塊18G接合時’闕別容易在接合墊⑽之轉角處發生 凸塊與接σ塾間的電性連接受到破壞關題。由於接合塾 140係用以將信號由晶片輸人/輸出，因此當凸塊與接合 =的電性連接如破壞時，就會降低整個電子產品的可 办又。，外’當保護層122受熱應力之破壞而產生破裂 (1二日ϋ外界的1氣也容易從破裂處渗入晶片12。内， 二;2之彳貝帛°所以’如何降低熱應力對晶片結構 100所造成的財便成為當務之各。 【發明内容】 〜 八墊2侦月的就是在提供-種接合墊，適於加強♦接 合塾，其他導體間電性連接的 本發明的再一目的3 又 晶片結構與其他组件供—種晶片結構，適於加強 基於上述目的，連接的可靠度。 在一晶片之一主動表明提出一種接合墊，適於配置 體部以及多個第一突。此接合墊主要係由一多邊形本 ΙΑ所構成。多邊形本體部具有一第 1237886 13689twf.doc 一平面及相對應之一第二平面，且多邊形本體部係以第二 平面接觸晶片而配置於晶片上。這些第一突起部配置於第 一平面上，且分別位於多邊形本體部之角落處。 在本實施例中，接合墊例如更包括一第二突起部， 其配置於第一平面上，且位於多邊形本體部之中央處。其 中，第二突起部例如連接第一突起部。由垂直第一平面之 方向觀之，第二突起部例如係呈圓形、圓環形、多.邊形、 多邊環形或交叉線。多邊形本體部、第一突起部與第二突 起部例如係一體成型。 在本實施例中，接合墊之材質例如係銘。而且，多 邊形本體部之形狀例如係四邊形。 基於上述目的，本發明再提出一種晶片結構，其主 要由一晶片以及至少一接合墊所構成。此晶片具有一主動 表面。接合墊配置於晶片之主動表面上。接合墊主要係由 一多邊形本體部及多個第一突起部所構成。多邊形本體部 具有一第一平面及相對應之一第二平面，且多邊形本體部 係以第二平面接觸晶片而配置於晶片上。這些第一突起部 配置於第一平面上，且分別位於多邊形本體部之角落處·。 在本實施例中，接合墊例如更包括一第二突起部， 其配置於第一平面上，且位於多邊形本體部之中央處。其 中，第二突起部例如連接第一突起部。由垂直第一平面之 方向觀之，第二突起部例如係呈圓形、圓環形、多邊形、 多邊環形或交叉線。多邊形本體部、第一突起部與第二突 起部例如係一體成型。 1237886 13689twf.doc 在本貫例中，接合墊之材質例如係紹。多邊形本 體部，形狀例如係四邊形。而且，此晶片結構例如更包括 保濩層，其配置於晶片之主動表面上，並覆蓋接合墊之 =緣而暴露接合墊之中間處。另外，此晶片結構例如更包 至^二凸塊，其配置於接合墊上並與其電性連接。凸塊 材質例如係金。此外，⑼結構之接合墊例如係以濺鑛 气^成。其中，晶片結構之第一突起部例如係利用一遮 罩以濺鍍方式形成。 、 ^ 综上所述，在本發明之接合墊中，由於多邊形本體 角落處配置有多個第一突起部，因此可增加接合墊在 角落處與後續形成之保護層的接觸面積，進而避免晶片在 與其他7〇件接合時因熱應力的破壞而降低接合良率。 盈為讓本發明之上述和其他目的、特徵和優點能更明 Γ員易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下。 、 【實施方式】 圖3繪不為本發明一較佳實施例之晶片結構的示音、 ，。請參照圖3，晶片結構3〇〇主要由一晶片32〇以及^ =一接合墊340所構成。此晶片320具有一主動表面322， 合塾340配置於晶片320之主動表面322上。 一圖3所繪示的實施例中，晶片結構300例如更包括 =呆護層360，其配置於晶片320之主動表面322上，並 设蓋接合墊340之周緣而暴露接合墊340之中間處，以避 免曰曰片320受到外在環境之污染。另外，晶片結構3〇〇例 1237886 13689twf.doc 如更包括至少一凸塊380，其配置於接合墊340上並與之 電性連接。在此，凸塊380的材質例如可採用金。由於金 所做成之凸塊380可具有較小體積，因此適於增加配置於 晶片320上之接合墊340的密度，進而縮小晶片32〇之體 積。本明較佳實施例之晶片結構3〇〇其特徵在於接合墊 340之成何形狀，接合擎34〇之細部結構將於以下做詳細 敘述。 圖4A繪不為本發明一較佳實施例之接合墊的上視 圖，而圖4B繪示為圖4A之接合墊的前視圖。請同時參 :、、，及圖4B，接合墊340包括一多邊形本體部342 ”夕個第-突起部344 ’且接合墊34()可應用於圖3所示 =、Γ冓綱。多邊形本體部342具有-第-平面_ 签-伞之一第二平面342b，且多邊形本體部342係以 32(Γ :夕34化接觸晶片320 (緣示於圖3)而配置於晶片 且八別位突起部344配置於第一平面342a上， 刀另J位於夕邊形本體部342之角落處。 -定要連接::旦並不限定第二突起部346 多邊形本體部342與第—突起^然，接合塾34G也可僅由 二突起部346。接合墊34〇之^44所構成’而不包括第 部342之形狀例如為四邊带。材質例如為銘。多邊形本體 1237886 13689twf.doc -突起邱為第二突起部346的各種形狀。第 一大起？6例如係呈圓形—、 346c、多邊環形346d或交又線她等。 夕柄 -夂了為接合墊與保護層接觸的局部放大示意圖。 二』5’當保護層360形成於接合墊340上後， 積。HI :::保護層360與接合墊340的接觸面 熱而產生執;二=在與其他元件接合的過程中受 =:;:度’同時解決伴隨保護層，破裂 亩妓5的疋’圖3所緣示之凸塊38G並非限定為 =接合墊34。接觸，亦可於接合塾 i =二質例如為鈦化嫣⑽)。凸塊380材質也
所入、可使用錫等其他合適的材料為材質。圖4A =曰=2墊340其多邊形本體部W並不限定為四邊 4C所洛外、他介的形狀。第二突起部346的形狀除了如圖 C所綠不外，亦可為任何其他合適的形狀。 3二稍做變化，以獲得如圖Μ所示具有第一突 接:墊二起部346之接合墊。以下將就本發明之 供口墊的製造方法做詳細介紹。 圖6緣示為本發0狀接合墊其製造方法的示意圖。 1237886 13689twf.doc 叫參照圖6 ’本發明之接合墊340的製造方法係於濺鍍機 中增δ又一遮罩620。遮罩620上形成有至少一鐘空部622。 此鏤空部622之形狀係對應所欲形成之第一突起部344以 及第二突起部346的形狀。本發明之接合墊34〇的製造方 法係先丨敗鑛形成接合墊340之多邊形本體部342，此時尚 未定義多邊形本體部342之形狀。之後，將遮罩62〇配設 於靶材640及多邊形本體部342之間，並且繼續進行濺鍍。 如此-來，科錄材_上賴出之材料即可通過鏤空 部622’最終沈積在多邊形本體部如的第一表面遍 上。 種接合墊之製作方法可不紐賴外的光罩，因 中為it製日 =罩所需之時間與成本。需注意的是，圖 中為求，早明瞭故只晝出單—接合墊34。及單_鎮空部 622之St際製程中’可同時使用形成有多個鏤空部 之=?，以-次形成多個至少具有第-突起細 墊之=於具在有=^^ 績與保護層之接觸面積。如此—來，春:θ力接α塾在後 元件接合時，就可避免熱應力在在與其他 層與接合墊受到破壞的問題 轉角處造成保護 之第二突起部可以使接合墊的結構更:力= 妾第-突起部 明之接合墊的製造方法中，t強。而且’本發 因此不會增加接合墊製作之成本。額外的光罩製程， 1237886 13689twf.doc 雖然本發明已以較佳實施例揭露如上，然其並非用 以限^本發明，任何熟習此技藝者，在不麟本發明之精 神和祀圍内，當可作些許之更動與潤飾，因此本發明之保 護範圍當概附之巾料利範_界定者為準。 【圖式籐單說明】 圖1、、、曰示為一習知晶片結構的剖面示意圖。 圖2繪不為圖1之接合墊的示意圖。
圖3繪示為本發明—較佳實施例之晶片結構的示意 圖。 圖4A !會不為本發明一較佳實施例之接合塾的上視 圖4B繪示為圖4A之接合塾的前視圖。 圖4C緣示為第二突起部的各種形狀。 圖5繪示為接合墊與保護層翻的局部放大示意圖 圖6繪示為本發明之接合墊其製造方法的示意圖。 【主要元件符號說明】
100 :晶片結構 120 ·晶片 122 ·主動表面 140 :接合墊 160 :保護層 180 :凸塊 300 ·晶片結構 320 ·晶片 12 1237886 13689twf.doc 322 ··主動表面 340 :接合墊 342 :多邊形本體部 342a :第一平面 342b :第二平面 344 ··第一突起部 346 :第二突起部 346a ··圓形 346b ··圓環形 346c :多邊形 346d :多邊環形 346e :交叉型 350 :黏著層 360 :保護層 380 ·•凸塊 620 :遮罩 622 :鏤空部 640 ··靶材 13

Claims (1)

1237886 13689twf.doc 十、申請專利範圍： 1. 一種接合墊，適於配置在一晶片之一主動表面上， 該接合藝包括： 一多邊形本體部，具有一第一平面及相對應之一第 二平面V且該多邊形本體部係以該第二平面接觸該晶片而 配置於該晶片上；以及 多數個第一突起部，配置於該第一平面上，且分別 位於該多邊形本體部之角落處。 2. 如申請專利範圍第1項所述之接合墊，更包括一第 二突起部，配置於該第一平面上，且位於該多邊形本體部 之中央處。 3. 如申請專利範圍第2項所述之接合墊，其中該第二 突起部連接該些第一突起部。 4. 如申請專利範圍第2項所述之接合墊，其中由垂直 該第一平面之方向觀之，該第二突起部係呈圓形、圓環形、 多邊形、多邊環形與交叉線其中之一。 5. 如申請專利範圍第3項所述之接合墊，其中由垂直 該第一平面之方向觀之，該第二突起部係呈圓形、圓環形、 多邊形、多邊環形與交叉線其中之一。 6. 如申請專利範圍第2項所述之接合墊，其中該多邊 形本體部、該些第一突起部與該第二突起部係一體成型。 7. 如申請專利範圍第1項所述之接合墊，其中該多邊 形本體部與該些第一突起部係一體成型。 8. 如申請專利範圍第1項所述之接合墊，其材質包括 14 1237886 13689twf.doc 構，其中該接合墊係一體成型。 16. 如申請專利範圍第10項所述之晶片結構，其中該 接合墊之材質包括鋁。 17. 如申請專利範圍第10項所述之晶片結構，其中該 多邊形本體部之形狀包括四邊形。 18. 如申請專利範圍第10項所述之晶片結構，更包括 一保護層，配置於該晶片之該主動表面上，並覆蓋該接合 墊之周緣而暴露該接合墊之中間處。 19. 如申請專利範圍第10項所述之晶片結構，更包括 至少一凸塊，配置於該接合墊上並與其電性連接。 20. 如申請專利範圍第19項所述之晶片結構，其中該 凸塊之材質包括金。 21. 如申請專利範圍第10項所述之晶片結構，其中該 接合墊係以藏鍵方式形成。 22. 如申請專利範圍第21項所述之晶片結構，其中該 第一突起部係利用一遮罩，以濺鍍方式形成。
TW093120184A 2004-07-06 2004-07-06 Bonding pad and chip structure TWI237886B (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
TW093120184A TWI237886B (en) 2004-07-06 2004-07-06 Bonding pad and chip structure
US10/711,674 US7064449B2 (en) 2004-07-06 2004-09-30 Bonding pad and chip structure
JP2004295273A JP2006024877A (ja) 2004-07-06 2004-10-07 ボンディングパッドとチップ構造
KR1020040080692A KR20060003801A (ko) 2004-07-06 2004-10-09 본딩 패드 및 칩 구조체

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW093120184A TWI237886B (en) 2004-07-06 2004-07-06 Bonding pad and chip structure

Publications (2)

Publication Number Publication Date
TWI237886B true TWI237886B (en) 2005-08-11
TW200603364A TW200603364A (en) 2006-01-16

Family

ID=35540449

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093120184A TWI237886B (en) 2004-07-06 2004-07-06 Bonding pad and chip structure

Country Status (4)

Country Link
US (1) US7064449B2 (zh)
JP (1) JP2006024877A (zh)
KR (1) KR20060003801A (zh)
TW (1) TWI237886B (zh)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE602004028349D1 (de) * 2003-03-04 2010-09-09 Rohm & Haas Elect Mat Koaxiale wellenleitermikrostrukturen und verfahern zu ihrer bildung
DE10333465B4 (de) * 2003-07-22 2008-07-24 Infineon Technologies Ag Elektronisches Bauteil mit Halbleiterchip, Verfahren zur Herstellung desselben sowie Verfahren zur Herstellung eines Halbleiterwafers mit Kontaktflecken
KR101476438B1 (ko) 2006-12-30 2014-12-24 누보트로닉스, 엘.엘.씨 3차원 미세구조 및 그 형성방법
EP1973189B1 (en) 2007-03-20 2012-12-05 Nuvotronics, LLC Coaxial transmission line microstructures and methods of formation thereof
US7755174B2 (en) 2007-03-20 2010-07-13 Nuvotonics, LLC Integrated electronic components and methods of formation thereof
CN101336042B (zh) * 2007-06-29 2012-05-16 鸿富锦精密工业（深圳）有限公司 焊盘、具有该焊盘的电路板和电子装置
KR101585962B1 (ko) * 2009-04-29 2016-01-15 주식회사 동부하이텍 반도체 소자의 본딩 패드 구조 및 패드 형성 방법
US20110123783A1 (en) 2009-11-23 2011-05-26 David Sherrer Multilayer build processses and devices thereof
WO2011091334A2 (en) * 2010-01-22 2011-07-28 Nuvotronics, Llc Thermal management
US8917150B2 (en) * 2010-01-22 2014-12-23 Nuvotronics, Llc Waveguide balun having waveguide structures disposed over a ground plane and having probes located in channels
US8866300B1 (en) 2011-06-05 2014-10-21 Nuvotronics, Llc Devices and methods for solder flow control in three-dimensional microstructures
US8814601B1 (en) 2011-06-06 2014-08-26 Nuvotronics, Llc Batch fabricated microconnectors
KR101982887B1 (ko) 2011-07-13 2019-05-27 누보트로닉스, 인크. 전자 및 기계 구조체들을 제조하는 방법들
US9825194B2 (en) * 2012-05-29 2017-11-21 Essence Solar Solutions Ltd. Self aligning soldering
US9325044B2 (en) 2013-01-26 2016-04-26 Nuvotronics, Inc. Multi-layer digital elliptic filter and method
US9306255B1 (en) 2013-03-15 2016-04-05 Nuvotronics, Inc. Microstructure including microstructural waveguide elements and/or IC chips that are mechanically interconnected to each other
US9306254B1 (en) 2013-03-15 2016-04-05 Nuvotronics, Inc. Substrate-free mechanical interconnection of electronic sub-systems using a spring configuration
US9349710B2 (en) * 2013-10-07 2016-05-24 Xintec Inc. Chip package and method for forming the same
KR20160133422A (ko) 2014-01-17 2016-11-22 누보트로닉스, 인크. 웨이퍼 규모 테스트 인터페이스 유닛 및 컨택터
US10847469B2 (en) 2016-04-26 2020-11-24 Cubic Corporation CTE compensation for wafer-level and chip-scale packages and assemblies
WO2016094129A1 (en) 2014-12-03 2016-06-16 Nuvotronics, Inc. Systems and methods for manufacturing stacked circuits and transmission lines
US10319654B1 (en) 2017-12-01 2019-06-11 Cubic Corporation Integrated chip scale packages
KR102446203B1 (ko) * 2017-12-12 2022-09-23 삼성디스플레이 주식회사 구동칩 및 이를 포함하는 표시 장치

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5348671A (en) * 1976-10-15 1978-05-02 Toshiba Corp Electrode structure of semiconductor element
JPS61172362A (ja) * 1985-01-28 1986-08-04 Seiko Epson Corp ボンデイング電極構造
JPH01165133A (ja) * 1987-12-21 1989-06-29 Seiko Instr & Electron Ltd 半導体装置
US5053850A (en) * 1988-03-14 1991-10-01 Motorola, Inc. Bonding pad for semiconductor devices
US5929521A (en) * 1997-03-26 1999-07-27 Micron Technology, Inc. Projected contact structure for bumped semiconductor device and resulting articles and assemblies
US6246587B1 (en) * 1998-12-03 2001-06-12 Intermedics Inc. Surface mounted device with grooves on a termination lead and methods of assembly
JP2000307373A (ja) * 1999-02-18 2000-11-02 Murata Mfg Co Ltd 表面波装置及びその製造方法
US6297562B1 (en) * 1999-09-20 2001-10-02 Telefonaktieboalget Lm Ericsson (Publ) Semiconductive chip having a bond pad located on an active device
JP2001168125A (ja) * 1999-12-03 2001-06-22 Nec Corp 半導体装置
JP2003209134A (ja) * 2002-01-11 2003-07-25 Hitachi Ltd 半導体装置及びその製造方法
US7008867B2 (en) * 2003-02-21 2006-03-07 Aptos Corporation Method for forming copper bump antioxidation surface

Also Published As

Publication number Publication date
KR20060003801A (ko) 2006-01-11
US20060006531A1 (en) 2006-01-12
US7064449B2 (en) 2006-06-20
JP2006024877A (ja) 2006-01-26
TW200603364A (en) 2006-01-16

Similar Documents

Publication Publication Date Title
TWI237886B (en) Bonding pad and chip structure
US7256503B2 (en) Chip underfill in flip-chip technologies
US7521810B2 (en) Chip stack package and manufacturing method thereof
US8421242B2 (en) Semiconductor package
TW200812448A (en) Flexible electronic assembly
JP5570727B2 (ja) 半導体装置
US8776602B2 (en) Acceleration sensor, semiconductor device and method of manufacturing semiconductor device
WO2021088037A1 (zh) 阵列基板及其制造方法、显示面板、显示装置
TWI311367B (en) Chip structure
TW410451B (en) Semiconductor device with improved pad connection
US20050269680A1 (en) System-in-package (SIP) structure and fabrication thereof
TWI495113B (zh) 具有改良防焊堰體結構之封裝用光學蓋板、影像感測件封裝體及其製作方法
TW519727B (en) Semiconductor wafer, semiconductor device and manufacturing method therefor
US6718604B1 (en) Mounting method for electronic device elements
TWI313049B (en) Multi-chips stacked package
TW200525656A (en) Stacked semiconductor device
JP2003229637A (ja) レーザダイオード装置及びその実装装置
JP2000294593A (ja) 集積回路の端子構造
JP5112659B2 (ja) 加速度センサならびにセンサチップおよびその製造方法
TWI315094B (en) Flip chip package
TWI225695B (en) Structure of flip chip package and structure of chip
US20090057916A1 (en) Semiconductor package and apparatus using the same
US11107759B2 (en) Chip package and manufacturing method thereof
JP2001274317A (ja) 半導体装置及び半導体装置の実装方法
JP2003234371A (ja) 半導体装置の実装構造

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees