TW410451B - Semiconductor device with improved pad connection - Google Patents
Semiconductor device with improved pad connection Download PDFInfo
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- TW410451B TW410451B TW088103984A TW88103984A TW410451B TW 410451 B TW410451 B TW 410451B TW 088103984 A TW088103984 A TW 088103984A TW 88103984 A TW88103984 A TW 88103984A TW 410451 B TW410451 B TW 410451B
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- Prior art keywords
- pad
- contacts
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 239000004020 conductor Substances 0.000 claims 1
- 238000005406 washing Methods 0.000 claims 1
- 239000011229 interlayer Substances 0.000 abstract 3
- 230000002079 cooperative effect Effects 0.000 description 4
- 230000000875 corresponding effect Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 235000015170 shellfish Nutrition 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
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Abstract
Description
A7 B7 410451 五、發明説明(1 ) 本發明係關於一半導體裝置,且更特別地相關於一供 該半導體裝置之輸入/輸出墊用之連接結構。 一般於一封裝的LSI中,一晶片與一封裝體藉由黏合線 而被互連β該晶片被在中心地形成,並且包或一内部邏輯 電路。該晶片的上表面於其外部周邊的四周上形成有多個 I/O墊。這些墊被用來馈送電力至該内部邏輯電路,並且 用來將訊號輸入至該内部邏輯電路及從該内部邏輯電路輸 出。該等墊借助黏合線而與暴露在該封裝體外的引線電極 互連。 —供I/O塾用的傳統連接結構之第一例子將參考第1 (a) 與1 (b)圖來作說明《第1 (a)圖係為該墊丨丨的頂視圖,並且 第1(b)圖係為沿第1(a)圖的線段lb-lb所截取的橫截面圖。 一諸如氧化物薄膜的内層薄膜12被沉積在該墊11之 下’該墊於組構狀態中大致為正方形。一佈線結構13被沉 積在該塾11之下。經由多個沿該墊11各邊對齊的接點接點 14該墊11與該佈線結構13被互連。一未顯示的自動線連接 器將一黏合線15接合至該墊11之一中心區域》 該墊li在位於對應該等接點接點14處之其上表面上具 有多個很淺的凹陷16。當該墊11被形成時,該等凹障16亦 被形成。因為該等凹陷16位於該墊11之外緣的四周,因此 該墊Π的上表面顯出高度平坦,其係確保有供在該墊灯與 該線15間接合用之廣大的面積,因此在該墊11與該線15之 間准許有一可靠的連接。 該墊Π經由沿該墊11的外緣被設置的該等接點接點14 民紙張尺度適用中國國家標準(CNS ) A4規格(210 X 297公釐) (讀先聞讀背面之注意事項一^寫本頁)A7 B7 410451 V. Description of the invention (1) The present invention relates to a semiconductor device, and more particularly relates to a connection structure for an input / output pad of the semiconductor device. Generally in a packaged LSI, a chip and a package body are interconnected by bonding wires. The chip is formed centrally, and a package or an internal logic circuit is formed. The upper surface of the wafer has a plurality of I / O pads formed on the periphery of its outer periphery. These pads are used to feed power to the internal logic circuit and to input signals to and output from the internal logic circuit. The pads are interconnected with lead electrodes exposed outside the package by means of bonding wires. -The first example of a conventional connection structure for I / O will be explained with reference to Figures 1 (a) and 1 (b). "Figure 1 (a) is a top view of the pad, and Figure 1 (b) is a cross-sectional view taken along line lb-lb of Figure 1 (a). An inner layer film 12 such as an oxide film is deposited underneath the pad 11 ' The pad is approximately square in a structured state. A wiring structure 13 is deposited under the coil 11. The pad 11 and the wiring structure 13 are interconnected via a plurality of contact points 14 aligned along each side of the pad 11. An unshown automatic wire connector joins a bonding wire 15 to a central area of the pad 11. The pad li has a plurality of very shallow depressions 16 on the upper surface thereof corresponding to the contact points 14. . When the pad 11 is formed, the concave barriers 16 are also formed. Because the recesses 16 are located around the outer edge of the pad 11, the upper surface of the pad Π appears highly flat, which ensures a large area for joining between the pad lamp and the line 15, so in this A reliable connection is permitted between the pad 11 and the line 15. The pad Π is provided through the contact points 14 along the outer edge of the pad 11. The paper size of the pad applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). ^ Write this page)
,tT •k_ 經濟部中央標準局員工消費合作社印裝 410451 A7 B7 五、發明説明(2 ) 經濟部_央標準局員工消費合作社印製 來與該佈線結構13互連。此即表示在該墊u與該佈線結構 13間的互連數目為少量者,而致使該墊丨丨的低連接強度。 為了提供一較南程度的整合積集度,積體電路使用被製成 較以往更薄的多重佈線結構層與該等接點14。此進一步地 促使該墊11連接強度的縮小。 該塾11被縮小的連接強度在該接合程序中出現了一個 問題。當該連接器將該線15固定至該墊Η上時,一向上的 力藉由該線15而被施加至該整11上,其可將該墊丨丨從該内 層薄膜12上分離’或從該佈線結構13將該内層薄膜12分 離因為從該墊11的中心區域至該佈線結構13沒有經由該 接點14的連接產生,所以該墊11的中心區域格外地容易分 離。 一被設計來抵抗由該線15造成的向上力而呈現一被增 加的強度之傳統墊連接結構之第二例子將參考第2(a)與 2(b)圖來作說明。經由在該塑· Ha整個表面上以相等的間 隔被定置的接點14,一墊11 a被與一佈線結構13互連。在 該墊11 a與該佈線結構13或該等接點14間的互連數目被增 加,並且因此該墊11a被牢固地固定至該佈線結構13上(且 也固定至該内層薄膜12上)。從該内層薄膜12或是該佈線 結構13分離該墊11a被避免,雖然一向上的力仍然在該接 合操作期間被施加至該塾11上。 然而,因為一些對應接點14數目之凹陷在該墊11的 表面上被形成,因此縮小了該墊11 a的表面平坦度,此 縮小在該墊11a的上表面上供與該線15接合用的面積。因 上 即 讀 A 閩 之 注 意 事 項, tT • k_ Printed by the Consumers 'Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 410451 A7 B7 V. Description of the Invention (2) Printed by the Consumers' Cooperative of the Ministry of Economics_Central Bureau of Standards to interconnect this wiring structure 13. This means that the number of interconnections between the pad u and the wiring structure 13 is small, resulting in a low connection strength of the pad. In order to provide a higher degree of integration, the integrated circuit uses multiple wiring structure layers and the contacts 14 which are made thinner than before. This further causes the connection strength of the pad 11 to decrease. The reduced connection strength of the 塾 11 presents a problem in the joining procedure. When the connector fixes the wire 15 to the pad ,, an upward force is applied to the whole 11 through the wire 15, which can separate the pad 丨 丨 from the inner film 12 ′ or The separation of the inner layer film 12 from the wiring structure 13 is not caused by the connection from the central region of the pad 11 to the wiring structure 13 via the contact 14, so the central region of the pad 11 is particularly easy to separate. A second example of a conventional pad connection structure designed to resist an upward force caused by the line 15 and exhibit an increased strength will be described with reference to Figs. 2 (a) and 2 (b). A pad 11a is interconnected with a wiring structure 13 via the contacts 14 positioned at equal intervals on the entire surface of the plastic Ha. The number of interconnections between the pad 11 a and the wiring structure 13 or the contacts 14 is increased, and thus the pad 11 a is firmly fixed to the wiring structure 13 (and also to the inner layer film 12). . Separating the pad 11a from the inner layer film 12 or the wiring structure 13 is avoided, although an upward force is still applied to the toe 11 during the bonding operation. However, because some depressions corresponding to the number of contacts 14 are formed on the surface of the pad 11, the surface flatness of the pad 11a is reduced, and this reduction is provided on the upper surface of the pad 11a for bonding with the wire 15 Area. Because of this, read A Min's notes
# 訂 本紙張尺度適用中國國家標準(CNS ) A4規格(210 X 297公潑) 410451# Order This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 male splash) 410451
五、發明説明( 此’該線15容易與該墊lla分離,而導致該積體電路之可 靠性的降低。 本發明之一目的係提供一具有一被增加的墊連接強度 之半導體裝置。 經濟部中夬標準局員工消費合作杜印製 發明總結 為達成上述目的,本發明提供一半導體裝置,其係包 含:一半導體晶片;一佈線結構,其係形成在該半導遨晶 片上,一内層薄膜,其係被設置在該佈線結構的頂部上; 一塾,係被設置在該内層薄膜之頂部上並包括一外緣與一 中心區域;及多個接點,係被形成在該内層薄膜中,用以 將該墊與該佈線結構互連,該等多個接點係包括以一偏移 的方式被設置而分別沿該墊與在該墊的中心區域中局部地 集中的第一與第二接點羣。 本發明係進一步地提供一半導體裝置,其係包含:一 半導體晶片;一佈線結構,其係被形成在該半導體晶片上; 一内層薄膜,係被設置在該佈線結構的頂部上;一墊,其 係被設置在該内層薄膜的頂部上並包括一外緣與一中心區 域;及第一與第二接點,其係被形成在該内層薄膜之内, 以供將該佈線結構與該墊互連之用,該第一接點係沿該墊 之外緣被設置,且該第二接點在該墊的中心區域被設置》 本發明的其他方面與優點將由下列說明並配合圖示而 變得顯而易見,其係藉由例子來舉例說明本發明之原理。 (諳先聞讀背面之註意事項 3ϋ寫本- 裝· 頁) -訂_ 本紙珉尺度適用中國國家操準(CNS ) Α4規格(210Χ297公釐) 6 經濟部中央標準局貝工消费合作社印製 410451 at B7 五、發明説明(4 ) 圖示之簡短說明 本發明連同其目的與優點藉由參考目前較佳實施例的 下列說明並伴隨後附圖式會得到最佳的領略,在後附圖式 中: 第係為一傳統墊之第一例子之頂視圖; 第為沿第1(a)圖之線段lb-lb所截取之横截面 圖; 、第2(a)圖係為一傳統墊之第二例子之頂視圖; 第2(b)圖係為沿第2(a)圖之線段2b-2b所截取之橫截面 圖, 第3(a)圖係為根據本發明之第一實施例之一 LSI的一部 份之頂視圖; 第3(b)圖係為第3(a)圖之一部份的放大圖;/ 第4(a)圖為顯示第3(a)圖之該LSI之一墊的頂視圖; 第4(b)圖係為沿第4(a)圖之線段4b-4b所截取的橫載面 圖;< 第5(a)至5(d)圖係為根據本發明之其他墊的頂視圖; 第6(a)圖係為根據本發明之又一墊之頂視圖;及 第6(b)圖為沿第6(a)圖所示的線段6b-6b所截取之橫截 面圖。广 較佳實施例之詳細說明 參考第3與4圖,根據本發明之其中一個實施例之一被 封裝的LSI將會被說明。 本紙張尺度適用_國國家標準(《:>^)八4規格(210/297公釐) (請先閱讀背面之注意事項ί寫本頁) .裝. 訂 A7 B7 410451 五、發明説明(5 ) 如第3(a)與3(b)圖所示,該被封裝的LSI包含一具有多 層佈線結構結構的晶片1與連接至該晶片1的封裝體4。該 晶片1具有位於中心的内部邏輯電路2,該内部邏輯電路係 由多個元件所形成。多個I/O墊3在該晶片1的外部周邊之 四周被形成,並且被用來饋送電力至該内部邏輯電路2, 並且用來將訊號輸入至該内部邏輯電路及從該内部邏輯電 路輸出。引線電極5在該封裝體4上被形成,並且被暴露在 外部。該墊3藉由黏合線6而被連接至在該封裝鱧4上的該 引線電極5上》 如第4(a)與4(b)圖所示,該墊3大致為正方形。一最好 包含一氧化物薄膜的内層薄膜7被設置在該墊3之下。一饰 線結構8位於該内層薄膜7下。多個在該内層薄膜7中的接 點9在該塾3與該佈線結構8之間提供一互連。欲註明的是, 該墊3可以是矩形或是呈任何期望的組構。該墊3在其上表 面為於對應該等接點9處被形成有一非常淺的凹陷1〇。該 黏合線6被接合至該墊3之中心區域,如第4(幻與4(b)圖所 示。 如將會被註明者,該等接點9被以偏移的方式設置,以 便在該墊3之中心區域中並亦沿該墊3之外緣被局部地集 中。特別地,有複數個接點9&與該墊3的各邊對齊,並且 有一給定數目的接點4b(在第4(b)圖中有四個),該等接點 係被局部地設置在該墊3之中心區域中。最好地,該等接 點9a至少在該墊3的四個角落附近被設置,並且該等接點外 被設置在一被指定用來與該線6接合用的區域中。 (請先聞讀背面之注意事項Η 裝-- 寶本!; 經濟部中央標率局員工消費合作社印製 8 410451 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明(6 ) 該等接觸9b的數目在一範圍中被選擇,該範園係確保 該墊與該佈線結構8之間期望的連結強度(或墊—佈線結構 的連接強度)並且維持在該墊3與該線6之間一期望的接合 強度(墊-線的接合強度)》將被領略的是,該墊-佈線結構 的連接強度與該墊-線的接合強度兩者皆視被提供的接點 9b之數目而定。特別地,該等接點孙的數目越少,該墊-佈線結構的連接強度越低’且該塾-線接合強度越大。相 反地,接點9b的數目越多,該墊-佈線結構的連接強度越 大,且該墊-佈線結構的接合強度越低。因此,接點9b的 數目被選擇在一範圍中,該範園係相當於即使在焊接操作 期間,亦能夠维持在該墊3與該線6間連接的完整之範圍。 接點9b的數目可以在此範圍内如所期望般地改變。接點9b 之數目可以根據欲在該墊3與詖線6間用以接合的面積來被 設定》此外,該等接點9b之配置可以如期望般地被改變。 欲註明的是,在第4(a)圖中被舉例說明之該墊3係為代 表性者,並該等接點9a與9b之實際的數目可與第4(a)圖之 例示不同。實際上會有較第4圓所示之接點9a、扑多》該 墊3與該等接點9a與9b實際的大小最好被選擇,使得當一 墊在一邊上有80# m時,各該等接點9a與9b在一邊上約有 0.6 μ m ’並且在相鄰的接點9a或9b間之間隔約為1 ·2仁m。 如此,借助該等接點9a與9b,該墊3被牢固地固定至該 佈線結構8或該内層薄膜7上。該墊-佈線結構的連接強度 被改進而優於在第1圖中所舉例之習知技藝的墊-佈線結構 的連接強度,並且即使一向上的力被施加至該墊3上,該V. Description of the invention (This' The wire 15 is easily separated from the pad 11a, which leads to a decrease in the reliability of the integrated circuit. It is an object of the present invention to provide a semiconductor device having an increased pad connection strength. Economy Summary of the Consumer Co-operation of the Ministry of Standards and Technology of the United States Du Printed Invention In order to achieve the above-mentioned object, the present invention provides a semiconductor device including: a semiconductor wafer; a wiring structure formed on the semiconductor wafer; an inner layer A film is provided on the top of the wiring structure; a frame is provided on the top of the inner layer film and includes an outer edge and a center region; and a plurality of contacts are formed on the inner layer film In order to interconnect the pad with the wiring structure, the plurality of contacts include a first contact and a first contact that are arranged along the pad and partially concentrated in a central area of the pad in an offset manner. The second contact group. The present invention further provides a semiconductor device including: a semiconductor wafer; a wiring structure formed on the semiconductor wafer; an inner layer film, Is provided on the top of the wiring structure; a pad is provided on the top of the inner layer film and includes an outer edge and a center region; and first and second contacts are formed on the Inside the inner film for interconnecting the wiring structure with the pad, the first contact is set along the outer edge of the pad, and the second contact is set in the center area of the pad Other aspects and advantages of the invention will become apparent from the following description and the accompanying drawings, which illustrate the principle of the present invention by way of example. (谙 Read the notes on the back 3ϋϋ 本-··))-Order_ The size of this paper is applicable to China National Standards (CNS) A4 specification (210 × 297 mm) 6 Printed by Shellfish Consumer Cooperative of Central Standards Bureau of the Ministry of Economic Affairs 410451 at B7 V. Description of the invention (4) Brief description of the invention together with its purpose Advantages and advantages will be best understood by referring to the following description of the presently preferred embodiment and accompanying drawings, in the following drawings: The first is a top view of the first example of a traditional pad; the first is along the Line segment lb-l in Figure 1 (a) Figure 2 (a) is a top view of the second example of a traditional pad; Figure 2 (b) is a section taken along line 2b-2b of Figure 2 (a) FIG. 3 (a) is a top view of a part of an LSI according to a first embodiment of the present invention; FIG. 3 (b) is a part of FIG. 3 (a) Figure 4 (a) is a top view showing one of the pads of the LSI in Figure 3 (a); Figure 4 (b) is shown along line 4b-4b of Figure 4 (a) A cross-sectional view of a section; < Figures 5 (a) to 5 (d) are top views of other pads according to the present invention; Figure 6 (a) is a top view of another pad according to the present invention ; And FIG. 6 (b) is a cross-sectional view taken along line 6b-6b shown in FIG. 6 (a). DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIGS. 3 and 4, a packaged LSI according to one of the embodiments of the present invention will be described. This paper size applies to the national standard (": > ^) 8 4 specifications (210/297 mm) (Please read the precautions on the back first to write this page). Packing. Order A7 B7 410451 V. Description of the invention ( 5) As shown in FIGS. 3 (a) and 3 (b), the packaged LSI includes a wafer 1 having a multilayer wiring structure and a package 4 connected to the wafer 1. The wafer 1 has an internal logic circuit 2 located at the center, and the internal logic circuit is formed of a plurality of elements. A plurality of I / O pads 3 are formed around the outer periphery of the chip 1 and are used to feed power to the internal logic circuit 2 and are used to input signals to and output from the internal logic circuit. . A lead electrode 5 is formed on the package body 4 and is exposed to the outside. The pad 3 is connected to the lead electrode 5 on the package 鳢 4 by an adhesive wire 6. As shown in FIGS. 4 (a) and 4 (b), the pad 3 is substantially square. An inner layer film 7 preferably containing an oxide film is disposed under the pad 3. A trim structure 8 is located under the inner film 7. A plurality of contacts 9 in the inner layer film 7 provide an interconnection between the coil 3 and the wiring structure 8. It should be noted that the pad 3 may be rectangular or in any desired configuration. The pad 3 has a very shallow depression 10 formed on the upper surface corresponding to the contacts 9. The bonding line 6 is bonded to the central area of the pad 3, as shown in Figure 4 (magic and 4 (b). As will be noted, these contacts 9 are set in an offset manner so that The central area of the pad 3 is also partially concentrated along the outer edge of the pad 3. In particular, there are a plurality of contacts 9 & aligned with each side of the pad 3, and there is a given number of contacts 4b ( There are four in Figure 4 (b)), the contacts are partially arranged in the central area of the pad 3. Preferably, the contacts 9a are at least near the four corners of the pad 3. Is set, and these contacts are set outside an area designated for joining with the line 6. (Please read the precautions on the back first. Installation-Treasures !; Central Standards Bureau, Ministry of Economic Affairs Printed by Employee Consumer Cooperatives 8 410451 A7 B7 Printed by Employee Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of Inventions (6) The number of these contacts 9b is selected within a range, and this model ensures that the pad and the wiring structure The desired connection strength (or the connection strength between the pad and the wiring structure) between 8 is maintained at a desired level between the pad 3 and the wire 6 Bonding strength (pad-wire bonding strength) "It will be appreciated that both the bonding strength of the pad-wiring structure and the bonding strength of the pad-wire depend on the number of contacts 9b provided. In particular The smaller the number of such contact grandchildren, the lower the connection strength of the pad-wiring structure 'and the greater the 塾 -wire bonding strength. Conversely, the greater the number of contacts 9b, the pad-wiring structure connection The greater the strength, and the lower the bonding strength of the pad-wiring structure. Therefore, the number of contacts 9b is selected in a range, which is equivalent to being able to maintain the pad 3 and the pad 3 even during the welding operation. The complete range of connections between the lines 6. The number of contacts 9b can be changed as desired within this range. The number of contacts 9b can be based on the area to be joined between the pad 3 and the cymbal 6 In addition, the configuration of these contacts 9b can be changed as desired. It should be noted that the pad 3 illustrated in Figure 4 (a) is representative, and the connection The actual number of points 9a and 9b may differ from the illustration in Figure 4 (a). Actually there will be The contact 9a and flutter shown in the fourth circle "The actual size of the pad 3 and the contacts 9a and 9b is best selected so that when a pad has 80 # m on one side, each of these contacts 9a and 9b are approximately 0.6 μm 'on one side and the distance between adjacent contacts 9a or 9b is approximately 1.2 m. Thus, with these contacts 9a and 9b, the pad 3 is firmly secured. It is fixed to the wiring structure 8 or the inner layer film 7. The connection strength of the pad-wiring structure is improved to be better than that of the pad-wiring structure of the conventional technique exemplified in FIG. The force is applied to the pad 3, which
(諸先閲讀背面之注意事項V 裝-- 、寫本頁)(Please read the precautions on the back of the first V equipment-, write this page)
'IT Μ. 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ297公釐) 9 410451 A7 B7 五、發明説明(7 ) 經濟部中央標準局負工消費合作社印製 佈線結構的連接強度維持被連接至該佈線結構8之該墊 在該墊3與該線3間之可靠的接合被維持成如被設置在 該中心區域的接點9b的數目—樣多,與例示於第2圖中的 習知技藝比較該等接點9b的數目被減少,以准許該墊3保 持间度平坦,使得有較寬的面積供在該整3與該線6之間焊 接用’因而避免該線6不良的接合。 對熟於此技者應為顯而易見的是’本發明在不背離本 發明之精神與範圍的情況下,可以許多其他特定的形式來 具體實施<尤其,應被了解的是,本發明可以具體實施成 下列形式: 八要該等接點9a與9b以一偏移的方式被設置成沿該墊3 之該外緣與在該墊3之中心區域中局部地集中,該等接點9a 與9b的數目與置放可如期.望般地修正。特別較好的是’當 該等接點9b被局部地設置在該墊3的中心區域時,該等接 點9a在該墊3之至少四個角落處被設置。 作為一例子,該等接點9 a可以作為一外部陣列沿一塾3 a 之各邊被設置,並且附加的複數個接點9c可以被設置在外 部陣列内該墊3的四個角落處,如第5(a)圖所示。複數個 接點9b被局部地設置在該塾3a的中心區域,並且可以包括 連同接點9b之接點9a的一中心羣’該等接點被與該中 羣隔離’並且從該墊3a的中心放射地延伸。另一方面, 等接點9a與9b可以沿該墊3a的對角線在相鄰的接觸間以 相等的間隔被設置。 墊- 3 心 該 諳 先. 閱 讀. 背 之 注 意 事 項 本 頁 裝 訂 )線 本紙張尺度適用中國國家標準(CNS ) A4規格(2Π)Χ297公釐) 10 410451 A7 B7 五、發明説明(8 ) 此外,該等接點9b可以被設置在用以與該線6接合用的 區域内,但是此係以一種方式來避免其置放位於一墊扑之 中心處,如第5b圖所示。在第5(c)圖中,一羣接點如在― 墊3c的各角落處被設置,並且接點处沿從該墊爻延伸至該 等角落的對角線被設置。如另一替換的形式,當—羣接點 9b只在該墊3d的中心被設置時,一羣接點%只在一墊“的 每個角落處被設置,如第5(d)圖所示。 如第ό圖所示’可使用連續接點i 1&與i lb。該接點i j a 係呈大小較一墊3e的外部輪廓小的矩形。該墊llb亦是呈 被設置在一用於與該線6接合用之區域中的矩形,並且與 該接點1 la成同心關係。在此示例中,該墊3e被形成有複 數個凹槽12於其中,該等凹槽係與該等接點lla與Ub相對 .應。 本例子與實施例係以例示而被考慮,但不是作為限制, 並且本發明不被限制於本文所述之細節中,而是可以在後 附的申請專利範圍之範園與相同者中作修正。 面 之 項'IT Μ. This paper size applies Chinese National Standard (CNS) A4 specification (210 × 297 mm) 9 410451 A7 B7 V. Description of invention (7) The connection strength of the printed wiring structure printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives is maintained by The reliable bonding of the pad connected to the wiring structure 8 between the pad 3 and the wire 3 is maintained as the number of contacts 9b provided in the center area-as many as the example illustrated in FIG. 2 The number of contacts 9b is reduced in comparison with conventional techniques to allow the pad 3 to be kept flat, so that there is a wider area for welding between the whole 3 and the line 6, thus avoiding the failure of the line 6. Of the joint. It should be apparent to those skilled in the art that the present invention can be embodied in many other specific forms without departing from the spirit and scope of the invention < in particular, it should be understood that the invention may be embodied It is implemented in the following form: The contacts 9a and 9b are required to be arranged in an offset manner to be partially concentrated along the outer edge of the pad 3 and in the central area of the pad 3. The contacts 9a and 9b The number and placement of 9b can be revised as expected. It is particularly preferable that when the contacts 9b are locally provided in the center region of the pad 3, the contacts 9a are provided at at least four corners of the pad 3. As an example, the contacts 9 a may be provided as an external array along each side of a 塾 3 a, and additional plurality of contacts 9 c may be provided at four corners of the pad 3 in the external array. This is shown in Figure 5 (a). The plurality of contacts 9b are locally provided in the center area of the 塾 3a, and may include a central group together with the contacts 9a of the contacts 9b 'the contacts are isolated from the middle group' and from the pad 3a The center extends radially. On the other hand, the equal contacts 9a and 9b may be arranged at equal intervals between adjacent contacts along the diagonal of the pad 3a. Pad-3 Be the first to read. Read. Notes on the back of this page) Thread paper size applies Chinese National Standard (CNS) A4 (2Π) x 297 mm 10 410451 A7 B7 V. Description of the invention (8) In addition The contacts 9b can be arranged in the area for joining with the line 6, but this is to prevent its placement in the center of a pad, as shown in Figure 5b. In Fig. 5 (c), a group of contacts is provided at each corner of the pad 3c, and the contacts are provided along a diagonal line extending from the pad to the corners. As another alternative form, when the group contact 9b is set only at the center of the pad 3d, the group contact% is set only at each corner of the pad, as shown in Figure 5 (d). As shown in the figure, 'continuous contacts i 1 & and i lb can be used. The contact ija is a rectangle smaller than the outer contour of a pad 3e. The pad 11b is also used for one purpose. The rectangle in the area to be joined with the line 6 is in a concentric relationship with the contact 11a. In this example, the pad 3e is formed with a plurality of grooves 12 therein, which grooves are connected to the The equivalent contact 11a corresponds to Ub. This example and embodiment are considered by way of illustration, but not as a limitation, and the invention is not limited to the details described herein, but can be applied for in the attached patent The scope of the Fan Garden is the same as that of the same.
妾 裝 訂 Λ線 經濟部中央標準局員工消費合作社印製 本紙張尺度適财關家楼準(CNS} (21QX297公袭丨 11 410451 A7 B7 經濟部中央標準局貞工消費合作社印製 五、發明説明(9 ) 元件標號對照表 1 晶片 2 内部邏輯電路 3 I/O墊 3a 墊 3b 墊 3c 塾 3d 墊 3e 墊 4 封裝體 • 5 引線電極 6 黏合線 7 内層薄膜 8 佈線結構 9 接點 9a 接點 9b 接點 9c 接點 10 凹陷 11 塾 11a 連續接點 lib 連續接點 12 内層薄膜 13 佈線結構 14 接點 15 焊線 16 凹陷 (讀先閱讀背面之注意事項再1^本頁) -裝· 訂 本紙張尺度適用中國國家標準(CNS ) A4現格(2丨0X297公釐) 12 1妾 Binding Printed by Λ Line Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (CNS) (21QX297 public attack 丨 11 410451 A7 B7 Printed by the Zhengong Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economy (9) Table of component numbers 1 Chip 2 Internal logic circuit 3 I / O pad 3a Pad 3b Pad 3c 塾 3d Pad 3e Pad 4 Package • 5 Lead electrode 6 Bonding wire 7 Inner film 8 Wiring structure 9 Contact point 9a Contact point 9b contact 9c contact 10 depression 11 塾 11a continuous contact lib continuous contact 12 inner film 13 wiring structure 14 contact 15 solder wire 16 depression (read the precautions on the back and read 1 ^ this page) This paper size applies Chinese National Standard (CNS) A4 (2 丨 0X297mm) 12 1
Claims (1)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP22334298A JP3898350B2 (en) | 1998-08-06 | 1998-08-06 | Semiconductor device |
Publications (1)
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TW410451B true TW410451B (en) | 2000-11-01 |
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TW088103984A TW410451B (en) | 1998-08-06 | 1999-03-15 | Semiconductor device with improved pad connection |
Country Status (4)
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US (1) | US5986346A (en) |
JP (1) | JP3898350B2 (en) |
KR (1) | KR100321594B1 (en) |
TW (1) | TW410451B (en) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
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US6140710A (en) * | 1999-05-05 | 2000-10-31 | Lucent Technologies Inc. | Power and ground and signal layout for higher density integrated circuit connections with flip-chip bonding |
KR100608608B1 (en) * | 2000-06-23 | 2006-08-09 | 삼성전자주식회사 | Semiconductor chip package having bonding pad structure of mixing type and manufacturing method thereof |
US6465895B1 (en) * | 2001-04-05 | 2002-10-15 | Samsung Electronics Co., Ltd. | Bonding pad structures for semiconductor devices and fabrication methods thereof |
JP4801296B2 (en) * | 2001-09-07 | 2011-10-26 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
US6740956B1 (en) | 2002-08-15 | 2004-05-25 | National Semiconductor Corporation | Metal trace with reduced RF impedance resulting from the skin effect |
US6864581B1 (en) | 2002-08-15 | 2005-03-08 | National Semiconductor Corporation | Etched metal trace with reduced RF impendance resulting from the skin effect |
US6703710B1 (en) * | 2002-08-15 | 2004-03-09 | National Semiconductor Corporation | Dual damascene metal trace with reduced RF impedance resulting from the skin effect |
US6853079B1 (en) | 2002-08-15 | 2005-02-08 | National Semiconductor Corporation | Conductive trace with reduced RF impedance resulting from the skin effect |
JP4627621B2 (en) * | 2002-10-18 | 2011-02-09 | パナソニック株式会社 | Semiconductor integrated circuit |
JP4517843B2 (en) | 2004-12-10 | 2010-08-04 | エルピーダメモリ株式会社 | Semiconductor device |
JP4646789B2 (en) * | 2005-12-02 | 2011-03-09 | パナソニック株式会社 | Semiconductor device |
US8579494B2 (en) * | 2008-08-22 | 2013-11-12 | Sara Lee Tm Holdings, Llc | System and method for dough extrusion |
KR101003118B1 (en) | 2008-10-10 | 2010-12-21 | 주식회사 하이닉스반도체 | Pad Structure of Semiconductor integrated circuit apparatus |
JP5041088B2 (en) * | 2011-04-15 | 2012-10-03 | 富士通セミコンダクター株式会社 | Semiconductor device |
JP2016129161A (en) * | 2013-04-24 | 2016-07-14 | パナソニック株式会社 | Semiconductor device |
US9984987B2 (en) | 2016-08-05 | 2018-05-29 | Nanya Technology Corporation | Semiconductor structure and manufacturing method thereof |
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US5175609A (en) * | 1991-04-10 | 1992-12-29 | International Business Machines Corporation | Structure and method for corrosion and stress-resistant interconnecting metallurgy |
US5248903A (en) * | 1992-09-18 | 1993-09-28 | Lsi Logic Corporation | Composite bond pads for semiconductor devices |
US5367195A (en) * | 1993-01-08 | 1994-11-22 | International Business Machines Corporation | Structure and method for a superbarrier to prevent diffusion between a noble and a non-noble metal |
JP3432284B2 (en) * | 1994-07-04 | 2003-08-04 | 三菱電機株式会社 | Semiconductor device |
JPH08213422A (en) * | 1995-02-07 | 1996-08-20 | Mitsubishi Electric Corp | Semiconductor device and bonding pad structure thereof |
-
1998
- 1998-08-06 JP JP22334298A patent/JP3898350B2/en not_active Expired - Lifetime
-
1999
- 1999-03-15 TW TW088103984A patent/TW410451B/en not_active IP Right Cessation
- 1999-03-22 US US09/273,472 patent/US5986346A/en not_active Expired - Lifetime
- 1999-04-07 KR KR1019990012041A patent/KR100321594B1/en not_active IP Right Cessation
Also Published As
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JP2000058583A (en) | 2000-02-25 |
KR20000016849A (en) | 2000-03-25 |
KR100321594B1 (en) | 2002-03-18 |
JP3898350B2 (en) | 2007-03-28 |
US5986346A (en) | 1999-11-16 |
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