JP2002217356A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same

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Publication number
JP2002217356A
JP2002217356A JP2001010893A JP2001010893A JP2002217356A JP 2002217356 A JP2002217356 A JP 2002217356A JP 2001010893 A JP2001010893 A JP 2001010893A JP 2001010893 A JP2001010893 A JP 2001010893A JP 2002217356 A JP2002217356 A JP 2002217356A
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Japan
Prior art keywords
semiconductor chip
layer
bonding pads
lower layer
semiconductor
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Pending
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JP2001010893A
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Japanese (ja)
Inventor
Koji Furusawa
宏治 古澤
Original Assignee
Nec Corp
日本電気株式会社
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Application filed by Nec Corp, 日本電気株式会社 filed Critical Nec Corp
Priority to JP2001010893A priority Critical patent/JP2002217356A/en
Publication of JP2002217356A publication Critical patent/JP2002217356A/en
Application status is Pending legal-status Critical

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Abstract

PROBLEM TO BE SOLVED: To prevent breaking of a semiconductor-chip in thermocompression- bonding a lower-layer semiconductor chip onto a wiring substrate and to enable visual confirmation on connection sites, in stacking semiconductor chips of equal size. SOLUTION: In this semiconductor device in which semiconductor chips of equal size are stacked on a printed wiring substrate 1, a lower-layer semiconductor chip 2 and an upper-layer semiconductor chip 4 are shifted in their mutual position in stacking the chips. Wiring layers 3, 5 for arranging the bonding pads of the lower-layer semiconductor chip and of the upper-later semiconductor chip are provided on respective peripheral end regions 30, 50 of the chips where the stacking is not taken place because of the position shifting.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は基板上に複数の半導体チップを積層して実装する半導体装置に関する。 The present invention relates to a semiconductor device that implements by stacking a plurality of semiconductor chips on a substrate. 特に、本発明は、サイズが等しい半導体チップを積層する時に下層の半導体チップのワイヤボンディングを可能にする半導体装置及びその製造方法に関する。 In particular, the present invention relates to a semiconductor device and a manufacturing method thereof enabling wire bonding of the underlying semiconductor chip when stacking the size equal semiconductor chip.

【0002】 [0002]

【従来の技術】従来の高密度実装技術の1つとして、プリント配線基板上に複数の半導体チップを積層実装するスタック実装という技術がある。 BACKGROUND ART As one of conventional high-density packaging techniques, there is a technique called stack implementation of laminating mounting a plurality of semiconductor chips on a printed wiring board. スタック実装では、通常、プリント配線基板と積層される半導体チップとの接続が、ワイヤボンディングにより行われる。 The stack implementation, typically, the connection between the semiconductor chip to be stacked with the printed wiring board is performed by wire bonding.

【0003】このため、ボンディングパッドを上向きにしたフェースアップ(Face Up)の状態で、チップサイズの大きな順に半導体チップが積層される。 [0003] Therefore, in a face-up in which the bonding pad in an upward (Face Up) state, the semiconductor chip are stacked to a large order of chip size. すなわち、積層される半導体チップでは、大きいサイズの下層の半導体チップの面のうち、小さいサイズの上層の半導体チップと接触しない面に、ボンディングパッドが設けられる。 That is, in the semiconductor chips to be stacked, of the surface of the underlying semiconductor chip larger size, do not contact the upper layer of the semiconductor chip of small size surface, the bonding pads are provided.

【0004】ところで、サイズが等しい半導体チップを積層する場合には、下層の半導体チップの全面が上層の半導体チップにより覆われるので、下層の半導体チップにはボンディングパッドを設ける場所が無くなる。 Meanwhile, in the case of lamination to equal the semiconductor chip size, since the entire surface of the lower semiconductor chip is covered with an upper layer of the semiconductor chip, there is no place to provide the bonding pads on the lower semiconductor chip. 従来技術として、サイズが等しい半導体チップの積層実装について以下に説明する。 As a conventional art will be described below stacked mounting of equal size semiconductor chip. 図16は本発明の前提となる半導体装置の概略を示す断面図である。 Figure 16 is a cross-sectional view schematically showing a semiconductor device which is a premise of the present invention. 本図に示すように、半導体装置は、プリント配線基板1に半導体チップ200、210が積層実装されることにより製造される。 As shown in the figure, a semiconductor device, a semiconductor chip 200, 210 is manufactured by being stacked and mounted on the printed circuit board 1.

【0005】プリント配線基板1にはボンディングパッド211a、211b、ボンディングパッド231a、 [0005] printed circuit on the board first bonding pads 211a, 211b, bonding pads 231a,
231bが設けられる。 231b is provided. 半導体チップ200、210のサイズは等しく、半導体チップ201が上層に位置し、 The size of the semiconductor chip 200 and 210 are equal, the semiconductor chip 201 is positioned on the upper layer,
半導体200が下層に位置する。 Semiconductor 200 is positioned in the lower layer. 上層の半導体チップ2 The upper layer of the semiconductor chip 2
10の両サイドには、通常とおりフェースアップの状態で、ボンディングパッド241a、241bが設けられる。 On both sides of the 10, in the state of normal as face-up bonding pads 241a, 241b are provided.

【0006】下層の半導体チップ200の両サイドには、フェースダウン(Face Down)の状態で、 [0006] On both sides of the lower layer of the semiconductor chip 200, in the state of face-down (Face Down),
ボンディングパッド221a、221bが設けられる。 Bonding pads 221a, 221b are provided.
通常とおり、上層の半導体チップ210のボンディングパッド241a、241bとプリント配線基板1のボンディングパッド211a、211bとがワイヤ201 As usual, the bonding pads 241a, 241b and the printed wiring board 1 of the bonding pad 211a of the upper semiconductor chip 210, 211b and the wire 201
a、201bを用いてワイヤボンディングにより電気的に接続される。 a, it is electrically connected by wire bonding using 201b. 下層の半導体チップ200のボンディングパッド221a、221bとプリント配線基板1のボンディングパッド231a、231bとが金バンプ22 Bonding pad 221a of the lower semiconductor chip 200, 221b and the printed wiring board 1 of the bonding pads 231a, 231b Togakin bumps 22
0a、220bを用いて熱圧着により電気的に接続される。 0a, it is electrically connected by thermocompression bonding using 220b.

【0007】このように、金バンプ220a、220b [0007] In this way, gold bump 220a, 220b
の熱圧着を用いて、下層の半導体チップ200とプリント配線基板1とのボンディングパッド220a、220 Using thermocompression bonding, underlying semiconductor chip 200 and the printed circuit bonding pad 220a of the substrate 1, 220
b、ボンディングパッド231a、231bを電気的に接続することは、特開平7−326710号公報に開示されている。 b, the bonding pad 231a, to electrically connect the 231b, are disclosed in JP-A-7-326710. 上層の半導体チップ210の面と下層の半導体チップ200の面は接着剤206bにより相互に接着固定される。 Surface and lower surface of the semiconductor chip 200 of the upper semiconductor chip 210 is bonded and fixed to each other by the adhesive 206 b. さらに、下層の半導体200の面とプリント配線基板1の面は接着剤206aにより相互に接着固定される。 Further, the surface and the surface of the printed wiring board 1 of the underlying semiconductor 200 is bonded and fixed to each other by an adhesive 206a.

【0008】 [0008]

【発明が解決しょうとする課題】しかしながら、上記半導体装置の製造では、下層の半導体チップ200がフェースダウンでプリント配線基板1に電気的に接続されるため、下層の半導体チップ200を熱圧着する際に、下層の半導体チップ200が破損したり、フェースダウンに起因して接続部位の目視確認ができず、歩留りが低下するという問題がある。 OBJECTS OF THE INVENTION It'll solve] However, in the production of the semiconductor device, since the lower layer of the semiconductor chip 200 is electrically connected to the printed wiring board 1 in a face-down, when the thermocompression bonding of the underlying semiconductor chip 200 the lower layer or the semiconductor chip 200 is corrupted, can not visually check the connecting portion due to face-down, the yield is lowered.

【0009】このため、後工程に対する負荷が増大するという問題が発生する。 [0009] Therefore, a problem that the load on the rear step is increased occurs. したがって、本発明は上記問題点に鑑みて、サイズが等しい半導体チップを積層する際に、下層の半導体チップとプリント配線基板との熱圧着による破損防止を可能にし、接続部位の目視確認を可能にする半導体装置及びその製造方法を提供することを目的とする。 Accordingly, the present invention is in view of the above problems, when stacking a size equal semiconductor chip, enabling preventing damage due to thermocompression bonding with the underlying semiconductor chip and the printed wiring board, to allow visual confirmation of the connection sites and to provide a semiconductor device and a manufacturing method thereof.

【0010】 [0010]

【課題を解決するための手段】本発明は前記問題点を解決するために、サイズの等しい半導体チップがプリント配線基板に積層される半導体装置において、下層の前記半導体チップと上層の前記半導体チップをずらして積層することにより積層されない周辺端部にボンディングパッドを形成するためのボンディングパッド用周辺端部と、下層の前記半導体チップの前記ボンディングパッド用周辺部に下層の前記半導体チップのボンディングパッドを配置する配線層とを備えることを特徴とする半導体装置を提供する。 Means for Solving the Problems The present invention to solve the above problems, a semiconductor device size equal the semiconductor chip is stacked on the printed circuit board, the lower layer of the semiconductor chip and the layer of the semiconductor chip shifting the peripheral edge bonding pads for forming a bonding pad on the peripheral edge portion which is not laminated by laminating a lower layer of the semiconductor chip bonding pad to the peripheral portion bonding pads of the lower layer of the semiconductor chip arranged further comprising a wiring layer to provide a semiconductor device according to claim.

【0011】この手段により、サイズが等しい半導体チップを積層する際に、下層の半導体チップとプリント配線基板とを熱圧着する必要がなくなり、熱圧着による下層の半導体チップの破損防止が可能になり、さらに接続部位の目視確認を可能にでき、歩留まりを向上させることが可能になる。 [0011] By this means, when stacking a size equal semiconductor chip, and a lower layer of the semiconductor chip and the printed wiring board do not have to thermocompression bonding enables prevention of damage underlying semiconductor chip by thermocompression bonding, further can enable visual confirmation of the connection site, it is possible to improve the yield. さらに、本発明は、サイズの等しい半導体チップがプリント配線基板に積層される半導体装置において、下層の前記半導体チップと上層の前記半導体チップをずらして積層することにより積層されない周辺端部にボンディングパッドを形成するためのボンディングパッド用周辺端部と、下層の前記半導体チップの前記ボンディングパッド用周辺部にボンディングパッドを配置する配線層とを備えることを特徴とする半導体装置を提供する。 Furthermore, the present invention provides a semiconductor device size equal the semiconductor chip is stacked on a printed wiring board, a bonding pad to the peripheral edge portion which is not laminated by laminating shifted lower layer of the semiconductor chip and the layer of the semiconductor chip a peripheral edge bonding pads for forming, to provide a semiconductor device characterized by comprising a wiring layer to place a bonding pad in the peripheral portion for bonding pads of the lower layer of the semiconductor chip. この手段により、通常、上層の半導体チップのボンディングパッドはワイヤボンディングが可能であるので、配置の必要が無い場合には、下層の半導体チップだけ配置を行うようにできる。 By this means, usually a bonding pad of the upper semiconductor chip so it is possible to wire bonding, if necessary placement is not be to make the arrangement only the lower layer of the semiconductor chip. 好ましくは、前記周辺部は、それぞれが矩形である下層の前記半導体チップと上層の前記半導体チップとが積層された状態から上層の前記半導体チップを1つの辺方向にずらすることにより、下層の前記半導体チップに形成される。 Preferably, the peripheral portion, by each of which Shifts from a state where the lower layer of the semiconductor chip and an upper layer of the semiconductor chip is rectangular laminated an upper layer of the semiconductor chip to one side direction, the lower layer of the It is formed on the semiconductor chip.

【0012】この手段により、下層の半導体チップの1 [0012] By this means, the lower semiconductor chip 1
つの辺にボンディングパッドを形成するための周辺端部が形成可能になる。 One of the peripheral edge for forming a bonding pad on the sides allowing formation. 好ましくは、前記周辺部は、それぞれが矩形である下層の前記半導体チップと上層の前記半導体チップとが積層された状態から上層の前記半導体チップを、例えば、45度回転してずらすことにより、下層の前記半導体チップに形成される。 Preferably, the peripheral portion, the upper layer of the semiconductor chip from the state where each and a lower layer of the semiconductor chip and an upper layer of the semiconductor chip is rectangular stacked, for example, by shifting and rotating 45 degrees, the lower layer It is the formed on the semiconductor chip.

【0013】この手段により、下層の半導体チップの4 [0013] By this means, the lower semiconductor chip 4
つの隅にボンディングパッドを形成するための周辺端部が形成可能になる。 One of the peripheral edge for forming a bonding pad on the corner becomes possible formation. また下層の半導体チップ2上層の半導体チップの中心が同軸上に積層できるため、半導体チップを積層する際の安定性が増し、各ワイヤが半導体チップの方向に引き出せるので、ワイヤ配線の自由度が増すという効果が発生する。 Further, since the center of the lower semiconductor chip 2 an upper layer of the semiconductor chip can be stacked coaxially, increased stability when stacking the semiconductor chips, each wire so pulled out in the direction of the semiconductor chip, the degree of freedom of the wire wiring is increased effect occurs that. 好ましくは、前記周辺部は、 Preferably, the peripheral portion,
それぞれが矩形である下層の前記半導体チップと上層の前記半導体チップとが積層された状態から上層の前記半導体チップを2つの辺方向にずらすことにより、下層の前記半導体チップに形成される。 By the shift from a state where the lower layer of the semiconductor chip and an upper layer of the semiconductor chip is rectangular laminated an upper layer of the semiconductor chip to the two side direction, respectively, are formed in the lower layer of the semiconductor chip.

【0014】この手段により、下層の半導体チップの2 [0014] 2 of this means, the lower layer of the semiconductor chip
つの辺にボンディングパッドを形成するための周辺端部が形成可能になる。 One of the peripheral edge for forming a bonding pad on the sides allowing formation. 好ましくは、前記配線層はポリイミド、アルミニウムにより構成される。 Preferably, the wiring layer is composed of polyimide, of aluminum. この手段により、 By this means,
配線層の内部に接続線の形成が可能になり、半導体チップのボンディングパッドの位置を、半導体チップ上の任意の位置に配置しなおすことが可能になる。 Formation of a connection line inside the wiring layers becomes possible, the position of the bonding pads of the semiconductor chip, it is possible to re-positioned anywhere on the semiconductor chip.

【0015】好ましくは、下層の前記半導体チップと上層の前記半導体チップをずらして半導体チップを2層又は3層に積層する。 Preferably, laminated to two or three layers of semiconductor chip by shifting the lower layer of the semiconductor chip and the upper layer of the semiconductor chip. この手段により、積層されるサイズが等しい半導体チップのワイヤボンディングが可能になり、歩留まりを向上しつつ高密度実装が可能になる。 By this means, the wire bonding of the semiconductor chip of equal size to be stacked becomes possible, allowing high-density mounting while improving the yield. 好ましくは、ずらして積層された下層の前記半導体チップと上層の前記半導体チップとについて配置されたボンディングパッドに対応して、プリント配線基板のボンディングパッドを配置する。 Preferably, shifting in response to stacked lower layer of the semiconductor chip and an upper layer of the semiconductor chip and the bonding pads arranged on it, placing the bonding pads of the printed wiring board.

【0016】この手段により、積層される半導体チップの全てとプリント配線基板とのワイヤボンディングが可能になる。 [0016] By this means, it is possible wire bonding between all the printed circuit board of the semiconductor chips to be stacked. さらに、本発明は、サイズの等しい半導体チップがプリント配線基板に積層される半導体装置の製造方法において、下層の前記半導体チップ、上層の前記半導体チップの周辺部にボンディングパッドを配線層により配置する工程と、下層の前記半導体チップ、上層の半導体チップの周辺部に配置される前記ボンディングパッドと重ならないように下層の半導体チップと上層の半導体チップをずらして積層する工程と、下層の前記半導体チップと上層の前記半導体チップのボンディングパッドと前記プリント配線基板のボンディングパッドをワイヤボンディングにより電気的に接続することを特徴とする半導体装置の製造方法を提供する。 Furthermore, the present invention comprises the steps of placing the semiconductor device manufacturing method size equal the semiconductor chip is stacked on a printed wiring board, a lower layer of the semiconductor chip, the bonding pads by the wiring layer in the peripheral portion of the upper layer of the semiconductor chip If, laminating by shifting the lower layer of the semiconductor chip, the lower semiconductor chip so as not to overlap with the bonding pads arranged on the periphery of the upper semiconductor chip and the upper semiconductor chip, and the lower layer of the semiconductor chip to provide a method of manufacturing a semiconductor device, wherein a top layer of said semiconductor chip bonding pad and the bonding pads of the printed wiring board are electrically connected by wire bonding.

【0017】この手段により、上記発明と同様に、サイズが等しい半導体チップを積層する際に、下層の半導体チップとプリント配線基板とを熱圧着する必要がなくなり、熱圧着による破損防止が可能になり、接続部位の目視確認を可能にでき、歩留まりを向上することが可能になる。 [0017] By this means, similarly to the above invention, when stacking a size equal semiconductor chip, there is no a lower layer of the semiconductor chip and the printed wiring board needs to thermocompression bonding enables damage prevention by thermocompression , can enable the visual confirmation of the connection site, it is possible to improve the yield.

【0018】 [0018]

【発明の実施の形態】以下、本発明の実施の形態について図面を参照して説明する。 BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, will be explained with reference to the drawings, embodiments of the present invention. 図1は、本発明に係る半導体装置の概略を示す斜視図である。 Figure 1 is a perspective view schematically showing a semiconductor device according to the present invention. 本図に示すように、 As shown in the figure,
プリント配線基板1には、矩形でありサイズが等しい下層、上層の半導体チップ2、4がフェースアップ状態で、重なった状態から相互に平行な辺の方向にずらして積層実装される。 The printed circuit board 1, lower layer is a rectangle size is equal, the upper layer of the semiconductor chip 2 and 4 face-up state, are stacked and mounted by sliding it in the direction of the sides parallel to each other from the overlapping state.

【0019】プリント配線基板1は樹脂を基材として銅配線による電気回路を内蔵し、半導体チップ2、4は集積回路を内蔵する。 The printed circuit board 1 has a built-in electric circuits with copper interconnect the resin as a base material, the semiconductor chip 2 and 4 incorporates an integrated circuit. なお、半導体チップ2、4には、複数のボンディングパッドがそれぞれ設けられ、ボンディングパッドの各々は、半導体チップに内蔵する回路の入出力端子をそれぞれの表面に引き出す。 Incidentally, the semiconductor chip 2 and 4, a plurality of bonding pads are respectively provided, each of the bonding pads, elicit input and output terminals of the circuit incorporated in the semiconductor chip on each surface.

【0020】半導体チップ2、4の表面には配線層3、 [0020] On the surface of the semiconductor chip 2, 4 wiring layer 3,
5がそれぞれ形成される。 5 are formed. 配線層3、5は半導体チップ2、4と等しいサイズに形成され、ポリイミドとアルミニウムの層で積層され、内部に接続線、周辺端部に複数のボンディングパッドを有し、半導体チップのボンディングパッドを任意の位置に配置することを可能にする。 Interconnection layers 3 and 5 are formed to a size equal to the semiconductor chip 2 and 4, are stacked with a layer of polyimide and aluminum, the internal connection line, having a plurality of bonding pads on the peripheral edge, the bonding pads of the semiconductor chip It makes it possible to place in any position.

【0021】一例として、本図に示すように、配線層3 [0021] As an example, as shown in the figure, the wiring layer 3
の左側周辺端部30に設けられる複数のボンディングパッド31は、配線層3の内部の接続線で、下層の半導体チップ2のボンディングパッドと接続することにより、 A plurality of bonding pads 31 provided on the left side peripheral edge 30 of the inside of the connection line of the wiring layer 3, by connecting a lower layer of the bonding pads of the semiconductor chip 2,
半導体チップ2のボンディングパッドを左側周辺端部3 Left peripheral edge of the bonding pad of the semiconductor chip 2 3
0に配置する。 It is placed on the 0. 同様に、配線層5の右側周辺端部50に設けられる複数のボンディングパッド51は、配線層5 Similarly, a plurality of bonding pads 51 provided on the right side peripheral edge 50 of the wiring layer 5, the wiring layer 5
の内部の接続線で、上層の半導体チップ4のボンディングパッドと接続することにより、上層の半導体チップ4 Inside the connection line, by connecting the bonding pads of the upper semiconductor chip 4, the upper layer of the semiconductor chip 4
のボンディングパッドを右側周辺端部50に配置する。 Placing the bonding pad on the right peripheral edge 50.

【0022】上層の半導体チップ4と下層の半導体チップ2とが完全に積層した状態から上層の半導体チップ4 The upper layer of the semiconductor chip 4 and the lower layer from the state where the semiconductor chip 2 is completely laminated in the semiconductor chip 4
を右側にずらして、下層の半導体チップ2に積層し、接着剤6bで接着固定することにより、下層の半導体チップ2の左周辺端部30にボンディングパッドが形成されるようにする。 The shifting to the right, and lower layers of the semiconductor chip 2 by bonding fixed by the adhesive 6b, so that the bonding pad to the left peripheral edge 30 of the lower layer of the semiconductor chip 2 is formed. なお、下層の半導体チップ2の表面がプリント配線基板1と接着剤6aで接着固定される。 Incidentally, the lower surface of the semiconductor chip 2 are bonded with adhesive 6a and the printed wiring board 1.

【0023】プリント配線基板1には、配置された複数のボンディングパッド31、51に対応して、複数のボンディングパッド11a、11bがそれぞれ設けられる。 [0023] printed circuit board 1, corresponding to the arranged plurality of bonding pads 31 and 51 are a plurality of bonding pads 11a, 11b are respectively provided. 下層の半導体チップ2、上層の半導体チップ4に配置された複数のボンディングパッド31、51は、複数のワイヤ101a、101bを用いてワイヤボンディングにより、プリント配線基板1の複数のボンディングパッド11a、11bにそれぞれ電気的に接続される。 Lower semiconductor chip 2, a plurality of bonding pads 31 and 51 arranged on an upper layer of the semiconductor chip 4, a plurality of wires 101a, by wire bonding using 101b, a plurality of bonding pads 11a of the printed circuit board 1, the 11b each of which is electrically connected.

【0024】なお、半導体チップ2、4とプリント配線基板1との間の電気配線を行うワイヤ101a、101 [0024] Incidentally, the wire 101a, 101 for electrical wiring between the semiconductor chips 2 and 4 and the printed wiring board 1
bは、金、アルミニウム等の極細ワイヤからなる。 b gold, made of ultrafine wires, such as aluminum. このようして、下層の半導体チップ2と上層の半導体チップ4をずらして得られる領域に配線層3によりボンディングパッド31を設けるようにしたので、下層の半導体チップ2のワイヤボンディングが可能になる。 Thus to, since the wiring layer 3 in a region obtained by shifting the lower layer of the semiconductor chip 2 and the upper semiconductor chip 4 to provide a bonding pad 31, allowing wire bonding of the underlying semiconductor chip 2.

【0025】すなわち、半導体チップ2、半導体チップ4に配置されたボンディングパッド31、51を全てワイヤボンディングすることが可能になる。 [0025] That is, the semiconductor chip 2, it is possible to all the wire bonding of the bonding pads 31, 51 disposed in the semiconductor chip 4. 上層の半導体チップ4のボンディングパッド51は、下層の半導体チップ2のボンディングパッド31と反対側になるように配置されるので、ワイヤボンディングされるワイヤ10 The bonding pads 51 of the upper semiconductor chip 4 is disposed so as the bonding pads 31 of the lower semiconductor chip 2 becomes opposite, wire 10 is wire-bonded
1aと101bとの干渉を回避することが可能になる。 It is possible to avoid interference between 1a and 101b.

【0026】したがって、本発明によれば、従来のように、熱圧着による下層の半導体チップの破損が無くなり、接続状態の目視確認が可能になり、後工程に対する負荷が無くなる。 [0026] Thus, according to the present invention, unlike the conventional, there is no damage to the lower layer of the semiconductor chip by thermocompression bonding, visual confirmation of the connection state enables the load on the subsequent process is eliminated. 図2は図1の線A−Aについての断面を示す図である。 Figure 2 is a view showing a section of the line A-A of FIG. 本図に示すように、下層の半導体チップ2の表側にはボンディングパッド21a、21b等が設けられている。 As shown in the figure, the bonding pads 21a on the front side of the lower semiconductor chip 2, 21b and the like. 配線層3には複数の接続配線31aが設けられ、接続配線31aの各々により、配線層3の複数のボンディングパッド31と半導体チップ2の複数のボンディングパッド21a、21b等がそれぞれ接続される。 The wiring layer 3 is provided with a plurality of connection wires 31a, by each of the connecting wires 31a, a plurality of bonding pads 31 and a plurality of bonding pads 21a of the semiconductor chip 2 of the wiring layer 3, 21b, etc. are connected.

【0027】配線層5には複数の接続配線51aが設けられ、接続配線51aの各々により、配線層5の複数のボンディングパッド51と半導体チップ5の複数のボンディングパッド41a、41b等がそれぞれ接続される。 The plurality of connection wirings 51a is provided on the wiring layer 5, by each of the connecting wires 51a, a plurality of bonding pads 41a of the plurality of bonding pads 51 and the semiconductor chip 5 of the wiring layer 5, 41b, etc. are connected that. なお、通常、上層の半導体チップ4のボンディングパッドはワイヤボンディングが可能であるので、上層の半導体チップ4のボンディングパッドを配置しなおす必要が無い場合には、下層の半導体チップだけ配置しなおすようにしてもよい。 Normally, since the bonding pad of the upper semiconductor chip 4 is capable of wire bonding, when there is no need to re-arrange the bonding pads of the upper semiconductor chip 4, as rearranges only the lower layer of the semiconductor chip it may be. 図3は配線層3により下層の半導体チップ2のボンディングパッドを配置する例を示す図である。 Figure 3 is a diagram showing an example of placing a layer of bonding pads of the semiconductor chip 2 by the wiring layer 3. 本図(a)に示すように、下層の半導体チップ2の表面周辺端部には、複数のボンディングパッド21 As shown in the figure (a), in the surface peripheral edge of the lower semiconductor chip 2, a plurality of bonding pads 21
a、21b、21c、21dが設けられているとする。 a, 21b, 21c, and 21d are provided.

【0028】本図(b)に示すように、下層の半導体チップ2とサイズが等しくこれに積層する配線層3の一方の周辺端部30、例えば、図中の左側周辺端部30に複数のボンディングパッド31が配置される。 As shown in the figure (b), one of the peripheral edge 30 of the wiring layer 3 underlying the semiconductor chip 2 and the size is equal laminated thereto, for example, a plurality of the left peripheral edge 30 in FIG. bonding pads 31 are arranged. 周辺端部3 The peripheral edge 3
0は下層の半導体チップ2と上層の半導体チップ4(図1、2参照)により積層されない周辺端部である。 0 is the peripheral edge portion which is not laminated with a lower layer of the semiconductor chip 2 and the upper semiconductor chip 4 (see FIGS. 1 and 2). 配線層3の複数の配線31aにより、配線層3における複数のボンディングパッド31と下層の半導体チップ2における複数のボンディングパッド21a、21b、21 A plurality of wires 31a of the wiring layer 3, a plurality of bonding pads 21a at a plurality of bonding pads 31 and the underlying semiconductor chip 2 on the wiring layer 3, 21b, 21
c、21dとがそれぞれ接続される。 c, 21d and are respectively connected.

【0029】図4は配線層5により上層の半導体チップ4のボンディングパッドを配置する例を示す図である。 [0029] FIG. 4 is a diagram showing an example of placing a bonding pad of the upper semiconductor chip 4 by a wiring layer 5.
本図(a)に示すように、上層の半導体チップ4の表面周辺端部には、複数のボンディングパッド41a、41 As shown in the figure (a), in the surface peripheral edge of the upper semiconductor chip 4, a plurality of bonding pads 41a, 41
b、41c、41dが設けられているとする。 b, and 41c, 41d are provided. 本図(b)に示すように、下層の半導体チップ4とサイズが等しくこれに積層する配線層5の一方の周辺端部50、 As shown in the figure (b), one of the peripheral edge 50 of the wiring layer 5 lower semiconductor chip 4 and the size is equal laminated thereto,
例えば、図中の右側周辺端部50に複数のボンディングパッド51が配置される。 For example, a plurality of bonding pads 51 on the right side peripheral edge 50 in the drawing is arranged. 周辺端部50は下層の半導体チップ2と上層の半導体チップ4により積層されない周辺端部である。 Peripheral edge 50 is a peripheral edge portion which is not laminated with a lower layer of the semiconductor chip 2 and the upper semiconductor chip 4.

【0030】配線層5の複数の配線51aにより、配線層5における複数のボンディングパッド51と上層の半導体チップ4における複数のボンディングパッド41 [0030] The plurality of wires 51a of the wiring layer 5, a plurality of bonding pads 41 in a plurality of bonding pads 51 and the upper semiconductor chip 4 on the wiring layer 5
a、41b、41c、41dとがそれぞれ接続される。 a, 41b, 41c, and the 41d are respectively connected.
図5は図1におけるプリント配線基板1のボンディングパッド11a、11bを示す図である。 Figure 5 is a diagram showing a bonding pad 11a, 11b of the printed wiring board 1 in FIG. 1.

【0031】本図に示すように、プリント配線基板1には、接着固定される下層の半導体チップ2のボンディングパッド31の位置に対応してボンディングパッド11 As shown in the figure, the printed wiring board 1, a bonding pad 11 corresponding to the positions of the bonding pads 31 of the lower semiconductor chip 2 is bonded and fixed
aが設けられる。 a is provided. これに対して、下層の半導体チップ2 In contrast, a lower layer of the semiconductor chip 2
に積層される上層の半導体チップ4のずれを考慮して、 Taking into account the upper layer of the displacement of the semiconductor chip 4 to be laminated on,
上層の半導体チップ4のボンディングパッド51に対応するボンディングパッド11bがプリント配線基板1に設けられる。 Bonding pads 11b corresponding to the bonding pads 51 of the upper semiconductor chip 4 is provided on the printed circuit board 1.

【0032】なお、上記の説明では、上層の半導体チップ4のボンディングパッド51は、下層の半導体チップ2のボンディングパッド31と対向する側に設けたが、 [0032] In the above description, the bonding pads 51 of the upper semiconductor chip 4 is provided on the side facing the bonding pad 31 of the lower semiconductor chip 2,
分散して、積層されている非対向の周辺端部に設けてもよい。 Dispersed, may be provided on the peripheral edge of the non-facing are stacked. 配置の柔軟性を確保するためである。 It is to ensure the flexibility of the arrangement. 図6は図1 Figure 6 is a diagram 1
の半導体装置の製造方法の概略を説明するフローチャートである。 It is a flowchart for explaining the outline of the manufacturing method of the semiconductor device.

【0033】S401:下層、上層の各半導体チップ2、4のウェハ上に、配線層3、5を形成し、ボンディングパッドの再配置を行う。 [0033] S401: lower, on the upper layer of the wafer of the semiconductor chips 2 and 4, to form the wiring layers 3 and 5, to re-arrangement of the bonding pads. S402:各半導体チップをダイシングし、チップ化する。 S402: dicing each of the semiconductor chip, the chip.

【0034】ステップS403において、下層の半導体チップ2をフェースアップ状態でプリント配線基板1に接着固定する。 [0034] In step S403, the bonded and fixed to the lower layer of the semiconductor chip 2 on the printed circuit board 1 in a face-up state. ステップS404において、上層の半導体チップ4をフェースアップ状態で下層の半導体チップ2にずらして積層し、接着固定する。 In step S404, the upper layer of the semiconductor chip 4 are laminated by shifting the lower layer of the semiconductor chip 2 in a face-up state, it is bonded and fixed. ステップS405 Step S405
において、下層、上層の半導体チップ2、4とプリント配線基板1とをワイヤボンディングパッドで電気的に接続する。 In the lower layer, the upper layer of the semiconductor chip 2 and 4 and the printed wiring board 1 are electrically connected by wire bonding pad.

【0035】図7は図1の変形例であり、半導体チップを3層に積層する例を示す図である。 [0035] Figure 7 shows a modification of FIG. 1 is a diagram showing an example of stacking the semiconductor chips in three layers. 本図に示すように、半導体チップ4の上にさらにサイズが等しい半導体チップ302が積層される。 As shown in the figure, further size on the semiconductor chip 4 is a semiconductor chip 302 are stacked equal. 積層される半導体チップ3 Semiconductor chip 3 to be stacked
02は、半導体チップ4のボンディングパッド51と反対側にずらして、接着剤306aにより、半導体チップ4に接着固定される。 02 is shifted to the side opposite to the bonding pads 51 of the semiconductor chip 4, the adhesive 306a, is adhesively fixed to the semiconductor chip 4. これにより、下層の半導体チップ4と重ならない周辺端部300が半導体チップ表側に形成される。 Thus, the peripheral edge portion 300 which does not overlap with the underlying semiconductor chip 4 are formed on the semiconductor chip front side.

【0036】半導体チップ302には配線層303が設けられ、配線層303は、周辺端部300にボンディングパッド331を形成し、配線303aにより半導体チップ302の複数のボンディングパッド321a、32 The wiring layer 303 on the semiconductor chip 302 is provided, the wiring layer 303, a bonding pad 331 formed on the peripheral edge portion 300, a plurality of bonding pads 321a of the semiconductor chip 302 by wires 303a, 32
1bをボンディングパッド331に配列する。 1b the sequence to the bonding pad 331. 配線層3 Wiring layer 3
03の複数のボンディングパッド331は配線層5のボンディングパッド51とは反対側に位置する。 A plurality of bonding pads 331 of 03 is located on the side opposite to the bonding pads 51 of the wiring layer 5.

【0037】これにより、半導体チップ302のワイヤ301aと半導体チップ4のワイヤ101bが干渉しないようになる。 [0037] Thus, wires 301a and the semiconductor chip 4 wire 101b of the semiconductor chip 302 is prevented from interfering. このように、サイズが同じ半導体チップを3層に積層することにより、さらに、高密度実装が可能になる。 Thus, by the size to be laminated to the same semiconductor chip in three layers, further, allows high-density mounting. 図8は図1の変形例であり、下層の半導体チップ2に対して、中心を共通にして、上層の半導体チップ4を45度回転して積層し、重ならない4隅の領域にボンディングパッドを設置する例を示す図である。 Figure 8 is a modification of the FIG. 1, to the underlying semiconductor chip 2, and the center in common, the upper layer of the semiconductor chip 4 are laminated rotated 45 degrees, the bonding pads on the four corners of the regions which do not overlap is a diagram showing an example of installation.

【0038】本図に示すように、プリント配線基板1に接着固定された半導体チップ2に対して、半導体チップ4を45度回転して積層すると、半導体チップ2、半導体チップ4にはそれぞれ重ならない4つの隅の周辺端部71、72、73、74、周辺端部81、82、83、 As shown in the figure, the semiconductor chip 2 is adhered and fixed to the printed wiring board 1, when stacked by rotating the semiconductor chip 4 45 degrees, the semiconductor chip 2 do not overlap each of the semiconductor chips 4 the four corners of the peripheral edges 71, 72, 73 and 74, the peripheral edge 81, 82, 83,
84が形成される。 84 is formed. 半導体チップ2の4つの隅の周辺端部71、72、73、74にそれぞれ設けられた複数のボンディングパッドと対応するプリント配線基板1の複数のボンディングパッドとが、複数のワイヤ71c、7 A plurality of bonding pads of the printed wiring board 1 corresponding to the plurality of bonding pads provided in four corners of the peripheral edge 71, 72, 73 and 74 of the semiconductor chip 2 is a plurality of wires 71c, 7
2c、73c、74cを用いて、ワイヤボンディングによりそれぞれ電気的に接続される。 2c, 73c, 74c with, are electrically connected by wire bonding.

【0039】同様に、半導体チップ4の4つの隅の周辺端部81、82、83、84にそれぞれ設けられた複数のボンディングパッドと対応するプリント配線基板1の複数のボンディングパッドとが、複数のワイヤ81c、 [0039] Similarly, a plurality of bonding pads of the printed wiring board 1 corresponding to the plurality of bonding pads provided in four corners of the peripheral edge 81, 82, 83, 84 of the semiconductor chip 4, a plurality of wire 81c,
82c、83c、84cを用いてワイヤボンディングによりそれぞれ電気的に接続される。 82c, 83c, are electrically connected by wire bonding with 84c. 図9は図8の半導体チップ2、配線層3を説明する図である。 Figure 9 is a view for explaining the semiconductor chip 2, the wiring layer 3 in FIG. 8. 本図(a)に示すように、下層の半導体チップ2のフェースアップ側周辺端部には、複数のボンディングパッド21a、21 As shown in the figure (a), the face-up side peripheral edge of the lower semiconductor chip 2, a plurality of bonding pads 21a, 21
b、21c、21dが設けられているとする。 b, and 21c, 21d are provided.

【0040】本図(b)に示すように、下層の半導体チップ2とサイズが等しくこれに積層する配線層3の4つの隅の周辺端部71、72、73、74には複数のボンディングパッド71a、72a、73a、74aがそれぞれ配置される。 As shown in the figure (b), 4 single corners of the plurality of bonding pads on the peripheral edge 71, 72, 73 and 74 of the wiring layer 3 underlying the semiconductor chip 2 and the size is equal laminated thereto 71a, 72a, 73a, 74a are respectively disposed. 配線層3の複数の配線31aにより、 A plurality of wires 31a of the wiring layer 3,
配線層3における複数のボンディングパッド71a、7 A plurality of bonding pads 71a of the wiring layer 3, 7
2a、73a、74aと下層の半導体チップ2における複数のボンディングパッド21a、21b、21c、2 2a, 73a, 74a and a plurality of bonding pads 21a in the lower layer of the semiconductor chip 2, 21b, 21c, 2
1dとがそれぞれ接続される。 1d and are respectively connected.

【0041】図10は図8の半導体チップ4、配線層5 [0041] FIG 10 is a semiconductor chip 4 in FIG. 8, the wiring layer 5
を説明する図である。 Is a diagram illustrating a. 半導体チップ4、配線層5は中心を共通にして半導体チップ2、配線層3に対して45度回転した状態にある。 Semiconductor chip 4, the wiring layer 5 is in a state rotated 45 degrees with the center on a common semiconductor chip 2, the wiring layer 3. 本図(a)に示すように、下層の半導体チップ2のフェースアップ側周辺端部には、複数のボンディングパッド41a、41b、41c、41d As shown in the figure (a), the face-up side peripheral edge of the lower semiconductor chip 2, a plurality of bonding pads 41a, 41b, 41c, 41d
が設けられているとする。 And it is provided.

【0042】本図(b)に示すように、下層の半導体チップ2とサイズが等しくこれに積層する配線層3の4つの隅の周辺端部81、82、83、84には複数のボンディングパッド81a、82a、83a、84aがそれぞれ配置される。 [0042] As shown in the figure (b), 4 single corners of the plurality of bonding pads on the peripheral edge 81, 82, 83, 84 of the wiring layer 3 underlying the semiconductor chip 2 and the size is equal laminated thereto 81a, 82a, 83a, 84a are respectively disposed. 配線層5の複数の配線51aにより、 A plurality of wires 51a of the wiring layer 5,
配線層5における複数の81a、82a、83a、84 Multiple 81a in the wiring layer 5, 82a, 83a, 84
aボンディングパッドと下層の半導体チップ2における複数のボンディングパッド41a、41b、41c、4 A plurality of bonding pads 41a in a bonding pad and a lower layer of the semiconductor chip 2, 41b, 41c, 4
1dとがそれぞれ接続される。 1d and are respectively connected.

【0043】図11は図8におけるプリント配線基板1 [0043] Figure 11 is a printed wiring board 1 in FIG. 8
のボンディングパッドを示す図である。 It is a diagram showing a bonding pad. 本図に示すように、プリント配線基板1には、接着固定される下層の半導体チップ2の4つ隅の周辺端部71、72、73、7 As shown in the figure, the printed wiring board 1, four corners of the peripheral edge of the lower semiconductor chip 2 is bonded and fixed 71,72,73,7
4ではボンディングパッド71a、72a、73a、7 4, the bonding pads 71a, 72a, 73a, 7
4aに対応してボンディングパッド71b、72b、7 Bonding pads 71b corresponding to 4a, 72b, 7
3b、74bがそれぞれ設けられる。 3b, 74b are provided, respectively.

【0044】これに対して、プリント配線基板1には、 [0044] On the other hand, in the printed wiring board 1,
下層の半導体チップ2に回転して積層される上層の半導体チップ4の隅の周辺端部81、82、83、84では81a、82a、83a、84aボンディングパッドに対応してボンディングパッド81b、82b、83b、 The upper layer of the semiconductor chip 4 corners near the end portion 81, 82, 83, 84 81a stacked by rotating the lower layer of the semiconductor chip 2, 82a, 83a, bonding corresponding to 84a bonding pad pads 81b, 82b, 83b,
84bがそれぞれ設けられる。 84b are provided, respectively. このようにして、下層の半導体チップ2と上層の半導体チップ4を、それらの中心が同軸上になるように、積層できるため、半導体チップを積層する際の安定性が増し、各ワイヤ71c、72 In this manner, the lower layer of the semiconductor chip 2 and the upper semiconductor chip 4, so that their center is coaxial, it is possible to stack, increases the stability when stacking the semiconductor chip, the wires 71c, 72
c、73c、74c、81c、82c、83c、84c c, 73c, 74c, 81c, 82c, 83c, 84c
が半導体チップの4方向に引き出せるので、ワイヤ配線の自由度が増すという効果が発生する。 There therefore pulled out in the four directions of the semiconductor chip, the effect occurs that the degree of freedom of the wire wiring is increased.

【0045】図12は図1の変形例であり、下層の半導体チップ2と上層の半導体チップ4を完全に積層した状態から直交する辺の方向にずらして積層し、重ならない周辺端部30、50にボンディングパッドを設置する例を示す図である。 [0045] Figure 12 is a modification of FIG. 1, a lower layer of the semiconductor chip 2 and the upper semiconductor chip 4 are stacked by sliding it in the direction of the side perpendicular from a fully stacked state, the peripheral edge 30 which does not overlap, it is a diagram illustrating an example of installing the bonding pads 50. 本図に示すように、プリント配線基板1に接着固定された半導体チップ2に対して、半導体チップ4を完全に積層した状態から直交する辺の方向にずらして積層することにより、例えば、半導体チップ2に重ならない領域が図中の参照番号30で示す左側周辺端部と上側周辺端部に形成され、半導体チップ4に重ならない領域が図中の参照番号50で示す右側周辺端部と下側周辺端部に形成される。 As shown in the figure, the semiconductor chip 2 is adhered and fixed to the printed wiring board 1, by laminating by sliding it in the direction of the side perpendicular to the semiconductor chip 4 from a fully stacked state, for example, a semiconductor chip region not overlapping the 2 is formed in the left side peripheral edge portion and the upper peripheral edge indicated by reference numeral 30 in the figure, the right side peripheral edge indicating region which does not overlap the semiconductor chip 4 by the reference numeral 50 in the figure and the lower side It formed in the peripheral edge.

【0046】半導体チップ2の左側及び上側周辺端部3 The left and upper peripheral edge portion 3 of the semiconductor chip 2
0にそれぞれ設けられた複数のボンディングパッドと対応するプリント配線基板1の複数のボンディングパッドとが、複数のワイヤ101a、101cを用いてワイヤボンディングによりそれぞれ電気的に接続される。 0 to the plurality of bonding pads respectively provided a plurality of bonding pads of the corresponding printed circuit board 1 is electrically connected by wire bonding using the wires 101a, the 101c. 同様に、半導体チップ4の右側及び下側周辺端部50にそれぞれ設けられた複数のボンディングパッドと対応するプリント配線基板1の複数のボンディングパッドとが、複数のワイヤ101b、101dを用いてワイヤボンディングによりそれぞれ電気的に接続される。 Similarly, wire bonding using a plurality of bonding pads provided respectively on the right and lower peripheral edge 50 of the semiconductor chip 4 and a plurality of bonding pads of the corresponding printed circuit board 1 is, a plurality of wires 101b, the 101d It is electrically connected by.

【0047】図13は図12の半導体チップ2、配線層3を説明する図である。 [0047] Figure 13 is a semiconductor chip 2 in FIG. 12 is a diagram for explaining a wiring layer 3. 本図(a)に示すように、下層の半導体チップ2の表面周辺端部には、複数のボンディングパッド21a、21b、21c、21dが設けられているとする。 As shown in the figure (a), in the surface peripheral edge of the lower semiconductor chip 2, a plurality of bonding pads 21a, 21b, 21c, 21d are provided. 本図(b)に示すように、下層の半導体チップ2とサイズが等しくこれに積層する配線層3の左側及び上側周辺端部30に複数のボンディングパッド3 As shown in the figure (b), a lower layer of the semiconductor chip 2 and the plurality of bonding pads 3 on the left and upper peripheral edge 30 of the wiring layer 3 whose size is equal laminated thereto
1、32が配置される。 1, 32 is placed.

【0048】配線層3の複数の配線31aにより、配線層3における複数のボンディングパッド31、32と下層の半導体チップ2における複数のボンディングパッド21a、21b、21c、21dとがそれぞれ接続される。 [0048] The plurality of wires 31a of the wiring layer 3, a plurality of bonding pads 21a at a plurality of bonding pads 31, 32 and a lower layer of the semiconductor chip 2 on the wiring layer 3, 21b, 21c, and the 21d are respectively connected. 図14は図12の半導体チップ4、配線層5を説明する図である。 Figure 14 is a semiconductor chip 4 in FIG. 12 is a diagram for explaining a wiring layer 5. 本図(a)に示すように、上層の半導体チップ4の表面周辺端部には、複数のボンディングパッド41a、41b、41c、41dが設けられているとする。 As shown in the figure (a), in the surface peripheral edge of the upper semiconductor chip 4, a plurality of bonding pads 41a, 41b, 41c, 41d are provided.

【0049】本図(b)に示すように、下層の半導体チップ2とサイズが等しくこれに積層する配線層3の右側及び下側周辺端部50には複数のボンディングパッド5 [0049] As shown in the figure (b), a plurality of bonding pads 5 on the right side and the lower peripheral edge 50 of the wiring layer 3 underlying the semiconductor chip 2 and the size is equal laminated thereto
1、52が配置される。 1, 52 is placed. 配線層5の複数の配線51aにより、配線層5における複数の51、52ボンディングパッドと下層の半導体チップ2における複数のボンディングパッド41a、41b、41c、41dとがそれぞれ接続される。 A plurality of wires 51a of the wiring layer 5, a plurality of bonding pads 41a at a plurality of 51 bonding pads and the underlying semiconductor chip 2 on the wiring layer 5, 41b, 41c, and the 41d are respectively connected.

【0050】図15は図12におけるプリント配線基板1のボンディングパッドを示す図である。 [0050] Figure 15 is a diagram illustrating the bonding pads of the printed wiring board 1 in FIG. 12. 本図に示すように、プリント配線基板1には、接着固定される下層の半導体チップ2の左側及び上側周辺端部30のボンディングパッド31、32に対応してボンディングパッド1 As shown in the figure, the printed wiring on the substrate 1, a lower layer of the semiconductor chip 2 on the left side and bonding to correspond to the bonding pads 31 and 32 of the upper peripheral edge 30 pad is adhesively fixed 1
1a、11cがそれぞれ設けられる。 1a, 11c are respectively provided.

【0051】これに対して、プリント配線基板1には、 [0051] On the other hand, in the printed wiring board 1,
上層の半導体チップ4の右側及び下側周辺端部50の5 5 of the right and lower peripheral edge 50 of the upper semiconductor chip 4
1、52ボンディングパッドに対応してボンディングパッド11b、11dがそれぞれ設けられる。 Bonding pads 11b corresponding to the 1, 52 a bonding pad, 11d are respectively provided.

【0052】 [0052]

【発明の効果】以上説明したように、本発明によれば、 As described in the foregoing, according to the present invention,
下層の半導体チップ、上層の半導体チップの周辺部にボンディングパッドを配線層により配置し、下層の半導体チップ、上層の半導体チップの周辺部に配置されるボンディングパッドと重ならないように下層の半導体チップ、上層の半導体チップをずらして積層し、下層の半導体チップ、上層の半導体チップのボンディングパッドとプリント配線基板のボンディングパッドをワイヤボンディングにより電気的に接続するようにしたので、サイズが等しい半導体チップを積層する際に、下層の半導体チップとプリント配線基板とを熱圧着にする必要がなくなり、熱圧着による破損防止が可能になり、接続部位の目視確認を可能にでき、歩留まりを向上させることが可能になる。 Lower semiconductor chip, the upper layer of the bonding pad is arranged by the wiring layers in the peripheral portion of the semiconductor chip, the lower semiconductor chip, the upper layer of the semiconductor chip of the lower layer so as not to overlap with the bonding pads of the semiconductor chip disposed on the periphery, laminated by shifting the upper layer of the semiconductor chip, the laminated lower semiconductor chip, since the bonding pads of the bonding pads and the printed wiring board of the upper semiconductor chip so as to electrically connected by wire bonding, size equal semiconductor chip when, the lower semiconductor chip and the printed wiring board eliminates the need for the thermocompression bonding enables damage prevention by thermocompression bonding, it can enable the visual confirmation of the connection site, so it is possible to improve the yield Become.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明に係る半導体装置の概略を示す斜視図である。 Is a perspective view schematically showing a semiconductor device according to the invention; FIG.

【図2】図1の線A−Aについての断面を示す図である。 Figure 2 is a view showing a section of the line A-A of FIG.

【図3】配線層3により下層の半導体チップ2のボンディングパッドを配置する例を示す図である。 The Figure 3 the wiring layer 3 is a diagram showing an example of placing a layer of bonding pads of the semiconductor chip 2.

【図4】配線層5により上層の半導体チップ4のボンディングパッドを配置する例を示す図である。 The Figure 4 wiring layer 5 is a diagram showing an example of placing a bonding pad of the upper semiconductor chip 4.

【図5】図1におけるプリント配線基板1のボンディングパッド11a、11bを示す図である。 [5] Bonding pads 11a of the printed wiring board 1 in FIG. 1 is a diagram illustrating a 11b.

【図6】図1の半導体装置の製造方法の概略を説明するフローチャートである。 6 is a flowchart for explaining the outline of the manufacturing method of the semiconductor device in FIG.

【図7】図1の変形例であり、半導体チップを3層に積層する例を示す図である。 7 is a modification of FIG. 1 is a diagram showing an example of stacking the semiconductor chips in three layers.

【図8】図1の変形例であり、下層の半導体チップ2に対して、中心を共通にして、上層の半導体チップ4を4 8 is a modification of FIG. 1, to the underlying semiconductor chip 2, and the center in common, the upper layer of the semiconductor chip 4 to 4
5度回転して積層し、重ならない4隅の領域にボンディングパッドを設置する例を示す図である。 5 ° rotated by laminating a diagram showing an example of installing the bonding pads at four corners of the regions which do not overlap.

【図9】図8の半導体チップ2、配線層3を説明する図である。 [9] The semiconductor chip 2 in FIG. 8 is a diagram for explaining a wiring layer 3.

【図10】図8の半導体チップ4、配線層5を説明する図である。 [10] The semiconductor chip 4 in FIG. 8 is a diagram for explaining a wiring layer 5.

【図11】図8におけるプリント配線基板1のボンディングパッドを示す図である。 11 is a diagram illustrating the bonding pads of the printed wiring board 1 in FIG.

【図12】図1の変形例であり、下層の半導体チップ2 [Figure 12] is a variation of FIG. 1, a lower layer of the semiconductor chip 2
と上層の半導体チップ4を完全に積層した状態から2方向にずらして積層し、重ならない領域にボンディングパッドを設置する例を示す図である。 And an upper layer of the semiconductor chip 4 are stacked offset from fully stacked state in two directions is a diagram showing an example of installing a bonding pad in a region which does not overlap.

【図13】図12の半導体チップ2、配線層3を説明する図である。 [13] The semiconductor chip 2 in FIG. 12 is a diagram for explaining a wiring layer 3.

【図14】図12の半導体チップ4、配線層5を説明する図である。 [14] The semiconductor chip 4 in FIG. 12 is a diagram for explaining a wiring layer 5.

【図15】図12におけるプリント配線基板1のボンディングパッドを示す図である。 15 is a diagram illustrating the bonding pads of the printed wiring board 1 in FIG. 12.

【図16】本発明の前提となる半導体装置の概略を示す断面図である。 16 is a cross-sectional view schematically showing a premise comprising the semiconductor device of the present invention.

【符号の説明】 DESCRIPTION OF SYMBOLS

1…プリント配線基板 2、4、302…半導体チップ 3、5、303…配線層 6a、6b、306a…接着剤 11a、11b、11c、11d、21a、21b、2 1 ... printed circuit board 2,4,302 ... semiconductor chip 3,5,303 ... wiring layer 6a, 6b, 306a ... adhesive 11a, 11b, 11c, 11d, 21a, 21b, 2
1c、21d、41a、41b、41c、41d、3 1c, 21d, 41a, 41b, 41c, 41d, 3
1、32、51、52、71a、72a、73a、74 1,32,51,52,71a, 72a, 73a, 74
a、71b、72b、73b、74b、81a、82 a, 71b, 72b, 73b, 74b, 81a, 82
a、83a、84a、81b、82b、83b、84 a, 83a, 84a, 81b, 82b, 83b, 84
b、311a、321a、321b、331、…ボンディングパッド 30、50、71、72、73、74、81、82、8 b, 311a, 321a, 321b, 331, ... bonding pad 30,50,71,72,73,74,81,82,8
3、84、300…周辺端部 31a、51a、303a…接続線 101a、101b、101c、101d、301a、 3,84,300 ... peripheral edge 31a, 51a, 303a ... connection lines 101a, 101b, 101c, 101d, 301a,
71c、72c、73c、74c、81c、82c、8 71c, 72c, 73c, 74c, 81c, 82c, 8
3c、84c…ワイヤ 3c, 84c ... wire

Claims (9)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 サイズの等しい半導体チップがプリント配線基板に積層される半導体装置において、 下層の前記半導体チップと上層の前記半導体チップをずらして積層することにより積層されない周辺端部にボンディングパッドを形成するためのボンディングパッド用周辺端部と、 前記ボンディングパッド用周辺部に下層の前記半導体チップ、上層の半導体チップのボンディングパッドを配置する配線層とを備えることを特徴とする半導体装置。 1. A semiconductor device size equal the semiconductor chip is stacked on the printed circuit board, forming a bonding pad on the peripheral edge portion which is not laminated by laminating shifted lower layer of the semiconductor chip and the layer of the semiconductor chip a semiconductor device and a peripheral edge bonding pads, a lower layer of the semiconductor chip in the peripheral portion for the bonding pad, comprising: a wiring layer to place a bonding pad of the upper semiconductor chip for.
  2. 【請求項2】 サイズの等しい半導体チップがプリント配線基板に積層される半導体装置において、 下層の前記半導体チップと上層の前記半導体チップをずらして積層することにより積層されない周辺端部にボンディングパッドを形成するためのボンディングパッド用周辺端部と、 下層の前記半導体チップの前記ボンディングパッド用周辺部にボンディングパッドを配置する配線層とを備えることを特徴とする半導体装置。 2. A semiconductor device size equal the semiconductor chip is stacked on the printed circuit board, forming a bonding pad on the peripheral edge portion which is not laminated by laminating shifted lower layer of the semiconductor chip and the layer of the semiconductor chip a peripheral edge bonding pads for the semiconductor device characterized by comprising a wiring layer to place a bonding pad in the peripheral portion for bonding pads of the lower layer of the semiconductor chip.
  3. 【請求項3】 前記周辺部は、それぞれが矩形である下層の前記半導体チップと上層の前記半導体チップとが積層された状態から上層の前記半導体チップを平行な辺の方向にずらすることにより、下層の前記半導体チップに形成されることを特徴とする、請求項1又は請求項2に記載の半導体装置。 Wherein the peripheral unit, by each of which Shifts from a state where the lower layer of the semiconductor chip and an upper layer of the semiconductor chip is rectangular laminated an upper layer of the semiconductor chip in a direction parallel sides, characterized in that it is formed in a lower layer of the semiconductor chip, the semiconductor device according to claim 1 or claim 2.
  4. 【請求項4】 前記周辺部は、それぞれが矩形である下層の前記半導体チップと上層の前記半導体チップとが積層された状態から上層の前記半導体チップを回転してずらすことにより、下層の前記半導体チップに形成されることを特徴とする、請求項1又は請求項2に記載の半導体装置。 Wherein said peripheral portion, by each shift from a state where the lower layer of the semiconductor chip and an upper layer of the semiconductor chip is rectangular stacked by rotating the upper layer of the semiconductor chip, the lower layer of the semiconductor characterized in that it is formed in the chip, the semiconductor device according to claim 1 or claim 2.
  5. 【請求項5】 前記周辺部は、それぞれが矩形である下層の前記半導体チップと上層の前記半導体チップとが積層された状態から上層の前記半導体チップを直交する辺の方向にずらすることにより、下層の前記半導体チップに形成されることを特徴とする、請求項1又は請求項2 Wherein said peripheral portion, by which the semiconductor chip of the lower layer each has a rectangular and the upper layer of the semiconductor chip is Shifts in the direction of the side perpendicular to the upper layer of the semiconductor chip from the state of being stacked, characterized in that it is formed in a lower layer of the semiconductor chip, according to claim 1 or claim 2
    に記載の半導体装置。 The semiconductor device according to.
  6. 【請求項6】 前記配線層はポリイミド、アルミニウムにより構成されることを特徴とする、請求項1又は請求項2に記載の半導体装置。 Wherein said wiring layer is characterized in that it is constituted of polyimide, of aluminum, semiconductor device according to claim 1 or claim 2.
  7. 【請求項7】 下層の前記半導体チップと上層の前記半導体チップをずらして半導体チップを2層又は3層に積層することを特徴とする、請求項1に記載の半導体装置。 7., characterized in that laminated to two or three layers of semiconductor chip by shifting the lower layer of the semiconductor chip and the upper layer of the semiconductor chip, the semiconductor device according to claim 1.
  8. 【請求項8】 ずらして積層された下層の前記半導体チップと上層の前記半導体チップとについて配置されたボンディングパッドに対応して、プリント配線基板のボンディングパッドを配置することを特徴とする、請求項1 8. shifting in response to stacked lower layer of the semiconductor chip and an upper layer of the semiconductor chip and the bonding pads arranged on it, characterized by arranging the bonding pads of the printed wiring board, according to claim 1
    又は請求項2に記載の半導体装置。 Or a semiconductor device according to claim 2.
  9. 【請求項9】 サイズの等しい半導体チップがプリント配線基板に積層される半導体装置の製造方法において、 下層の前記半導体チップ、上層の前記半導体チップの周辺部にボンディングパッドを配線層により配置する工程と、 下層の前記半導体チップ、上層の半導体チップの周辺部に配置される前記ボンディングパッドと重ならないように下層の半導体チップと上層の半導体チップをずらして積層する工程と、 下層の前記半導体チップと上層の前記半導体チップのボンディングパッドと前記プリント配線基板のボンディングパッドをワイヤボンディングにより電気的に接続することを特徴とする半導体装置の製造方法。 9. size equal the semiconductor chip in the manufacturing method of the semiconductor device to be laminated to the printed wiring board, placing the wiring layer bonding pad lower layer of the semiconductor chip, the peripheral portion of the upper layer of the semiconductor chip a step of laminating by shifting the lower layer of the semiconductor chip, the lower semiconductor chip so as not to overlap with the bonding pads arranged on the periphery of the upper semiconductor chip and the upper semiconductor chip, the lower layer of the semiconductor chip and the upper the manufacturing method of a semiconductor device and a semiconductor chip bonding pad of the bonding pads of the printed wiring board, characterized in that electrically connected by wire bonding.
JP2001010893A 2001-01-19 2001-01-19 Semiconductor device and method of manufacturing the same Pending JP2002217356A (en)

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