TWI236117B - Semiconductor package with a heat sink - Google Patents

Semiconductor package with a heat sink Download PDF

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Publication number
TWI236117B
TWI236117B TW092104001A TW92104001A TWI236117B TW I236117 B TWI236117 B TW I236117B TW 092104001 A TW092104001 A TW 092104001A TW 92104001 A TW92104001 A TW 92104001A TW I236117 B TWI236117 B TW I236117B
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TW
Taiwan
Prior art keywords
chip
substrate
heat dissipation
wafer
bumps
Prior art date
Application number
TW092104001A
Other languages
English (en)
Other versions
TW200416980A (en
Inventor
Sung-Fei Wang
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW092104001A priority Critical patent/TWI236117B/zh
Priority to US10/605,163 priority patent/US7026719B2/en
Publication of TW200416980A publication Critical patent/TW200416980A/zh
Application granted granted Critical
Publication of TWI236117B publication Critical patent/TWI236117B/zh

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    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
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Description

1236117 差號
五、發明說明（1) 發明所屬之技射 本發明是有關於一錄且古# # ^ ^ 細，Η拄則a古M #、種具有政熱構件之多晶片封裝模 片封裝】組 種散熱性佳之具有散熱構件之多晶 先前技術 τΓΜαίϊ ‘體產業中，積體電路（Integrated Circuits， 1C)的生產，主要分為二個階段：積體 的封裝（Package)等。其中，裸晶-片係經 ^ ^ ^ 冤路叹计、光罩製作以及切割晶圓 ^步，，元成，而每一顆由晶圓切割所形成的裸晶片，經 ^稞Bs片上之焊墊（B〇nding Pad)與外部訊號電性連接 t，膠材料將裸晶片包覆著，其封裝之目的在於防 π ϊ i f文到濕氣、熱量、雜訊的影響，並提供裸晶片與 ° :，比如與印刷電路板（Printed Circuit Board, ϋ i:他封裝用基板之間電性連接的媒介，如此即完成 積體電、路的封裝（Package)步驟。 省a , w為了連接上述之裸晶片和封裝用基板，通常會使用 ί、ti π Υ1作為接合之媒介。隨著晶片積集度的增加，多 II® 于裝（Multl-Chip Module， MCM)已逐漸成為未來 t ΐ ί ί的主要趨勢，其中多晶片模組封裝係例如將多個 曰曰、t在一塊基板上，而多個晶片之間比如藉由基板彼 此電性連接’以構成一具有完整功能的多封裝模組之封裝 結構。 以動怒隨機存取記憶體（d y n a m i c r a n d 〇 m a c c e s s memory ’ DRAM)以及中央處理器（CPU)為例，利用多晶片模
10230twf1.ptc 第5頁 1236117 _案號92104001_年月日__ 五、發明說明（2) 組封裝（MCM)的封裝結構可將多個DRAM以及中央處理器 (CPU )封裝在同一個基板上，如此不僅提高構裝密度、減 少空間需求，也降低了封裝模組之間訊號延遲的現象，以 達到高速處理的目的，因此廣泛被應用在通訊及攜帶式電 子產品中。 請參照第1圖，其繪示習知多晶片封裝模組之剖面示 意圖。晶片封裝模組1 0 0包括一基板1 1 0、二晶片1 3 0、 1 5 0、一封裝材料1 7 0、多條導線1 8 0、1 8 2及多個焊球 184。其中基板110具有一上表面112及一下表面122，並且 基板1 1 0還具有一晶片座1 1 4、多個接點1 1 6、1 2 4，其中晶 片座1 1 4及接點1 1 6係配置在基板1 1 0之上表面1 1 2上，而接 點1 1 6係環繞在晶片座1 1 4的周圍；接點1 2 4係配置在基板 110之下表面122上。 晶片130具有一主動表面132及對應之一背面142，並 且晶片1 3 0還具有接點1 3 4、1 3 6，均環繞在晶片1 3 0之主動 表面1 3 2上的周圍位置，且接點1 3 4所環繞的位置係位在接 點1 3 6所環繞的位置之外部。而晶片1 3 0係以其背面1 4 2並 藉由一黏著材料1 4 4貼附在基板1 1 0之晶片座1 1 4上。並且 藉由打線的方式，透過導線1 8 0可以使晶片1 3 0與基板1 1 0 電性連接，而導線1 8 0之一端係接合到晶片1 3 0之接點1 3 4 上，導線1 8 0之另一端係接合到基板1 1 0之接點1 1 6上。 晶片150具有一主動表面152及對應之一背面162，並 且晶片1 5 0還具有接點1 5 4，環繞在晶片1 5 0之主動表面1 5 2 上的周圍位置。而晶片1 5 0係以其背面1 6 2並藉由一黏著材 料1 6 4貼附在晶片1 3 0之主動表面1 3 2上的中間區域。並且
10230twfl.ptc 第6頁 1236117 _案號92104001_年月日_iMz_ 五、發明說明（3) 藉由打線的方式，透過導線1 8 2可以使晶片1 3 0、1 5 0間電 性連接，而導線1 8 2之一端係接合到晶片1 5 0之接點1 5 4 上，導線1 8 2之另一端係接合到晶片1 3 0之接點1 3 6上。 另外，封裝材料1 7 0係包覆晶片1 3 0、1 5 0、基板1 1 0 之上表面1 1 2及導線1 8 0、1 8 2。而焊球1 8 4係配置在基板 1 1 0之接點1 2 4上。 在上述的晶片封裝模組1 0 0中，係藉由導線1 8 0使晶 片1 3 0與基板1 1 0電性連接，而藉由導線1 8 2使晶片1 3 0、 1 5 0間電性連接，然而由於導線1 8 0、1 8 2的截面積甚小並 且長度甚長，使得訊號會被快速地衰減，並且會有訊號延 遲的現象，而在高頻電路運作時，會有電感電容寄生效應 (P a r a s i t i c s )的發生，以致產生訊號反射的情形。如上所 述，利用導線1 8 0、1 8 2作為電性傳輸的媒介，會有嚴重的 雜訊問題，並且電性品質甚低。 值得注意的是，當晶片1 3 0、1 5 0在高頻運作下，由 於晶片130、150會產生介電耗損而產生大量的熱量，如此 將導致晶片1 3 0、1 5 0之本身的溫度逐漸升高。當晶片 130、150之本身的溫度一旦超出其正常的工作溫度範圍 時，晶片1 3 0、1 5 0之内部電路可能會發生運算錯誤的現 象，或是暫時性地失效。然而，習知晶片封裝模組1 0 0係 藉由封裝材料1 7 0及基板1 1 0將熱量散溢至外界，但是封裝 材料1 7 0及基板1 1 0的熱傳導係數均甚差，導致晶片1 3 0、 1 5 0所產生之熱量無法有效地散溢至外界，嚴重時將造成 晶片的運算錯誤或失效。 發明内容
10230twf1.ptc 第7頁 1236117 _案號92104001_年月日_«_ 五、發明說明（4) 有鑑於此，本發明的目的是提出一種具有散熱構件 之多晶片封裝模組，可以大幅提昇晶片之散熱效率。 在敘述本發明之前，先對空間介詞的用法做界定， 所謂空間介詞π上π係指兩物之空間關係係為可接觸或不可 接觸均可。舉例而言，Α物在Β物上，其所表達的意思係為 A物可以直接配置在B物上，A物有與B物接觸；或者A物係 配置在B物上的空間中，A物沒有與B物接觸。 為達本發明之上述目的，提出一種具有散熱構件之 晶片封裝模組，至少包括一第一晶片、一第二晶片、一散 熱構件及一基板，而第一晶片具有一主動表面，而第二晶 片配置在該第一晶片之主動表面上，散熱構件配置在第一 晶片上，並且基板係與第一晶片接合。 依照本發明之一較佳實施例，基板具有一開口，開 口係貫穿基板，且可以容納散熱構件及第二晶片。或者， 開口亦可以是未貫穿基板的型態，此時基板還具至少一導 熱孔，貫穿基板，導熱孔的一端係暴露在基板之開口處， 並與散熱構件導熱性連接。而一填充材料可以填入於基板 之開口中。 另外，散熱構件可以配置在第一晶片之主動表面上 或與主動表面對應之背面上。而第一晶片可以透過凸塊接 合與第二晶片、基板及散熱構件接合，或者第一晶片及第 二晶片可以藉由打線的方式與基板電性連接。 為讓本發明之上述目的、特徵、和優點能更明顯易 懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說 明如下：
10230twf1.ptc 第8頁 1236117 _案號 921040m_年月日__ 五、發明說明（5) 實施方式 請參照第2圖，其繪示依照本發明第一較佳實施例之 一種具有散熱構件之晶片封裝模組之剖面放大圖。晶片封 裝模組2 0 0包括一基板21 〇、二晶片2 3 0、2 5 0、一散熱構件 2 7 0、多個凸塊2 8 0、2 8 2、2 8 4及多個焊球2 8 6。其中基板 210具有一上表面212及一下表面222，並且基板210還具有 一開口 2 1 4、多個接點2 1 6、2 2 4，其中開口 2 1 4係貫穿基板 2 1 0，而接點2 1 6係配置在基板2 1 0之上表面1 1 2上環繞於開 口 214的周圍；接點224係配置在基板210之下表面222上。 而焊球2 8 6係配置在基板210之接點2 2 4上，並與基板210之 接點2 2 4電性連接。 晶片230具有一主動表面232，並且晶片230還具有接 點234、236、238，均配置在晶片230之主動表面232上， 其中接點2 3 4係環繞在晶片2 3 0之主動表面2 3 2上的周圍位 置，且包圍接點2 3 6、2 3 8。而晶片2 3 0係藉由凸塊2 8 0與基 板2 1 0接合且電性連接，其中凸塊2 8 0係配置在晶片2 3 0之 接點2 3 4與基板2 1 0之接點2 1 6之間。 晶片250具有一主動表面252，並且晶片250還具有接 點2 5 4，係以矩陣的形式配置在晶片2 5 0之主動表面2 5 2 上。晶片250係配置在晶片230之主動表面232上，且基板 2 1 0的開口 2 1 4可以容納晶片2 5 0 ，而晶片2 5 0係藉由凸塊 2 8 2與晶片2 3 0接合且電性連接，其中凸塊2 8 2係配置在晶 片2 3 0之接點2 3 6與晶片2 5 0之接點2 5 4之間。 散熱構件2 7 0係配置在晶片2 3 0之主動表面2 3 2上，且 基板210的開口214可以容納散熱構件27〇，而散熱構件27〇
第9頁 月 曰 1236117 案號 92104001 五、發明說明（6) ，，由凸塊2 84與晶片2 3 0接合，其中凸塊284的一端係與 :片2 3 0之接點2 3 8接合，而凸塊284的另一端係與散熱構 1 # 〇#接a 。其中散熱構件2 7 〇比如是無電性功能的晶片， 二材貝可以是由石夕所構成，而凸塊284係不具訊號傳輸功 凸塊。另外，還可以在散熱構件2 7 〇的表面鍍金，以 曰口散熱構件2 7 0與晶片2 3 0之間的接合性，且亦可以增加 放…、構^牛^ 7 0，母板3 〇 〇 (繪示於第3圖）之間的接合性。 一 明參照第3圖’其緣示依照本發明第一較佳實施例之 ，士有政熱構件之晶片封裝模組配置在母板上的剖面放 :意圖。透過迴焊的步驟，藉由焊球2 8 6可以將晶片封 j模組2 0 0裝配到一母板3〇〇上，而母板3〇〇具有一表面 w a ’、，且母板3 〇 〇還具有多個接點3 0 4、一晶片接合區域 f 一散熱構件接合區域3〇8，均配置在母板30 〇之表面 el而接點3〇4係位在晶片接合區域3〇6及散熱構件接 的周圍。其中，晶片封裝模組2 0 0之焊球2 8 6會 ;汰t 〇之接點3 0 4接合並電性連接，而導熱材料3 1 2係 ί I #曰曰片2 5 〇與母板3 〇 〇之晶片接合區域3 0 6之間，藉由 ^ f ·材、胃料3 1 2可以將熱量快速地從晶片2 5 0傳導至母板 播杜’拉^人熱材料314係塗佈在散熱構件27 〇與母板3 00之散熱 ϊϊίΐί域3 0 8之間，藉由導熱材料314可以將熱量快速 地從政熱構件2 7 0傳導至母板300。 考_ ^在上述的晶片封裝模組2 0 0中，晶片2 3 0比如是中央 ^，而晶片2 5 0比如是記憶體。當晶片2 3 〇在高頻運作 持9 S /因為介電耗損而產生大量的熱量，此時可以透過凸 塊284、散熱構件27〇及導熱材料314將晶片23〇所產生的熱
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五、發明說明（7) 量快速地傳導至外界，以及透過凸塊2 8 2、晶片2 5 〇及、曾 材料3 1 2將晶片2 3 0所產生的熱量快速地傳導至外界。2熱 所述，本發明之晶片封裝模組2 0 0具有甚佳的散熱效果°。上 然而，本發明的應用並非限於此，請參照第4圖，° 繪示依照本發明第二較佳實施例之一種具有散熱構;之f 片封裝模組之剖面放大圖，其中若是本實施例中的標號^ 第一較佳貫施例一樣者’則表不在本貫施例中所指^的^ 件係雷同於在第一較佳實施例中所指明的構件，在此$ # 再贅述。在本實施例中，晶片封裝模組2 0 2還包括_填充P 材料3 2 0，比如利用點膠的方式填入到基板2 1 〇之開口 ^ i 4 中、晶片2 3 0、2 5 0之間、晶片2 3 0與散熱構件2 7 0之間及晶 片230與基板210之間，以包覆晶片250、散熱構件27q及& jt免2 8 0、2 8 2、2 8 4 ° 然而，本發明的應用並非限於此，請參照第5圖，立 繪示依照本發明第三較佳實施例之一種具有散熱構件之曰^ 片封裝模組之剖面放大圖，其中若是本實施例中的標號與 第一、第二較佳實施例一樣者，則表示在本實施例中所指 明的構件係雷同於在第一、第二較佳實施例中所指明的才^ 件’在此便不再贅述。在本實施例中，晶片封裝模組2 〇 4 還包括一封裝材料3 2 2，比如利用灌模的方式灌入到模具 (未繪示）之模穴（未繪示）中以包覆基板210之上表面212、 填充材料3 2 0及晶片2 3 0之側壁2 4 4，而晶片2 3 0的背面2 4 2 會貼附模穴之一表面，在進行脫膜之後，晶片2 3 0的背面 242會暴露於外。 在前述的較佳實施例中，基板之開口係貫穿基板，
10230twf1.ptc 第11頁 1236117 案號 92104001 五、發明說明（8) 然而本發明的應用並非限於此，如第6圖所示，其繪示依 照本發明第四較佳實施例之一種具有散熱構件之晶月封裝 模組配置在母板上的剖面放大示意圖，其中若是本實施例 中的標號與第一較佳實施例一樣者，則表示在本實施例中 所指明的構件係雷同於在第一較佳實施例中所指明的構 件，在此便不再贅述。在本實施例之晶片封裝模組4 〇 〇 中’基板410之凹穴414具有一底部416，而基板41〇還具多 個導熱孔418貫穿基板410，而導熱孔418的一端係暴露在 基板410之凹穴414的底部416，導熱孔418的另一端係與焊 球48 6接合，而基板41 〇透過焊球4 86可以與母板5〇〇接合。 ，熱材料5 1 2係塗佈在晶片2 5 0與凹穴4 1 4之底部4 1 6之間， 藉由導熱材料5 1 2可以將熱量快速地從晶片2 5 〇傳導至基板 410，透過基板410之導熱孔418及焊球48 6可以將熱量傳導 至母板5 0 0上；而導熱材料514係塗佈在散熱構件2 與基 板4 1 0之底部4 1 6之間，藉由導熱材料5 1 4可以將埶量快速 地從散熱構件270傳導至基板410，透過基板41〇；；導熱孔 4Λ8η^ϊΪ486可以將熱量傳導至母板5 0 0上。晶片封裝模 、、且 逛匕括一填充材料5 2 0，比如利用點膠的方式填入到 ί 凹穴414中、晶片2 3 0 、25 0之間、晶片2 3 0與散 間及晶片2 3 0與基板410之間，以包覆晶片 2 5 0、政熱構件27〇及凸塊28〇、282、2 84。 除此之外，在前述的較佳實施例中，第一晶片均是 透過凸塊與散熱構件接合，然而本發明並不限於此，第一 ^7片^30亦可以利用一導熱膠289與散熱構件2 7 0接合，如 弟圖所不，其繪示依照本發明第五較佳實施例之一種具 第12頁 10230twf1.ptc 1236117 _案號92104001_年月日_iMi_ 五、發明說明（9) 有散熱構件之晶片封裝模組的剖面放大示意圖，其中若是 本實施例中的標號與第一較佳實施例一樣者，則表示在本 實施例中所指明的構件係雷同於在第一較佳實施例中所指 明的構件，在此便不再贅述。 另外，在第一晶片上並非僅限於與一個第二晶片接 合或一個散熱構件接合，亦可以是與多個第二晶片接合或 多個散熱構件接合。 綜上所述，本發明之具有散熱構件之多晶片封裝模 組，由於在第一晶片之主動表面上除了配置有第二晶片， 並且還配置有散熱構件，因此第一晶片可以透過散熱構件 的配置使第一晶片所產生的熱量快速地傳導至外界，故具 有甚佳的散熱效果。 雖然本發明已以一較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍内，當可作各種之更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者為準。
10230twf1.ptc 第13頁 1236117 _案號92104001_年月曰 修正_ 圖式簡單說明 第1圖繪示習知晶片封裝模組之剖面示意圖。 第2圖繪示依照本發明第一較佳實施例之一種具有散 熱構件之晶片封裝模組之剖面放大圖。 第3圖繪示依照本發明第一較佳實施例之一種具有散 熱構件之晶片封裝模組配置在母板上的剖面放大示意圖。 第4圖繪示依照本發明第二較佳實施例之一種具有散 熱構件之晶片封裝模組之剖面放大圖。 第5圖繪示依照本發明第三較佳實施例之一種具有散 熱構件之晶片封裝模組之剖面放大圖。 第6圖所示，其繪示依照本發明第四較佳實施例之一 種具有散熱構件之晶片封裝模組配置在母板上的剖面放大 示意圖。 第7圖所示繪示依照本發明第五較佳實施例之一種具 有散熱構件之晶片封裝模組的剖面放大示意圖。 圖式標示說明 1 00 晶 片 封 裝模組 110: 基 板 1 12 上 表 面 114 晶 片 座 1 16 接 點 122 下 表 面 1 24 接 點 130 晶 片 1 32 主 動 表 面 134 接 點 1 36 接 點 142 背 面 1 44 黏 著 材 料 150 晶 片 1 52 主 動 表 面 154 接 點
10230twf1.ptc 第14頁 1236117 _案號92104001_年月日 修正 圖式簡單說明 156 接 點 162 • 背 面 164 黏 著 材 料 170 • 封 裝 材 料 180 導 線 182 導 線 200 晶 片 封 裝 模 組 202 晶 片 封 裝 模 組 210 基 板 212 • 上 表 面 2 14 開 α 216 • 接 點 222 下 表 面 224 • 接 點 230 晶 片 232 主 動 表 面 234 接 點 236 接 點 238 接 點 242 • 背 面 244 側 壁 250 • 晶 片 252 主 動 表 面 254 接 點 270 散 熱 構 件 280 凸 塊 282 凸 塊 284 ： 凸 塊 286 焊 球 289 ： 導 熱 膠 300 母 板 302 • 表 面 304 接 點 306 晶 片 接 合 區 域 308 散 熱 構 件 接 合區 域 312 導 熱 材 料 314 • 導 熱 材 料 320 填 充 材 料 322 封 裝 材 料 400 晶 片 封 裝 模 組 410 基 板 412 • 上 表 面 414 凹 穴 416 • 底 部 418 導 熱 孔 486 • 焊 球
10230twf1.ptc 第15頁 1236117 _案號92104001_年月日_修正 圖式簡單說明 500 母 板 512 • 導 熱 材 料 514 導 熱 材 料 520 • 填 充 材 料 600 晶 片 封 裝模組 6 10 • 基 板 612 上 表 面 614 • 開 σ 616 接 點 6 18 ·· 接 點 622 下 表 面 624 • 接 點 630 晶 片 632 • 主 動 表 面 634 接 點 642 • 背 面 644 黏 著 材 料 650 晶 片 652 主 動 表 面 654 接 點 662 背 面 664 • 黏 著 材 料 670 散 熱 構 件 680 導 線 682 導 線 684 • 凸 塊 686 焊 球 690 • 封 裝 材 料 692 填 充 材 料 700 • 母 板 714 導 熱 材 料
10230twf1.ptc 第16頁

Claims (1)

1236117 _案號92104001_年月日_魅_ 六、申請專利範圍 1 · 一種具有散熱構件之多晶片封裝模組，至少包括： 一基板，具有一開口 ，貫穿該基板； 複數個第一凸塊； 一第一晶片，具有一主動表面，該第一晶片係以其 該主動表面並藉由該些第一凸塊與該基板接合並與該基板 電性連接，而該第一晶片之該主動表面係朝向該基板之該 開口 ； 複數個第二凸塊； 至少一第二晶片，容納在該基板之該開口中，並且 該第二晶片藉由該些第二凸塊與該第一晶片之該主動表面 接合，並且該第二晶片透過該些第二凸塊與該第一晶片電 性連接；以及 至少一散熱構件，容納在該基板之該開口中，並且 該散熱構件與該第一晶片之該主動表面接合。 2 .如申請專利範圍第1項所述之具有散熱構件之多晶 片封裝权組9逛包括一填充材料’係填充在該基板之該開 口中、該第一晶片與該第二晶片之間及該第一晶片與該基 板之間，並且該填充材料還包覆該些第一凸塊及該些第二 凸塊。 3. 如申請專利範圍第1項所述之具有散熱構件之多晶 片封裝模組，其中該散熱構件係不具訊號傳輸功能之晶 4. 如申請專利範圍第1項所述之具有散熱構件之多晶 片封裝模組，其中該散熱構件之表面鍍金。
10230twf1.ptc 第17頁 1236117 _案號92104001_年月曰 修正_ 六、申請專利範圍 5 ·如申請專利範圍第1項所述之具有散熱構件之多晶 片封裝模組，還包括複數個第三凸塊，該散熱構件藉由該 些第三凸塊與該第一晶片之該主動表面接合，且該些第三 凸塊係不具訊號傳輸功能之凸塊。 6 .如申請專利範圍第1項所述之具有散熱構件之多晶 片封裝模組，還包括一導熱膠，該散熱構件藉由該導熱膠 與該第一晶片之該主動表面接合。 7. —種具有散熱構件之多晶片封裝模組，至少包 括： 一基板，具有一凹穴及複數個導熱孔，該些導熱孔 係貫穿該基板，並且該些導熱孔之一端係暴露在該凹穴 處； 複數個第一凸塊； 一第一晶片，具有一主動表面，該第一晶片係以其 該主動表面並藉由該些第一凸塊與該基板接合並與該基板 電性連接，而該第一晶片之該主動表面係朝向該基板之該 凹穴； 複數個第二凸塊； 至少一第二晶片，容納在該基板之該凹穴中並與該 基板之該些導熱孔導熱性連接，該第二晶片藉由該些第二 凸塊與該第一晶片之該主動表面接合，並且該第二晶片透 過該些第二凸塊與該第一晶片電性連接；以及 至少一散熱構件，容納在該基板之該凹穴中並與該 基板之該些導熱孔導熱性連接，且該散熱構件與該第一晶
10230twf1.ptc 第18頁 1236117 _案號92104001_年月日_iMz_ 六、申請專利範圍 片之該主動表面接合。 8 .如申請專利範圍第7項所述之具有散熱構件之多晶 片封裝模組，還包括一填充材料，係填充在該基板之該凹 穴中、該第一晶片與該第二晶片之間及該第一晶片與該基 板之間，並且該填充材料還包覆該些第一凸塊及該些第二 凸塊。 9 .如申請專利範圍第7項所述之具有散熱構件之多晶 片封裝模組，其中該散熱構件之材質包括矽。 1 0 .如申請專利範圍第7項所述之具有散熱構件之多 晶片封裝模組，其中該散熱構件之表面鍵金。 1 1 .如申請專利範圍第7項所述之具有散熱構件之多 晶片封裝模組，還包括複數個第三凸塊，該散熱構件藉由 該些第三凸塊與該第一晶片之該主動表面接合。 1 2.如申請專利範圍第7項所述之具有散熱構件之多 晶片封裝模組，還包括一導熱膠，該散熱構件藉由該導熱 膠與該第一晶片之該主動表面接合。
10230twf1.ptc 第19頁
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