TWI235443B - Bond pad for flip chip package - Google Patents

Bond pad for flip chip package Download PDF

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Publication number
TWI235443B
TWI235443B TW093117175A TW93117175A TWI235443B TW I235443 B TWI235443 B TW I235443B TW 093117175 A TW093117175 A TW 093117175A TW 93117175 A TW93117175 A TW 93117175A TW I235443 B TWI235443 B TW I235443B
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Taiwan
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chip
pad
patent application
groove
item
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TW093117175A
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TW200518245A (en
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Tai-Chun Huang
Chih-Hsiang Yao
Ching-Hua Hsieh
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Taiwan Semiconductor Mfg
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
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    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/13001—Core members of the bump connector
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
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    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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    • H01L2924/351—Thermal stress

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

；1235443
發明所屬之技術領域 本發明係有關於一種積體電路之封裝技術，特別係有 關於一種覆晶封裝之整合技術。 先前技術 士 覆晶封裝係超大型積體電路（VLSI)之最節省空間封 裂。覆晶技術適用於不同型式的電路版，包括陶瓷基板、 二印刷電路板、撓性電路板（f 1 ex i b 1 e c i r cu i t s )以及石夕基 底°覆晶通常係一單石（111011〇111:]11幻半導體元件，例如一 積體電路（integrated circuit, IC)，具有類似珠狀端點 V成於。亥表面之一上。該端點通常以銲錫凸塊之形式將覆 晶固定於電路板上並電性聯結該晶片電路與形成於該電 板上之導電圖案。 /在覆晶封裝中，一積體電路元件通常具有複數個呈矩 形陣列分佈之銲墊於該元件表面上。這些銲墊係用以連接 該積體電路元件與印刷電路板上（PCB)之電性路徑。球形 μ銲錫凸塊形成於積體電路元件上之每一銲墊。設置該積體 電路元件與印刷電路板以便使該銲墊與該印刷電路板上、 (PCB)之電性路徑接觸，接著加熱該裝置使銲錫回銲以於 該積體電路元件與該印刷電路板上（PCB)間形成 拖 械聯結。 /戍 e Erickson於美國專利6，18〇,26 5，中揭露將一鋁銲線轉 變成一覆晶銲錫凸塊銲墊以便使最初為銲線接合而設計 積體電路元件可以覆晶技術進行接合。
0503-10078twf(nl);tsmc2003-0291；Uofung.ptd 第4頁 1235443 <五、發明說明（2)
Chi ttipeddi et al·於美國專利β μ 、， 專利6, 087, 732中揭露一形成覆晶封裝之銲墊的；J :: 封裝步驟與半導體製造過程整合。 法以將 $積體電路元件上，目前許多已知製程之典型銲墊皆 ^鋁或以鋁為主之合金。第U圖顯示—傳統覆晶 勿剖面圖。此外，該傳統覆晶封裝之 2邛 if以提清楚圖解該覆晶封裝之結構，只有-個鮮墊 102以及一個銲錫凸塊104顯示於該圖。 斤 在操作積體電路元件中通常會產生熱而使該銲塾1〇2 與邊印刷電路板1〇6膨脹，然而由於銲墊1〇2與印 1〇6之熱膨脹係數差異極大，會造成如第lB圖所示，板 由於熱應力而變形’因此該銲錫凸塊1〇 = 離或《壞。 發明内容 有鑑於此，本發明的目在於提供一種覆晶封裝之 ，，其中該銲墊結構係用以釋放應力，特別是熱應力、，如 此可避免銲錫凸塊之剝落。 本發明特徵之一係提供溝槽於覆晶組件之銲塾中。者 此溝槽之延伸方向係大抵正交於晶片中心之放射方向（°此虽 方向即為熱膨脹方向）熱應力可被該溝槽釋放，如此可 免由於連接頂部銲錫凸塊之銲墊與連接底部銲錫凸塊之印 刷電路板之間因熱膨脹之不同而造成銲錫凸塊剝離或損
0503-10078twf(nl)；tsmc2003-0291 ;Uofung.ptd ^一"第 5 頁 ------ 1235443 五、發明說明（3) ^而5亥熱度係由操作該晶片時自銲墊中心放射產生。後 文中將說明該溝槽之不同情況實施例。 曰^，上述目的，本發明之_實施例係提供一種關於覆 ΐ^鲜墊。該銲墊用於一覆晶組件且具有複數個溝槽設 访，/、上，而此溝槽之延伸方向係大抵正交於晶片中心之 射方向，且該銲墊設置於積體電路晶片之邊角。 電踗，^本^明’該設有溝槽之銲墊大體上以設置在積體 曰曰片之邊角較佳。而且，該銲墊數可多於一個，因 大致上以陣列式排列。 八 根據本發明該銲墊呈圓形、矩形或多邊形。 t ^發明該溝槽以矩形較#，如此當在同—鲜墊之 於一時該溝槽則會相互平行…溝槽至少有 刀延伸穿過該銲墊。 ^ 1 Θ ^ Ϊ月之另一只施例係提供複數個覆晶封裝之銲墊。 戎銲墊用於覆晶裝詈中甘# ^ ρ .—復日日衣置中其设置於每四等分之積體電路晶 二：二母一銲墊至少包含一溝槽，而在同一四等分晶片之 伸方向’係大體正交於穿過此溝槽所在之四等 本發明，該溝槽呈矩形或長條型且每一溝槽至少 =至穿過部分之鲜塾’且於同-四等分晶片之溝。ί 為讓本發明之上述和苴#目 顯易懂，下文特舉出較佳二施例，、、1和俊點月b更明 細說明如下： a例並配合所附圖式，作詳
1235443 五、發明說明（4) 實施方式 本發明之較佳實施例請參考下面圖示說明。 第4圖係一傳統銲墊結構之剖面圖。該銲墊結 於-半導體基底50 0上，並形成複數層包括内層介電材^ 層（ILD)502、504於該半導體基底wo上。一下部 ’、 518插入於該層間介電層5〇2中。一上部金屬銲墊η 〇形备 於該層間介電層50 4上並由鈍態層5〇6圍繞。該上部金屬 墊51 0與下部金屬銲墊51 8以複數個插塞512電性連接’。一、 銲墊514形成於上部金屬銲墊51〇上。一銲錫凸塊— 步形成於該銲墊51 4上以用於覆晶封裝中常用之銲錫凸 回銲技術。該基底5 0 0可能包括積體電路元件，例如金氧 半電晶體、電阻、邏輯元件及其他所f，該些元件為 示清晰而被省略。下述該名詞「基底」係表示一包含元 於其中之半導體晶圓以及該晶圓上之覆蓋層。而該名詞 「基底表面」係表示包含一半導體晶圓上之頂部暴露層， 例如矽晶圓表面上之絕緣層以及金屬連線。該層間介電層 5 02、5 04可包括二氧化矽、磷矽玻璃（pSG )、硼磷矽破 璃（BPSG )以及低介電值材料，例如氟矽玻璃（FSG )。 该鈍態層506可包括氮化矽。該金屬銲墊51〇、518可包括 銅、紹或銅/铭合金。同樣地該銲墊5丨4可包括鋁或鋁基 之合金。 >在操作該積體電路元件過程中會產生大量熱能，包括 切變應力’因此銲錫凸塊以及銲墊會受切變應力的影響。 第7頁 0503-10078twf(nl);tsmc2003-0291 ;Uofung.ptd 1235443 五、發明說明（5) ^ ^上述傳統銲墊之結構可被利用，加上本發明 本：明” r案化更可減少該銲錫凸塊之切變應力。根據 於二#丄稷數個大體上正交於自積體電路晶片表面中心之 明#人t之溝槽可提供該銲墊釋放切變應力。下面係說 月付二本發明幾個銲墊排列之實施例。 第一實施例 =茶見第2a_2b圖，其中該積體電路晶片2 00係矩形基 =二^積體電路晶片20 0之中心C係由該晶片對角線之交叉 9 ^ 5亥積體電路晶片2 0 0包括複數個銲墊2 0 4，該銲墊 #具有一溝槽，且該溝槽的延伸方向係自該中心C以 二ιίϊ方向T的方式延伸或與放射方向T的角度為介於 °該銲墊204以大體上位於該積體電路晶片2〇〇 又土 5亥積體電路晶片200更包括額外的辉塾21〇， :第2B”示，其中所有的銲墊⑽以及m 1 Ϊ二Τ4ί括單一溝槽2〇2或複數個溝槽2〇2。當： π ’其以相互平行者較佳，且該銲墊2〇4可 為矩形、圓形或多邊形結構，然該溝槽2〇2以矩形較佳， 且該溝槽2 0 2延伸通過至少部分之銲墊2 〇 〇之深處。 該溝槽202可利用已知之黃光與蝕刻方法形&成。
M 之延伸方向係大抵正交於中心c之放射方向T π或/、放射方向τ的角度為介於90度卜15度，熱應 ^匕被溝槽202釋放，如此可避免由於連接頂部銲^凸^ 銲墊與連接底部銲錫凸塊之印刷電路板之間因熱 4 同而造成銲錫凸塊剝離。 … 又
0503-100781wf(η1);t smc2003-0291;Uo fung.p t d 第8頁 1235443 五、發明說明（6) 弟二實施例 請麥見第3A-3B圖，其係顯示一用於覆晶裝置中之積 體電路晶片40 0。該積體電路晶片4 0 0包括複數個銲墊、 404a、404b、404c以及404d其分別位於積體電路晶片4〇〇 之四等份區域上，其中該積體電路晶片4〇〇由四等分分割
線401等分為四等份區域。每一該銲墊4〇4a、4〇4b、4〇4c 以及404d所包括之溝槽402的延伸方向大體上正交於該積 體電路晶片400之對角線方向τ或與放射方向τ的角度為介 於90度+ -15度，其中該對角線通過積體電路晶片之四 等份區域。所有於同一四等分積體電路晶片之溝槽4〇2會 沿同一方向延伸。例如，所有的銲墊4〇4a沿一方向延伸， 而所有之銲墊404b沿另一方‘向延伸。該銲墊4〇“、4〇牡、 404c以及404d可大體上以陣列方式排列。如第^圖所示， 該銲墊404a、404b、404c以及404(1可為圓形。如第3β圖戶/ 不，該銲墊404a、404b、404c以及404d亦可為矩形。 - k其會相互平行。該溝_2延伸通過至少部分 404a、404b、404c 以及404d。 坚
該溝槽2 02可利用已知之音本版“古丨+丄 L ^ θ光與蝕刻方法形成。 當此溝槽402之延伸方向係士紅χ# 乂 τ y 1J 1糸大抵正交於晶片4 〇 〇 φ 放射方向或與放射方向的角产兔人 鬥双為介於90度+ -15声日本，妯 力可藉此被該溝槽402釋放，如 又τ …、 _ 如此可避免由於連接頂邱夺 錫凸塊之鮮墊與連接底部銲錫 、W、_ 踢凸塊之印刷電路柘夕pq 膨脹之不同而造成銲錫凸塊剝離。 路板之間因
1235443 :五、發明說明（7) 丨 雖然本發明已以數個較佳實施例揭露如上，然其並非 j用以限定本發明，任何熟習此技藝者，在不脫離本發明之 L精神和範圍内，當可作些許之更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者為準。
0503-10078twf(nl);tsmc2003-0291;Uofung.ptd 第10頁 1235443
面圖第圖係繪示出傳統覆晶封裝其熱膨脹問題之剖 -"ΓΑΓΛ係九示出根據本發明覆晶封裝之銲塾之-:; 二少有一銲塾設置在積體電路晶片之邊角之 封裴之銲墊之另一實 之一實施例之剖面 弟3 Α - 3 Β圖係緣示出本發明覆晶 施例之上視圖。 第4圖係繪示出本發明覆晶封震 圖； 符號說明 100〜 104〜 20 0〜 204〜 210〜 401〜 402〜 晶片； 1 0 2〜銲墊； 銲錫凸塊； 1 0 6〜印刷電路板； 積體電路晶片；2 0 2〜溝槽； 鲜塾； c〜積體電路晶片之中心 鲜塾； 400〜積體電路晶片； 積體電路晶片之四等分分割線； 溝槽； 404a、404b、404c、404d〜銲塾； T〜積體電路晶片之對角線方向； 500〜半導體基底； 502、504〜内層介電材料層； 506〜鈍悲層， 510〜上部金屬銲墊； 512〜插塞； 514〜銲塾；
1235443 圖式簡單說明 516〜鮮錫凸塊； 5 1 8〜下部金屬銲墊。
Jilill 0503-10078twf(nl);tsmc2003-0291;Uofung.ptd 第12頁

Claims (1)

1235443 六、申請專利範圍 1. 一種覆晶封裝之銲墊，適用於一積體電路晶片，其 中包括： 至少一溝槽，該溝槽之延伸方向係大抵正交於該積體 電路晶片中心之放射方向或與放射方向的角度為介於9 0度 + - 1 5 度。 2. 如申請專利範圍第1項所述之覆晶封裝之銲墊，其 中該銲墊大體上位於該積體電路晶片之邊角或全部表面。 3. 如申請專利範圍第1項所述之覆晶封裝之銲墊，其 中該圖案大體上以陣列方式排列。 4. 如申請專利範圍第1項所述之覆晶封裝之銲墊，其 中該銲墊呈圓形、矩形或多邊形。 5. 如申請專利範圍第1項所述之覆晶封裝之銲墊，其 中該溝槽呈矩形或長條形。 6. 如申請專利範圍第1項所述之覆晶封裝之銲墊，其 中該溝槽延伸穿過至少部分之該銲墊。 7. 如申請專利範圍第1項所述之覆晶封裝之銲墊，其 中該溝槽可向下延伸至該銲墊之底部。 8. —種覆晶封裝之銲墊，適用於一積體電路晶片，其 中包括： 複數個溝槽設於該銲墊上，每一個該溝槽之延伸方向 係大抵正交於該積體電路晶片中心之放射方向或與放射方 向的角度為介於90度+ -15度，該銲墊形成於該積體電路晶 片之角落。 9. 如申請專利範圍第8項所述之覆晶封裝之銲墊，其
0503-1007Stwf(nl);tsmc2003-0291;Uofung.ptd 第13頁 1235443
六、申請專利範圍 中該銲墊呈圓形或矩形或多邊形„ 其 1 〇 ·如申請專利範圍第8所述之覆晶封裳 中該溝槽呈矩形或長條形。 之~藝 其 n •如申請專利範圍第8項所述之覆晶封裝 中該溝槽延伸穿過至少部分之該銲墊。 、干墊 其 1 2.如申請專利範圍第8項所述之覆晶封裝 中戎溝槽可向下延伸至該銲塾之底部。 13· —種覆晶封裝之銲墊，適用於一積體電 曰 該積體電路晶片呈矩形，其中包括： 曰曰片， 複數個銲墊位於每一四等分之積體電路晶片中 每一銲墊至少包含一溝槽，而該同一四等分之該粬其中 伸方向，係大體上正交於穿過該溝槽所在之四等^㈢之延 線或與放射方向的角度為介於9〇度+一 15度。、的對角 14.如申請專利範圍第13項所述之覆晶封裝 其中該溝槽呈矩形或長條形。 、干藝， 1 5.如申請專利範圍第1 3項所述之覆晶封襄之銲 其中該溝槽延伸穿過至少部分之該銲墊。 塾’ 1 6·如申請專利範圍第1 3項所述之覆晶封裝之 其中該溝槽可向下延伸至該銲墊之底部。 藝’ 1 7·如申請專利範圍第丨3項所述之覆晶封裝之隹曰 其中該銲墊呈圓形或矩形或多邊形。 、干藝’ 18. —種半導體元件，包括： 一基底； 一導電層形成於該基底上；以及
0503-10078twf(nl);tsmc2003-0291;Uofung.ptd 第14頁 1235443 六、申請專利範圍 至少一銲墊形成於該導電層上，其中該銲墊包括至少 一溝槽，該溝槽之延伸方向係大抵正交於該積體電路晶片 中心之放射方向。 1 9.如申請專利範圍第1 8項所述之半導體元件，其中 位於四等分之積體電路晶片中之該銲墊數量多於一，而該 同一四等分之該溝槽之延伸方向，係大體上正交於穿過該 溝槽所在之四等分的對角線.或與對角線方向的角度為介於 90 度+ -15 度。 2 0.如申請專利範圍第1 8項所述之半導體元件，其中 該溝槽呈矩形或長條型。 2 1.如申請專利範圍第1 8項所述之半導體元件，其中 該溝槽延伸穿過至少部分之該銲墊。 2 2.如申請專利範圍第1 8項所述之半導體元件，其中 該溝槽可向下延伸至該銲墊之底部。
0503-10078twf(nl);tsmc2003-0291;Uofung.ptd 第15頁
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CN2731710Y (zh) 2005-10-05
US6927498B2 (en) 2005-08-09

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