TWI234289B - Schottky diode with high field breakdown and low reverse leakage current - Google Patents

Schottky diode with high field breakdown and low reverse leakage current Download PDF

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TWI234289B
TWI234289B TW093107828A TW93107828A TWI234289B TW I234289 B TWI234289 B TW I234289B TW 093107828 A TW093107828 A TW 093107828A TW 93107828 A TW93107828 A TW 93107828A TW I234289 B TWI234289 B TW I234289B
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polycrystalline silicon
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Shye-Lin Wu
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Chip Integration Tech Co Ltd
Shye-Lin Wu
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609Diodes
    • H01L29/66143Schottky diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28537Deposition of Schottky electrodes
    • HELECTRICITY
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/872Schottky diodes

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Description

1234289 五、發明說明(1) 【發明所屬之技術領域】 本發明係有關於一種蕭特基半導二極體元件,尤指一 種具有漏電流小及高場崩潰電壓的蕭特基二極體結構及製 造方法。 【先前技術】 蕭特基二極體是一種廣泛應用於功率整流元件的整流 應用,例如於電源供應器的開關、馬達控制、電信開關、 工廠自動化、電子自動化等等及許多高速電力開關應用。 雖然蕭特基二極體具有高速開關特性,然而高逆向漏電流 及低崩潰電壓大大的限制其在高逆向電壓及高溫環境下的 應用。 習知技術美國專利第3, 541,4 0 3號揭示應用p+型護環 擴散區包圍蕭特基接觸區可以增加逆向崩潰電壓。P型護 環擴散區係由硼-氮為擴散源或由硼或BF 2+離子佈植所產 生。然而,過高劑量的硼離子植入會造成表面損傷以及高 漏電流。除此之外,ρ-η接面曲率效應也會嚴重影響逆向 漏電流以及崩潰電壓(請參考S. M. S z e所著π P h y s i c s 〇 f Semiconductor Devices”第二版、第二章)。為使植入的 刪離子擴散至碎基板深處,在南溫長時間的熱處理為必須 過程。經過這樣的處理後’可以獲付較大的ρ - Π接面曲 率,以減低逆向漏電流及獲取較大的崩潰電壓。 本發明的目的之一即為提出一新方法以製造具有高崩 潰電壓、低漏電流且可高速切換之蕭特基二極體。
第8頁 1234289 五、發明說明(2) 【發明内容】 本發明揭 含以下步驟: 體基板上具有 層形成於η-蟲 層以定義護環 層之後,一多 域。隨後,進 溫退火以驅使 中。接下來, 而形成熱氧化 二光罩及餘刻 一阻障金屬( 金屬矽化程序 陽極金屬導電 域。另以金屬 露一種蕭特基二極體結構及其製造方法,包 首先,提供一 η+重摻雜半導體基板,該半^ η -成日日層I成於其上。隨後,一第一氧4 晶層上。一圖案化製程隨即圖案化第_ ^ = 區域(guard ring, GR)。在除去光阻圖 晶矽層利用LPCVD或APCVD法沈積於所有區” 行或BFA的離子佈植程序。隨後,進°°古 多晶矽層内的硼離子擴散而進入蠢曰:回 -熱氧化製程接著進行以完全氧化多:曰:“ 層,同時更驅使硼離子更深入矽基板。一二 過程隨後進行,以定義出主動區。緊接著弟 barrier metal)層沉積於主動區上並施以 。在未反應的金屬層移除後,最後再沈積一 層,再施以第三光罩並圖案化以定義陽極區 $包層則开》成於基板背面以作為陰極。 【實施方式】 本發明揭露一蕭特基二極體結構及其製造方法。請參 2圖的橫截面示意圖,顯示—半導體基板ι〇〇包含一 n + 重乜雜基板101和η-輕摻雜磊晶層1〇2。—厚約1〇〇至 2〇〇〇韻之氧化層i丨〇接著以熱氧化或CVD法形成於η_遙晶層 。一包含開口 1 1 5 Α之光阻圖案1丨5接著形成在氧化層u 〇 上以定義護環區。
1234289 五、發明說明(3) 仍請參考第2圖,一蝕刻步驟以光阻圖案π 5為罩幕接 著實施以蝕刻裸露的氧化層。隨後移除光阻圖案1丨5。 繼續請參照第3圖,一多晶矽層1 4 0厚約2 0至1 0 0 0 nm接著以 低壓氣相沈積法(low pressure chemicai vapor deposition, LPCVD)沈積於全部區域上。繼之高劑量的 B F 2 +或離子全面佈植於^ -蟲晶層上。佈植劑量與佈值能 量分別約為1Ε11至5E16/cm輿10至400KeV。 參照第4圖,接著高溫退火(therma 1 annea 1)製程進 行,以活化離子,並驅使動離子進入基板形成p+區域 1 5 0。以多晶矽層1 4 0為雜質的擴散源。 接下來’芩照第5圖,高溫氧化製程接著進行以氧化 多晶石夕層1 4 0以形成第二氧化層1 4 0 A。同時p +區1 5 0的雜質 進一步縱向及橫向擴散開來而形成護環區1 6 5。 隨後,參照第6圖,一定義主動區的光阻圖案} 6 〇接著 形成於第二氧化層140 A上。主動區的範圍包含由一終止區 (termination region) 20〇a上的部分護環與終止區另一 立而2 0 0 b的部分護環所包含的範圍間,請同時參考第9圖。 在主動區被定義後,一濕式蝕刻以光阻圖案i 6〇為罩幕接 著將所有暴露出的氧化層區域1 4 0 A、1 1 〇除去。
1234289 五、發明說明(4) 請見第7圖,在除去光阻圖案1 6 〇後,蕭特基金屬層 (Schottky barrier metal layer)緊接著覆蓋在全部區 域之上。蕭特基金屬層可選自Ti、TiN、 Ni、Cr、Pd、
Pt、W、Mo等。隨後再施以約2 0 0°c 〜85(TC退火製程以形成 金屬石夕化層170。 在氧化層140A之上未與矽反應之金屬緊接著被除去, 隨後一厚金屬層180覆蓋於全部區域之上。此金屬層再被 圖案化以形成陽極區域,最後的陽極金屬層區域將覆蓋 有主動區以及一部份在終止區的蝕刻平台。此金 A面::ί ϊ ϊ 後進行以除去在前述製程中形成於基板 ::上的各層材料’最後,再使用濺鍍一金屬層19 马陰極。 之一概略佈局示意 1 6 5或長方形護環區 弟8 Α及8 Β圖為依據本發明的方法 圖’圖示包含明複數個正方形護環區 16 5°
第11頁 1234289 五、發明說明(5) 本發明具有以下優點: 1. 在終止區之護環區1 6 5既寬且又平坦,因此,空乏 區的彎折區可預期要比傳統的元件更遠離主動區。 2. 高劑量佈植所導致的離子損傷可以忽略,這是因本 發明係藉由多晶矽層來做為雜質擴散源,這部分可以參考 作者的另一篇美國專利第5, 3 47, 1 6 1號。基於上述的好 處,可預期本發明所製造之蕭特基二極體將有高的崩潰電 壓與低的逆向漏電流。 以上所述係利用一較佳實施例詳細說明本發明,而非 限制本發明之範圍,而且熟知此類技藝人士皆能明瞭,適 當而作些微的改變及調整,仍將不失本發明之要義所在, 亦不脫離本發明之精神和範圍。
1234289 圖式簡單說明 第1 A至1 C圖顯示傳統蕭特基二極體具有p+護環結構之 製造方法之橫截面示意圖。 第2圖顯示根據本發明的方法,以光阻圖案定義護環 之橫截面示意圖。 第3圖顯示根據本發明之方法,形成一多晶矽層於所 有區域後,再施以B + 〇 r B F 2+離子佈植的橫截面示意圖。 第4圖顯示根據本發明之方法,以多晶矽層為雜質來 源,施以退火製程使雜質擴散進入η-蠢晶層以形成p+區的 橫截面示意圖。 第5圖顯示根據本發明之方法,施以熱氧化製程以形 成第二氧化層,同時使p+摻雜區擴大之橫截面示意圖。 第6圖顯示根據本發明之方法,再塗佈一第二光阻圖 案於第二氧化層上,以定義主動區之橫截面示意圖。 第7圖顯示根據本發明之方法,以第二光阻圖案為罩 幕,除去裸露的第二氧化層後,再形成蕭特基金屬矽化層 於主動區上,最後再形成一陽極金屬層,基板背面形成陰 極金屬層的橫截面示意圖。 第8 A及8 B圖顯示根據本發明之方法,元件的概要佈局 示意圖。 第9圖顯示根據本發明之方法,示蕭特基二極體橫截 面示意圖。 圖號對照說明: 10 : n+型半導體基板 2 0· π -型蠢晶層
第13頁 1234289 圖式簡單說明 20A:蠢晶層表面 2 5 ·•第一氧化層 3 0 :氧化層 3 5 :護環(p型離子摻雜區) 4 0 :光阻圖案 5 0 :陽極金屬層 1 0 0 :半導體基板 101 : n+型半導體基板 102 : η-型磊晶層 1 1 0 :第一氧化層 鲁 1 4 0 :多晶矽層 1 4 0 A :第二氧化層 1 5 0 : p +型護環區 1 6 0 :光阻圖案 - 1 6 5 : p +型護環區 1 7 0 :蕭特基金屬石夕化層 ' 180:陽極金屬層 1 9 0 :陰極 •
第14頁

Claims (1)

1234289 六、申請專利範圍 1. 一種形成半導體元件之方法,至少包含以下步驟: 提供一半導體基板,該基板含有一第一導體層及一磊 晶層,該兩層具有相同導電型雜質摻雜,且該磊晶層摻雜 濃度低於該第一導體層; 形成一第一氧化層於該磊晶層上; 形成一第一光阻圖案於該氧化層上以定義護環區域; 進行一第一蝕刻製程蝕刻該第一氧化層,以該光阻圖 案為罩幕; 除去該第一光阻圖案; 形成一多晶矽層於所有裸露的表面; 層為 形成 氧化 區; 案為 全面進行離子佈植,以佈植P型雜質於多晶矽層中; 施以一退火製程,活化該p型雜質,同時以該多晶矽 p型雜質之來源向該多晶矽層下的該磊晶層擴散,以 p型區域; 施以南溫氧化製程’用以將該多晶碎層氧化成為弟一· 層,同時使P型區域擴大而形成護環區; 形成第二光阻圖案於該第二氧化層上,以定義出主動 施以蝕刻製程,蝕刻該第二氧化層,以該第二光阻圖 罩幕; 除去該第二光阻圖案; 形成一蕭特基阻障金屬層於所有裸露的表面; 應 進行一退火製程,以使該蕭特基阻障金屬層與石夕反 因此形成一金屬石夕化物層;
第15頁 1234289 六、申請專利範圍 除去未反應之蕭特基阻障壁金屬層; 形成一頂部金屬層於裸露的表面; 圖案化該頂部金屬層以定義陽極置; 施以研磨製程,以研磨該半導體基板背面,至裸露該 第一導體層;及 形成一金屬層於該半導體基板背面以作為陰極。; 2 .如申請專利範圍第1項所述之方法,其中上述之BF 2+及/ 或·離子植入劑量與能量分別為1E11至5E16/cm2,及1 0至 400KeV。 3 .如申請專利範圍第1項所述之方法,其中上述之多晶矽 層厚度為約1 0至1 OOOnm。 4.如申請專利範圍第1項所述之方法,其中上述之退火製 程約在2 0 0至8 5 0°C下進行。 5 .如申請專利範圍第1項所述之方法,其中上述之蕭特基 阻障金屬層是選自於Ti、TiN、 Ni、Cr、Mo、Pt、Zr、W 及其組合的其中之一種,而頂部金屬層係選自T i N i及Ag或 八1或1^"八1或(:11/^1的其中之一種的堆疊層構成。 6 .如申請專利範圍第1項所述之方法,其中上述之第二光 阻圖案覆蓋住部分該護環區域,所以該主動區位在兩個護
第16頁 1234289 六、申請專利範圍 環間並且包含部分的護環。 7. —種半導體功率整流元件,至少包含以下部分: 一半導體基板,包含一第一導電層及一磊晶層形成於 其上,其中該第一導電層及該磊晶層摻雜有第一型導電性 雜質,且該磊晶層摻雜濃度較低; 一陰極金屬層形成於該第一導電層背面上; 四個護環線狀排列於該磊晶層内,且摻雜有第二型導 電型雜質,其中,最外側之兩個護環部分被一氧化層覆 蓋,並作為終止區;及 一蕭特基矽化層該磊晶層上,且位於分開的該氧化層 之間。 一陽極金屬層形成於該蕭特基矽化層上並延伸以覆蓋 該氧化層上。 8. 如申請專利範圍第7項所述之半導體功率整流元件,其 中該護環區由兩種第二型導電型雜質以隻擴散所形成。 9. 如申請專利範圍第7項所述之半導體功率整流元件,其 中該蕭特基石夕化層係選自Ti、TiN、Ni、Cr、Μο、Ρΐ、Zr 及W其中一種與矽反應產生之金屬矽化層構成,而其中該 陽極金屬層係由Ti/Ni及Ag或A1或TiN/Al或Cu/Al的其中之 一種的堆疊層構成。
第17頁
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