TWI226709B - Two mask Schottky barrier diode with LOCOS structure - Google Patents

Abstract

A power Schottky rectifier device and method of making the same are disclosed. The Schottky rectifier device including a LOCOS structure and two p doped regions, which are positioned one above another therein to isolate cells so as to avoid premature of breakdown. The Schottky rectifier device comprises: an n- drift layer formed on an n+ substrate; a cathode metal layer formed on a surface of the n+ substrate opposite the n- drift layer; a pair of field oxide regions and termination region formed into the n- drift layer and each is spaced from each other by the mesas, where the mesas have metal silicide layer formed thereon. A top metal layer formed on the field oxide regions and termination region and contact with the silicide layer. Under each of field oxide regions and termination region is a p doped and p- doped region cascade which provide depleted regions enclosed the p- doped regions to block the leakage current while a reverse bias voltage is exerted to the Schottky power rectifier diode.

Description

1226709 V. Description of the invention α) The technical field to which the invention belongs: The present invention relates to semiconductor processes, in particular to a Schottky barrier diode structure including a region oxide layer therein to simplify the production process, and Reduces leakage current under high reverse bias conditions. Prior technology: Schottky two-pole system is an important power component, widely used in power supply switches, motor control, telecommunication switches, factory automation, electronic automation, and many other high-speed power switching applications. These power components typically require the ability to carry a significant amount of forward current, and they can block at least 100 volts or more when reverse biased, and have low leakage current. There are many disclosed power components that can achieve the above-mentioned characteristics of high load current and high reverse bias resistance. An example of a typical Schottky diode can be found in U.S. Patent No. 6,648,316, 4 obtained by Kanemaru et al. The manufacturing process is shown in Figures 1A to 1C. Referring to FIG. 1A, a semiconductor substrate 10 heavily doped with n-type conductive impurities is first prepared, and a drift layer (dr i f t 1 a y e r) 20 is formed thereon and extends to the first surface 20A. Subsequently, an oxide layer 25 is formed on the first surface 20 A. After that, please refer to FIG. 1B to pattern the oxide layer to define the position of the guard ring 35 in the termination region. Subsequently, the guard ring zone 3 5 is then doped with an ion implantation or diffusion technique and mixed with a P-type conductive impurity.

Page 6 1226709 V. Description of the invention (2) The mass is formed in the drift layer 20. Next, a thermal oxidation process is applied to diffuse P-type conductive impurities such as boron inward, and at the same time, an oxide layer 30 is grown and the oxide layer is thickened. A second photoresist pattern 40 is then applied on the surface of the above result to define the anode contact area. I The worm engrave part was removed in the previous worm engrave followed by a gold traditional cover to become Xiao Ming's. Please refer to the figure to follow the steps to describe the result of the photoresist pattern on the guard ring. Basic energy is complete. The Teck rectification method is only 1C, which is beneficial, and it is performed on the surface after the zones 35 and 40. In the foregoing steps, the rectifier element of the present invention requires a dual-use second to remove the exposure and the guard ring. Later, it is used to determine the special base resistance of the oxygen I region 3 5 which can be used for the purpose of protecting the substrate and can be changed to the photoresist pattern of the photomask. Use good collapse. Case 40 is used as a curtain, and a wet layer 30 and 25. In this way, the drift layer 20 in between is exposed. At the barrier metal layer 50, three photoresist patterns (not shown) and a base barrier metal layer 50 pattern are formed. Several layers of material layers, and then the process of forming 〇 requires at least three light. Simplified process steps to achieve the purpose of forming voltage. Summary of the Invention According to the present invention: The present invention discloses a Schottky rectifier element (S c h 〇 11 k y r e c t i f r e de r v e c e) and a manufacturing method thereof. The Tiki rectifier element includes a plurality of regional oxide layers in it to avoid premature collapse and serve as the buffering stress of the wire. Wherein, the Schottky rectifier element includes at least an n-type drift layer formed on the n + semiconductor substrate. Η- here

Page 7 1226709 V. Description of the invention (3) refers to lightly doped n-type conductive impurities, and n + refers to heavily doped conductive impurities. A cathode metal layer is formed on the back of the n + semiconductor substrate and is opposed to the n-type drift layer. A pair of field oxidation regions and termination regions are formed in the n-type drift layer. There is a platform separation between the field oxidation area and the field oxidation area, and between the termination area and the field oxidation area. The platform has a metal silicide barrier layer formed thereon as an anode contact, and a patterned top metal layer. The anode is formed on the metal silicide layer and the field oxide region oxide layer, and extends to cover a part of the stop region oxide layer. In addition, there are P-doped and ρ-doped regions under the oxide layer in the field oxidation region and the termination region. Therefore, when the device is reverse biased, the leakage current can be suppressed. Embodiments: As described in the prior art, the conventional manufacturing technology of power transistor rectifier elements including a termination structure requires at least three photomask processes. However, the present invention can simplify the manufacturing process, in particular, only two photomasks are needed. The manufacturing method will be described in detail below. In the following description, the "-" sign following η or ρ indicates light doping, and "+" indicates heavy doping. Please refer to the schematic cross-sectional view of FIG. 2. First, an n-type impurity heavily doped η + semiconductor substrate 1 0 0 and an n-type impurity-doped n-stupid crystal layer 105 are also provided as a drift layer (dr i ft layer) is formed thereon. An oxide layer 1 1 0 having a thickness of about 5-50 nm is then formed thereon.

Page 1226709 V. Description of the invention (4) After that, the ion implantation is applied comprehensively, and n-type ions are implanted to form an n-type layer 1 1 5 under the oxide layer 1 1-stupid crystal layer 1 〇5。 Within 0. When the η-type impurity is an ion, the implanted energy and dose are 10 to 2000 k e V and 0 to 5 X 1 0 13 / cm2, respectively. Therefore, the impurity concentration in the η-type layer 1 15 is higher than that in the η-stupid crystal layer 1 05, but the concentration is still lower than the η + semiconductor substrate 100. To define the active area, please refer to FIG. 3. A nitride layer 120 is then formed on the oxide layer 110. A photoresist pattern 125 is then formed on the nitride layer i20 to define an active area. Subsequently, using the photoresist pattern i 25 as a mask, an etching technique #etched into the nitride layer 1 2 0 and the oxide layer 1 1 0. Still referring to FIG. 3, a dual ion implantation is performed next to implant b and BF ^ n-worm crystal layers 105 at different depths to form a p-doped region 13 and a p-doped region 135, respectively. When boron ions are implanted, the energy is implanted. To mkem5x 10n to 5x 1014 / cm2. And the planting ^ =; don't worry, the energy and dose of the planting are 30 to 2000k 2 1015 / cm2, respectively. ^ D X 10 ^ 5x after ion implantation

^ ^ ~ • 一一 彔 1IZ 彔 接 接手 stripping 0 Sara Park

It is known that the thermal oxidation process ′ uses the nitrogen cutting layer 12G as a mask, and f ^ ′ does not. When performing the thermal oxidation process, as shown in the figure ... 〃 As shown in Figure 4, 140 is formed on the active 1 and has a thick stop zone oxidation / zone oxidation panel. In addition, the impurities formed in p,: ^ and the basic type will diffuse to p and Γ and Λ 1: 5 due to annealing.

1226709 V. Description of the invention (5) Into the η-stupid crystal layer 105, the relevant area is enlarged. In a preferred embodiment, for a field oxide layer having a thickness of about 0.1 to 2 // m and a p-130 / n 105 junction, the depth D1 from the surface of the platform 150A is about 0.1 to 5 / In terms of m / m, the plateau region 150 A between the field oxide region oxide layer 140 and the plateau width between the field oxide region and the stop region oxide layer is about 3 〇β m 〇 Please refer to the figure 5. First remove the nitride layer 1 2 0 and the pad oxide layer 1 1 0, and then the refractory element type Schottky metal barrier layer 1 50 is deposited on the substrate.

The front side of the board. The refractory metal layer 15 may be selected from π, Ni, Cr, Mo,

Pt, Zr, W and so on. After the refractory metal layer 150 has been transformed into a metal silicide layer 150, the gold 1 on the field oxide region oxide layer 140 and the termination region oxide layer 140 a is sequentially removed by wet etching. Subsequently, an anode metal layer 160 is deposited again on the Schottky metal silicide layer on the field oxide region oxide layer ^ 4 and the termination region oxide layer 140A. The anode metal layer 160 may be selected from T ^ i / Ag or

TiW / A. Here Ti and Ni or Ti and W are deposited together. The lithography ^ and etching techniques were used to pattern the anode metal layer to define the extended length of the oxide layer in the termination region "140A. Finally, a number of deposited layers on the back of the substrate were removed by chemical mechanical polishing ^ 1 to the substrate1. 〇 Back soundtrack,

The preset thickness. After that, a metal layer is fully deposited as the cathode. 6 / A, FIG. 6A shows a schematic diagram of the layout of a-stand® ^ m according to the method of the present invention. The number of oxide layers in the field oxidation area shown in the figure is

1226709 V. Description of the invention (6) Seen in the schematic cross-section. In addition to the dot patterns shown in the figure, the oxide layers in the field oxidation area can also have a long stripe distribution. Please refer to Figure 6B. According to the present invention, only two photomasks are needed to achieve a high-performance Schottky barrier diode structure-one of the photomasks is used to define an active area, and the other photomask is used to define an anode metal layer. The field oxide region oxidation layer 1 40 interspersed in the active region can also be used as a buffer layer, especially when a wire (w i r e b ο n d i n g) is applied to the oxygen electrode, providing a stress relaxation function. FIG. 7 and FIG. 8 respectively show the forward current and the empty region when the Schottky barrier diode element is subjected to forward bias and reverse bias operation. In circle 7, the anode 160 is positive relative to the cathode, and most of the forward current flows through the plateau region 150 A, which is the Schottky contact of the metal silicide. Only a very small amount of current flows along the boundary of the oxide layer in the field oxidation zone. This is because the turn-on voltage of the Schottky contact is lower than the p-n junction, and the resistance of the metal silicide is much lower than that of the oxide layer in the field oxidation region. When the Schottky diode is reverse-biased, the vacant region 190 starts to form and surrounds the P-region 130 and the p-region 135. The vacant region increases with the reverse bias of the electrode, and with the field The thickness of the oxide layer in the oxidized region increases the breakdown voltage, and the coating of the empty region can reduce the leakage current. According to the method of the present invention, the present invention can achieve at least the following advantages. (1). The manufacturing method of the present invention is simpler than the traditional method because only two

1226709 V. Description of the invention (7) * One mask is used to define the active area and the other is used to define the anode metal layer. : (2) The field oxide region oxide layer is located in the active region, which can provide a buffer layer that should be relaxed when wiring. In addition, the field oxide region oxide layer 1 40 can also increase the collapse voltage. (3) The oxide layer 140 A in the termination region is wide and flat. Therefore, the bending region of the empty region can be expected to be farther away from the active region than the conventional element. (4). The forward current is almost composed of the main carrier, so the switching speed of the element is superior to the conventional one. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention. Any other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application.

Page 1212709 Brief description of the preferred embodiment of the present invention will be described in more detail in the following explanatory text with the following figures: Figures 1A to 1C show the termination of a traditional Schottky diode The cross-section of the title page of the manufacturing method for forming the guard ring structure in the zone is not intended. FIG. 2 shows that an oxide layer is formed on an η-stupid layer according to the method of the present invention. The cross-section of the η + semiconductor substrate under the stupid layer is not intended. FIG. 3 shows a schematic cross-sectional view of a method of forming a nitrided layer mask on an oxide layer according to the method of the present invention, and then applying double-layered (dua 1 im ρ 1 ant) technology to the n-stupid crystal layer. According to the method of the present invention, a thermal oxidation process is applied to form a region oxide layer structure and a termination region, and a schematic cross-sectional view of expanding the double P # hetero region. Figure 5 shows a method according to the present invention, in which a metal silicide is formed on a platform. And patterning to form an anode on the front surface of the substrate, and in addition, a cross-sectional schematic diagram of the cathode is also formed on the surface of the back surface of the substrate. Figure 6A and Figure 6B show the schematic layout of the method according to the present invention, which shows the formation of a region oxide layer In the active area and the termination area, and only two photomasks can be used in the process. Figure 7 shows the forward current distribution when a forward bias is applied to the Schottky diode. Figure 8 shows the reverse bias Schematic diagram of empty distinction when applied to Schottky diodes.

Page 13 1226709 Brief description of the drawings 1 0 Semiconductor substrate 20 Drift layer 2 0 A Stupid layer (drift layer) surface 25 Oxide layer 3 5 Guard ring (p-type ion doped region) 40 Photoresist pattern 3 0 Oxide layer 50 Anode metal layer 6 0 Cathode metal layer 100 Semiconductor substrate 1 0 5 Drift layer 115 η doped layer 1 2 0 Silicon nitride layer 125 Photoresist pattern 1 3 0 p doped layer 135 ρ-doped layer 1 4 0 field oxidation Area oxide layer 140A Termination area oxide layer 150A Worm crystal layer (platform) surface 150 Schottky metal barrier layer 1 6 0 Anode metal layer 170 Cathode layer _

Page 14

Claims (1)

1226709 VI. Scope of patent application1. A method for forming a trench metal-oxide semiconductor transistor. The method includes at least the following steps: A first conductive semiconductor substrate is provided with an epitaxial layer doped with the first conductive impurity. Formed on it; forming a first oxide layer on the remote crystal layer; forming a first decay layer on the first oxide layer; patterning the first nitride layer and the first oxide layer to define Active zone The end of the zone and the first layer of oxygen ionization, the first type of electricity and the conductive layer type of dinitrogen, the first doped dopant is mixed into a case diagram, the plant is clothed, and the subarea is doped with the doped layer. The main part of the doped mask area should be re-formed in the area of the oxygen field to process the oxygen heat to apply the spar. The exposed surface is exposed, and the half of the oxygen conductivity of the plate substrate should be equal to •, In the metallized gold zone, the barriers stop first, the division and the shifting of the inner special depression are performed by the layer of gold barriers, and the steps are reduced. Second, the metallization layer is formed by the product of silicon barriers. Shen; The first step is described directly above; because the plate is based on the first half of the body number, the upper half of the body is faced with the layer, the layered plate is behind the layer, the gold fund department, the body is guided, the half is reduced, and the case is completed. Removal of the figure is to use the surface of the backplane to guide the half of the surface. It should be layered on the gold surface and a layer of material. Material pole page 15 1226709 6. Application for patent scope 2. The method of applying for patent scope item 1 further includes forming a second doped layer by ion implantation before patterning the nitride layer and the first oxide layer. Under the first oxide layer. 3. The method according to item 2 of the patent application, wherein the impurity concentration of the second doped layer is higher than that of the epitaxial layer, but lower than that of the semiconductor substrate. 4. The method according to item 1 of the patent application, wherein the first doped layer is implanted with boron ions and BF 2 + ions at different depths to form a P-doped layer and a P-doped layer, respectively. After the thermal oxidation process step is performed, and the impurity concentration of the P-doped layer is high, and the impurity concentration is on the P-doped layer. 5. The method according to item 4 of the patent application, wherein the boron ions are implanted at a dose of 5 parent 1011 to 5 \ 1014 / 〇111 and an energy of 10 to 2 0 1 ^ ¥. 6. The method according to item 4 of the patent application range, wherein the above B F 2 ions are implanted at a dose of 5x 10 12 to 5x 10 14 / cm 妁 and an energy of 30 to 2000 keV. 7. The method according to item 4 of the patent application, and after the thermal oxidation process, the thickness of the oxide layer in the field oxidation region is about 0.1 to 2 // m, and the p-doped layer / epitaxial layer interface The depth of the epitaxial layer is about 0.1 to 5 // m, and the interval between the field oxidation regions is about 1 to 30 // m. Page 16 1226709 VI. Application for Patent Scope 8 · The method of applying for the first item of patent scope, wherein the above barrier metal layer is selected from the group consisting of Ti, Ni, Cr, Mo, Pt, Zr, and W One and its combination. 9. The method of claim 1 in which the above-mentioned top metal layer is selected from one of TiNi / Ag or TiW / Al. 10. The method according to item 1 of the scope of patent application, wherein the patterning of the top metal layer to define the anode step at least includes defining an extension of the top metal layer in the termination region. 11. A power rectifying element, at least comprising: an n-drift layer formed on an n + semiconductor substrate; a cathode metal layer formed on the back of the n + semiconductor substrate, opposite to the n-drift layer; a pair of field oxide region oxide layers A first platform is separated from each other and is formed on the η-drift layer. A pair of stop region oxide layers are located outside the pair of field oxide regions and separated by a second platform. A P-type doped region is formed in the field oxide region An oxide layer and below the termination layer oxide layer; a Schottky barrier silicide layer is formed on the first platform and the second platform; and Page 17 1226709 VI. Scope of patent application A top metal layer is formed as an anode on the Schottky barrier silicide layer, the field oxide region oxide layer, and extends to cover a portion of the termination region oxide layer. 1 2. As for the element in the scope of claim 11 of the patent application, it further comprises an n-doped region under the Schottky barrier silicide layer, and the impurity concentration in the n-doped layer is lower than that of the epitaxial layer south. On the semiconductor substrate. 13. The element according to item 11 of the scope of patent application, further comprising a P-doped region formed under the p-doped region. 14. The element according to item 11 of the scope of patent application, wherein the thickness of the oxide layer in the field oxidation region is about 0.1 to 2 // m and the depth of the ρ- / stupid crystal layer junction is determined by the Lei The amount of crystal layer surface is about 0.1 to 5 // m, and the distance from the field oxidation region is about 1 to 30 / zm. 15. The element according to item 11 of the scope of patent application, wherein the barrier metal layer is selected from one or a combination of a group consisting of Ti, Ni, Cr, Mo, Pt, Zr, and W. 16. The element according to item 11 of the patent application range, wherein the top metal layer is selected from one of TiNi / Ag or TiW / Al.