TWI233678B - Semiconductor device with improved heatsink structure - Google Patents

Semiconductor device with improved heatsink structure Download PDF

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TWI233678B
TWI233678B TW092129051A TW92129051A TWI233678B TW I233678 B TWI233678 B TW I233678B TW 092129051 A TW092129051 A TW 092129051A TW 92129051 A TW92129051 A TW 92129051A TW I233678 B TWI233678 B TW I233678B
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substrate
heat sink
semiconductor device
patent application
semiconductor wafer
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TW092129051A
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TW200411872A (en
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Naoto Kimura
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Nec Electronics Corp
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Description

1233678
一、 【發明所屬之技術領域】 尤其是關於一 本發明係關於一種封裝式半導體裝置， 種封裝式半導體裝置之散熱構造。 二、 【先前技術】 從丰㈣’封裝式半導體裝置通常採用可同時 攸+ ¥體曰曰片的主要表面及背面散熱的散熱結構。 抓用此種散熱結構的封裝式半導體裝置已在曰本專利 公=報第P20 0 2- 1 64485A號中揭露出來。圖1顯示該揭露 之丰，體裝置的結肖。該揭露之半導體裝置係由具高導熱 ^之虱=鋁製之第一及第二絕緣基板1〇2及1〇4所組成，而 第及第一政熱體1 0 3及1 〇 5便分別連接至該第一及第二絕 緣基板102及1〇4。此種散熱結構可讓熱力從半導體晶片 ιοί的主要表面透過該第一絕緣基板102及該散熱體1〇3而 散發’同時亦可使熱力由該半導體晶片丨的背面透過該 第二絕緣基板104及該散熱體105而散發出去。該半導體晶 片1 0 1與外界之電性連接係透過位於絕緣基板丨〇 2、連接至 该互連線之導體106、接合線1〇7及端子108等上面之互連 線來達成。
另一種可由半導體晶片之主要表面及背面散熱之散熱 結構已在日本專利公開公報第JP —A —Heisei 7-29940， JP-A-Heisei 8-64730 以及P2000-174180A 中揭露。 若半導體裝置封裝可改善散熱效率將會非常有利。 若半導體封裝用之互連線的長度可以降低亦會非常有 利。縮短之半導體裝置封裝用之互連線長度可有效降低信
1233678 五、發明說明（2) 號的延遲， 三、【發明 總體而 構的改良。 詳細說 裝之散熱效 本發明 體晶片與外 在本發 基板、一連 於該第一散 基板之主要 片之一背面 當該半 第一墊片， 片以便與該 第一互連線 含一第二互 放熱板包含 點的話，將 該第一 間的主體部 形成一邊緣 在此例 且可避免高頻信號之阻抗失配。 内容】 言，本發明係著墨於半導體裝置封裝之散熱結 來，本發明之一目的係為了改善半導體裝置封 率0 之另一目的係為了降低半導體裝置封裝之半導 界電性連接之互連線的長度。 Ϊ ί : Ϊ施態樣中，一半導體裝置係由-第- ίΓ::基板之第一散熱板、其-背面連接 ;基板、一具有一表面連接於該第二 0;第：、ί體晶片，以及一連接至該半導體晶 的第一政熱板等所組成。 :ί 2 ί含一連接至該第一基板之-背面的 半導姊曰Η至邊第二基板之主要表面的第二墊 ίϊ::電性連接時’若該第-基板包含- 牙越其中而連接 第一墊片，而第二墊片包 中而連接至該第二藝片，且該第- 較為有弟一及第二互連線電性連接之通孔接 ==包含-位於該第1第二基板之 。該側面部，以在其間 軚好疋垂直於該主體部。 …散熱板較好是包含—連接至該側面 五、發明說明（3) 部之ΐ部：該上部較好是垂直於該側面部— ^省"一放熱板係連接至該上部將 、若該第一及第二散熱板係互相為有利。 半導體晶片之封閉體將較為有利。 %成一環繞於該 、在本發明之另一實施態樣中，一半導 法包含下列步驟： 體竣置之製造方 將一第一散熱板之一背面連接至一 第 將一第二基板之一背 將一半導體晶片倒裝 面；
將一第二散熱板連接 更包含下歹，J 一散 體部 本方法若 熱板以便 係位於該 在此例中 折疊該第 上部，將 該上部較 在該第一散 第一及第二 ’若本方法 一散熱板以 更為有利。 好是折疊狀 該第一及第二散熱板 一封閉體 【實施方 本發明之 基板之一主要 面連接至該第-散熱板之—主要 晶片接合至該第二基板之主要表 ^該半導體晶片之一背面。 y驟，亦即在一邊緣 ，中形成主體 基板之間，將更為有利。。亥主 更包含下列步驟’亦即在另一 形成連接#莖 ^ 接垓第一散熱板内之側面 二以便與該第二散熱板耦合。 較好疋形成一環繞於該半導體曰 式】 較佳實施例 將參照相關圖示來做更詳盡 的說 1233678 五、發明說明（4) 明。 圖2顯示一沿著圖3之A - A方向所取之本實施例之半導 體裝置之橫剖面圖。本實施例之半導體裝置包含一下基板 1、一内部散熱板4、一中間基板11以及一半導體晶片1 4。 該下基板1係由内部互連線2所穿過之玻璃環氧樹脂基 板所組成。該内部互連線2包含電源供應線、接地線以及 信號線等。該内部互連線2係用來當作連接該下基板1之主 要表面la及其背面lb的橋樑。 金屬墊片3及銲球1 9均連接至該下基板1。該墊片3位 於下基板之背面1 b上以與該内部互連線2連接。該墊片3並 排列成行列狀。而該銲球丨9則分別連接到該墊片3。
^該中間基板11係由内部互連線1 2所穿過之玻璃環氧才 脂基=所組成。該内部互連線丨2包含電源供應線、接地矣 以及信號線等。該内部互連線丨2係用來當作連接該中間^ 板11之主要表面lla及其背面Ub的橋樑。 - 1墊片13係位於該中間基板11之主要表面1 la上。 β玄墊^13並連接到該内部互連線12。 間H部散_熱板4係位於該下基板1及該中間基板11之
的+ $ # h所不該内部散熱板4係由於邊緣9和1 0上折疊 形銅，所製成。，亥内部散熱板4 之間。側面部7則：：體部4C係位於下基板1及中間基板1 之側面部7，該内二=體部4 c ’而上部8則垂直於相, 政”、、板4為折疊式以便該上部8與該主 1233678
體部4 C互相平私 卜 互相垂直，> 。母一側面部均有其邊緣與該邊緣9及1 0 時係與相鄰：側：7之垂直邊緣當該内部散熱板4折疊 一對傾斜邊緣 °之垂直邊緣相接。每一上部8均具有 立以之傾斜、喜與連之邊緣1〇成45度角相接。該每一上 之開口。板折豐後具有一盒狀結構並具有一向上 、杳# πτ Ϊ H不，5亥内部散熱板4具有複數個通孔接點2 0以 達成下基板1之内部互連線2以及中間基板丨丨之内部互連線 12之電性連接。如圖3C所示，每一通孔接點2〇均包含一絕 緣體5以及一圓柱導體6。該通孔接點2〇係透過下列製造過 程所形成。在該通孔接點2 〇穿透該内部散熱板4而形成之 後，該通孔接點20便被包覆著該絕緣體5。該圓柱導體6便 貫穿該絕緣體5而形成。該導體6通常以金製成。 該内部散熱板4之背面4b係以黏著的方式耦合於該下 基板1之主要表面1 a。使其黏著劑變硬將在主要表面丨a及 背面4b間產生一收縮力，因而達成該導體6.及該内部互連 線2之間的電性連接。 相同地’該中間基板11之背面11 b係以黏著的方式搞 合於該内部散熱板4之主要表面4 a。使該黏著劑變硬將達 成該導體6及該内部互連線1 2的電性連接。結果，該墊片3 及1 3便 < 透過該通孔接點2 〇而電性連接。 回到圖2，該半導體晶片1 4係倒裝晶片接合至該中間 基板11之主要表面1丨8上°該半導體晶片14之主要表面14a
第11頁 1233678
设^數個凸塊15，且該半導體晶片14係以面朝下的方式 而，、連接墊片13的凸塊15相接。如此則造成半導體晶片 的主要表面14a與該中間基板u的主要表面⑴相對。 ‘體:片1 4與中間基板丨丨之間的空間係填以下部填充樹脂 1 6。該内部散熱板4中的半導體晶片丨4周圍的空間則 了樹脂1 7。 該半導體晶片14的背面14b係連接至一銅板製的外部 散熱板1 8。該外部散熱板丨8可以焊劑或導電黏著劑固定於
該半導體晶片14。該外部散熱板18係連接於該内部散熱板 4之上部8的上表面8a。 由内部散熱板4及外部散熱板丨8所組成之散熱結構在 半導體晶片1 4及該中間基板丨丨周圍形成一封閉體，並因此 而提供一個高效率的電磁遮罩。除此之外，該外部散熱板 1 8及該上部8的連接透過增加該散熱結構的厚度而有效地 提升了散熱效率。 圖4 A到4 D以及5 A到5 C說明了本實施例之半導體裝置之 製造方法。 ~
如圖4A所示，該製造程序首先將墊片3裝設在下基板j 之背面1 b上，如此該墊片3便連接至該下基板1中之内部互 連線2。 如圖4B所示，該内部散熱板4之背面4b係以黏著劑連 接至5玄下基板1之主要表面1 a ’以達成該内部互連線2及該 通孔接點2 0中之導體6之間的電性連接。 在將墊片3形成於該中間基板1 1的主要表面11 a之後，
第12頁 1233678 五、發明說明（7) 如圖4 C所示，該中pj | 4cr 1 1 > 接至該内部散孰板4便透過黏著劑而連 中門其私M加…反 要表面4a，達成了該導體6以及該 中曰土板内之内部互連線1 2之間的電性連接。 如圖4D所示，該位於半導體晶片14之主要表面14a上 =凸塊15係連接至塾片13以達成倒裝晶片接合。該半 晶片1 4係以面朝下的方式裝設在該中間基面 11…如此該半導體晶片14之主要表面14a便盘； 面1 la相對。 /、β王要表 在倒裝晶片接合之後，該半導體晶片14與該中間美 11間的空間係填以下部填充樹脂i 6。 土 如圖5Α所示，於邊緣9及10上折疊該内部散熱板4以 疋該側面部7以及該上部8。 在折豐該内部散熱板4之後，該内部散熱板4内的空 則填以樹脂1 7。 1 如圖5Β所示’該外部散熱板1 8係以焊劑或導電性黏 劑連接至該半導體晶片1 4之背面丨4 b以及該上部8。 如圖5C所示，該銲球19係連接至該墊片3 成 施例之半導體裝£。 兀砥本Λ
上面描述之散熱結構可有效地改善散熱效率。如圖6 所示’其中散熱的路徑係以箭號來說明，位於下基板1以 及中間基板11之間的内部散熱板4可使得熱氣透過側面部7 及上部8而從該半導體晶片14的主要表面14a中散出。且， 該外部散熱板1 8可使得該半導體晶片丨4中產生之熱氣直接 由背面1 4b散發至外界。本實施例之散熱結構的特色是可
第13頁 1233678 五、發明說明（8) _
改善散熱效率。除此之外，該外部I 板4之上部8之間的連接降低了該散埶= ^该内部散熱 ^狀熱結構的執阳> 加了散熱的區域。這也可提升散熱的效率。^ ^，並增 散^率可使得該Ρ板1以及該中間基板Η擁有所善♦後^ 之夕層結構，但之如卻常苦於不良的散熱效率。斤南要 本實施例之散熱結構的另一優點就是該内 熱板4及1 8在該半導體晶片1 4及該中門其 ° 外部散 ^ ^ r間基板11的周in妲vu 了一電磁遮罩。如此可有效降低來 &供 干擾（EMI)。 /千导體凌置的電磁 本實施例之散熱結構的再另一傷 該封裝之半導體裝置不需連接電、線憂而=J ：構可使 封裝半導體裝置内之互連線的長产。 /有效減少該 可有效地降低訊號的延遲，1可二4 ^連線的長度 配。 殊·τ促成命頻信號之阻抗失 本發明之較佳實施例均揭露於此，雖然在此使用 特疋的形式，自此等形式僅用來解釋說明之用，並非：; :用。^㉟習本項技藝者應瞭解，在」 些實施例中是可以變化的，其範圍; 界疋於申睛專利犯圍以及其等效設計内。 兮由：：f§兄’热習該項技藝者可以領會該下基板1及/或 该：間基板U可以陶竞板、樹脂磁帶板、石夕板、】 金屬板所組成。 且，熟習該項技藝者亦可領會該内部及外部散熱板4 及1 8亦可以合金板或鐵板等組成來替代銅板。 1233678 圖式簡單說明 五、【圖式簡單說明】 圖1顯示一剖面圖 圖2顯示一剖面圖 導體裝置。 圖3A顯示一透視圖 說明一習知之半導體裝置封裝。 說明根據本發明之一實施例的半 說明該半導體裝置。 圖3 B顯示該半導體裝置之内部散熱板的發展。 圖3 C顯示一平面圖，說明貫穿該内部散熱板之通孔接 圖4A〜4D顯示四個平面圖，說明在該内部散熱板彎曲 前之半導體裝置之製造方法的步驟。 圖5A〜5C顯示三個平面圖，說明在該内部散熱板彎曲 後的半導體裝置之製造方法的步驟。 圖6顯示該半導體裝置之散熱機制。 元件符號說明 1 下 基 板 10 邊 緣 101 半 導 體 晶 片 102 絕 緣 基 板 103 第 一 散 孰 體 104 第 二 絕 緣 基板 105 第 二 散 熱 體 106 導 體 107 接 合 線
4P
第15頁 1233678 圖式簡單說明 108 端子 · 11 中間基板 1 la 中間基板11之主要表面 lib 中間基板11之背面 12 内部互連線 、 13 墊片 14 半導體晶片 14a 半導體晶片14之主要表面 14b 半導體晶片14之背面 15凸塊 0 16 下部填充樹脂 17 樹脂 18 外部散熱板 19 辉球 la 下基板1之主要表面 lb 下基板1之背面 2 内部亙連線 2 0 通孔接點 3 墊片 p 4 内部散熱板 4 3 内部散熱板4之主要表面 4 b 内部散熱板4之背面 4c 主體部 5 絕緣體
第16頁 1233678 圖式簡單說明 6 導體 7 側面部 8 内部散熱板4之上部 8a 内部散熱板4之上部8的上表面 9 邊緣 (Ψ
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第17頁

Claims (1)

1233678 六、申請專利範圍 1. 一種半導體裝置，包含： a) . —第一基板； b) . —第一散熱板，連接至該第一基板； c) · 一第二基板，具有主要表面及背面，該第二基板 之背面係連接至該第一散熱板； d) · —半導體晶片，具有一主要表面連接至該第二基 板的主要表面；以及 導體晶片之一背面。 體裝置，其中更包 e) · —第二散熱板，連接至該半 2 ·如申請專利範圍第1項之半導 含： 基板之一背面； 基板之主要表面，以 a). 一第一墊片，耦合至該第 b). 一第二墊片，耦合至該第二 電性連接至該半導體晶片， 其中，該第一基板包含一貫穿其中之第一互連線以連 接至該第一墊片， 其中，該第二基板包含一貫穿其中之第二互連線以連 接至該第二塾片，且， 其中’該第一散熱板包含一通孔接點，以提供該第一 及第二互連線間之電性連接。 3.如申請專利範圍第1項之半導體裝置，其中該第一 散熱板包含： a) . 一主體部，位於該第一基板及該第二基板間； b) . 一側面部，連接至該主體部，以在其間形成一邊 緣。
第18頁 1233678 六、申請專利範圍 4 ·如申請專利範圍第3項之半導體裝置 部係垂直於該主體部。 5. 如申請專利範圍第3項之半導體裝置 散熱板更包含一連接至該側面部的上部。 6. 如申請專利範圍第5項之半導體裝置 係垂直於該側面部。 7. 如申請專利範圍第5項之半導體裝置 散熱板係連接至該上部。 8. 如申請專利範圍第2項之半導體裝置 其中該側面 其中該第一 其中該上部 其中該第 其中該第一 散熱板係互相連接以在該半導體晶片周圍形成一封 閉體 9. 一種半導體裝置之製造方法，其步驟包含·· a) · 將一第一散熱板之一背面麵合至一第一基板之一 主要表面； b) · 將一第二基板之一背面耦合至該第一散熱板之一 主要表面； c ).將一半導體晶片倒裝晶片接合至該第二基板之該 主要表面上； d) ·將一第二散熱板耦合至該半導體晶片之一背面。 10. 如申請專利範圍第9項之半導體裝置之製造方 法，其步驟更包含將在一邊緣上折疊該第一散熱板以在該 第一散熱板中形成主體部及側面部，該主體部係位於該第 一基板及第二基板之間。 11. 如申請專利範圍第10項之半導體裝置之製造方
第19頁 1233678 六、申請專利範圍 法，其步驟更包含在另一邊緣上折疊該第一散熱板以在該 第一散熱板中形成連接至該側面部之上部。 12·如申請專利範圍第1 1項之半導體裝置之製造方 法，其步驟更包含將該第二散熱板耦合至該上部。 13·如申請專利範圍第12項之半導體裝置之製造方 法，其中該第一及第二散熱板在該半導體晶片周圍形成一 封閉體。
第20頁
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Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7262077B2 (en) * 2003-09-30 2007-08-28 Intel Corporation Capillary underfill and mold encapsulation method and apparatus
JP4220982B2 (ja) 2005-06-08 2009-02-04 富士通株式会社 分布型増幅器
JP5259053B2 (ja) 2005-12-15 2013-08-07 パナソニック株式会社 半導体装置および半導体装置の検査方法
US7390700B2 (en) * 2006-04-07 2008-06-24 Texas Instruments Incorporated Packaged system of semiconductor chips having a semiconductor interposer
US20090014870A1 (en) * 2007-07-12 2009-01-15 United Microelectronics Corp. Semiconductor chip and package process for the same
US20090243012A1 (en) * 2008-03-28 2009-10-01 Micron Technology, Inc. Electromagnetic interference shield structures for semiconductor components
JP5590869B2 (ja) 2009-12-07 2014-09-17 新光電気工業株式会社 配線基板及びその製造方法並びに半導体パッケージ
US8519515B2 (en) 2011-04-13 2013-08-27 United Microlectronics Corp. TSV structure and method for forming the same
US8481425B2 (en) 2011-05-16 2013-07-09 United Microelectronics Corp. Method for fabricating through-silicon via structure
US8822336B2 (en) 2011-06-16 2014-09-02 United Microelectronics Corp. Through-silicon via forming method
US8828745B2 (en) 2011-07-06 2014-09-09 United Microelectronics Corp. Method for manufacturing through-silicon via
US8518823B2 (en) 2011-12-23 2013-08-27 United Microelectronics Corp. Through silicon via and method of forming the same
US8609529B2 (en) 2012-02-01 2013-12-17 United Microelectronics Corp. Fabrication method and structure of through silicon via
US8691600B2 (en) 2012-05-02 2014-04-08 United Microelectronics Corp. Method for testing through-silicon-via (TSV) structures
US8691688B2 (en) 2012-06-18 2014-04-08 United Microelectronics Corp. Method of manufacturing semiconductor structure
US9275933B2 (en) 2012-06-19 2016-03-01 United Microelectronics Corp. Semiconductor device
US8900996B2 (en) 2012-06-21 2014-12-02 United Microelectronics Corp. Through silicon via structure and method of fabricating the same
US8525296B1 (en) 2012-06-26 2013-09-03 United Microelectronics Corp. Capacitor structure and method of forming the same
CN102832146A (zh) * 2012-09-06 2012-12-19 淄博美林电子有限公司 一种igbt模块封装工艺及双向散热的igbt模块
US8912844B2 (en) 2012-10-09 2014-12-16 United Microelectronics Corp. Semiconductor structure and method for reducing noise therein
US9035457B2 (en) 2012-11-29 2015-05-19 United Microelectronics Corp. Substrate with integrated passive devices and method of manufacturing the same
US8716104B1 (en) 2012-12-20 2014-05-06 United Microelectronics Corp. Method of fabricating isolation structure
US9484313B2 (en) 2013-02-27 2016-11-01 Advanced Semiconductor Engineering, Inc. Semiconductor packages with thermal-enhanced conformal shielding and related methods
US8884398B2 (en) 2013-04-01 2014-11-11 United Microelectronics Corp. Anti-fuse structure and programming method thereof
US9287173B2 (en) 2013-05-23 2016-03-15 United Microelectronics Corp. Through silicon via and process thereof
US9123730B2 (en) 2013-07-11 2015-09-01 United Microelectronics Corp. Semiconductor device having through silicon trench shielding structure surrounding RF circuit
US9024416B2 (en) 2013-08-12 2015-05-05 United Microelectronics Corp. Semiconductor structure
US8916471B1 (en) 2013-08-26 2014-12-23 United Microelectronics Corp. Method for forming semiconductor structure having through silicon via for signal and shielding structure
US9048223B2 (en) 2013-09-03 2015-06-02 United Microelectronics Corp. Package structure having silicon through vias connected to ground potential
US9117804B2 (en) 2013-09-13 2015-08-25 United Microelectronics Corporation Interposer structure and manufacturing method thereof
US9343359B2 (en) 2013-12-25 2016-05-17 United Microelectronics Corp. Integrated structure and method for fabricating the same
US10340203B2 (en) 2014-02-07 2019-07-02 United Microelectronics Corp. Semiconductor structure with through silicon via and method for fabricating and testing the same
JP6560496B2 (ja) * 2015-01-26 2019-08-14 株式会社ジェイデバイス 半導体装置
US9941260B2 (en) * 2015-09-16 2018-04-10 Mediatek Inc. Fan-out package structure having embedded package substrate
US10515887B2 (en) 2016-09-20 2019-12-24 Mediatek Inc. Fan-out package structure having stacked carrier substrates and method for forming the same

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0729940A (ja) 1993-07-12 1995-01-31 Sumitomo Electric Ind Ltd 半導体装置
JPH0864730A (ja) 1994-08-19 1996-03-08 Hitachi Ltd 半導体集積回路装置
US5739581A (en) * 1995-11-17 1998-04-14 National Semiconductor Corporation High density integrated circuit package assembly with a heatsink between stacked dies
US6201701B1 (en) * 1998-03-11 2001-03-13 Kimball International, Inc. Integrated substrate with enhanced thermal characteristics
JP2000174180A (ja) 1998-12-02 2000-06-23 Shibafu Engineering Kk 半導体装置
US6452113B2 (en) * 1999-07-15 2002-09-17 Incep Technologies, Inc. Apparatus for providing power to a microprocessor with integrated thermal and EMI management
JP2002164485A (ja) 2000-11-28 2002-06-07 Toyota Industries Corp 半導体モジュール

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