TWI231026B - Planarized plastic package modules for integrated circuits - Google Patents

Planarized plastic package modules for integrated circuits Download PDF

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Publication number
TWI231026B
TWI231026B TW090115294A TW90115294A TWI231026B TW I231026 B TWI231026 B TW I231026B TW 090115294 A TW090115294 A TW 090115294A TW 90115294 A TW90115294 A TW 90115294A TW I231026 B TWI231026 B TW I231026B
Authority
TW
Taiwan
Prior art keywords
lead
patent application
connecting rod
encapsulant
chip package
Prior art date
Application number
TW090115294A
Other languages
English (en)
Inventor
David V Caletka
James L Carper
John P Cincotta
Kibby B Horsford
Gary H Irish
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of TWI231026B publication Critical patent/TWI231026B/zh

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/16Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • HELECTRICITY
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry
    • H01L23/49551Cross section geometry characterised by bent parts
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/4501Shape
    • H01L2224/45012Cross-sectional shape
    • H01L2224/45015Cross-sectional shape being circular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • HELECTRICITY
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    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Packaging Frangible Articles (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

1231026 A7 ------— _____B7 五、發明説明(1 ~)~" --—-- 曰本發明一般有關於積體電路的塑膠封裝件。更確切地說 是有關於用來減少塑膠封裝模組彎曲和提供更加平坦的模 組的改良結構。更加確切地說是有關於提供更加平坦的模 組之改良引線框。 一 通常,積體電路晶片通過高度導電的引線框而電連接到 外部。晶片的金屬絲鍵合焊點被細軟的直徑丨爪丨1的金屬 絲連接到更厚和更堅韌的引線框導體。晶片、細軟的金屬 絲、和引線框的鄰接部分被包封在模塑塑膠中,以保護晶 片和金屬絲不受損傷,同時,延伸出塑膠的引線框導 分可以用來焊接到諸如印刷電路板之類組件的下一層。每 年有成千上萬的這種類型的模組在出售。 很多問題被認為與這個封裝概念有關聯。其中之一就是 彎曲。使成品模組彎曲的高應力能夠使積體電路晶片破裂 並使之不能正常工作。在封裝過程中,或在晶片封裝件已 經被安裝在客戶使用的電子裝置中以後,都可以出現彎曲 和破裂。成品率的下降明顯增加了封裝晶片的成本,且使 用中出現的失效會使客戶惱怒。 即使晶片不破裂,封裝件的彎曲也能在把模組引線框固 定到印刷電路板的焊接過程中導致嚴重的問題。如果塑膠 封裝模組彎曲’引線端頭的位置就可能移出平面,一些引 線端頭在焊接步驟中可能不接觸到板上的焊點。為了避免 14個問題,一種由J E D E C建立的工業平面化規範M s _ 0 2 4,規定所有的引線必須平坦,不能存在彼此偏離超過 4 m i 1的兩根引線。 -4- 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) 1231026 A7 ______Β7 ϋ明説明(2~^ 如果封裝件由具有不同熱膨脹係數(τ c Ε)的不同材料 組成,就會產生封裝件彎曲。矽晶片、金屬引線框、和塑 膠包封劑通常具有非常不同的熱膨脹係數(T CE ),而在 製造過私中或使用過程中,封裝件要經歷溫度的明顯變 化。所以,需要一種塑膠封裝的更好解決辦法,來避免能 導致4曲的/息度應力,以下的本發明提供了這種解決辦 法。 因此,本發明的一個目的是提供一種減少或消除塑膠封 裝件彎曲的方法。 本發明的另一目的是提供一種減少彎曲的引線框設計。 本發明的另-目的是提供_種平衡各個力,以便在溫度 改變時避免彎曲的引線框。 本發明的—個特徵是’引線框在一個層上具有用來電連 接到晶片的元件,並在塑膠包封劑内的帛二層上具有用來 平衡應力的額外的元件。 本發明的優點是,當封裝件經受溫度大改變時,應力被 平衡並避免了彎曲。 本發明的這些和其他目的、特點和優點,借助於包含具 有接觸焊點的半導體晶片和引線框的晶片封裝件被實 該引線框具有與接觸焊點隔開至少第一距離並位於鄰近接 觸焊點的第-層上的引線指條。包封劑把晶片和部分引線 框士封,來。位於第二層上的材料也在包封劑中。此材料 在:-第二層上具有包含長度和寬度的面積。此材料也具 有厚度、比厚度大的長度和寬度。此材料從晶片延伸第二 -5- 1231026 五、發明説明(3 距離’其中該第二距離大於第—距離。第二 用來借助於平衡g+ 61上的材料被 平坦的封裝件_和包封劑之間的熱應力而提供更加 本發明人認識到杏曰& 彎曲問題通常更加明顯小於封裝件的面積時, 小的尺寸生產,而封裝件仍1保代—代的晶片以更 , 策忏仍然保持相同的尺寸時, 題就=大。本發明提供一種在封裝件内提供更小晶片而; 增加相的万法。在本發明的較佳實施例中,材料是引線 =的-個整: 豊部分。這是與電連接到晶片的那部分不同的 曰^的包封劑中的引線框的彎曲部分。在封裝完成時,此 材料可以包;不電連接到引線的那部分引線框。在另外一 個實施例中,此材料是諸如第二半導體晶片的沒有用金屬 絲電連接到晶片的鍵合焊接點的物體。第二半導體晶片可 以被安裝到用來在裝配過程中保持其位置的條帶。 從附圖中該本發明的下列詳細描述中,本發明的上述和 其他的目的、特點、和優點將顯而易見,其中·· 圖la是包含半導體晶片和具有與引線指條分離的下置 部分的引線框的一個模組的三維視圖; 圖lb是圖la的引線框的三維視圖,示出了連接到引 線框指條連接端的下置部分; 圖2是另一實施例的三維視圖,示出了包含半導體晶 片和具有帶下置部分的引線框的一個模組; 圖3疋另一實施例的三維視圖,示出了包含半導體晶 片和具有連接到引線指條的下置部分的引線框的一個模 -6- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 裝 訂 線 1231026 A7 B7 五、發明説明(4 組; 圖4 a是另一實施例的三維視圖,示出.了包含半導體晶 片、引線框、和類比晶片的一個模組,此類比晶 線指條的下〜層; ;5丨 圖4 b是兩個實施例的俯視圖,左邊的那個示出了包本 由支架固足在圖“類比晶片下一層的物體的模組,右邊 的那個示出了厚度相似於晶片並用條帶固定到引線框 的物體; 圖4 c是圖4 b實施例的剖面圖;以及 圖4d-4f是具有各種形狀的物體的俯視圖; 圖4 d - 4 f疋具有各種形狀的物體的側視圖。 本發明人認識到,通過平衡塑膠封裝件内的各個力,可 以減少或避免弯曲。他們認識到,當引線框上面的塑膠的 厚度不同於引線框下面的厚度時,封裝件就好像是雙金屬 條’並根據溫度而彎曲。為了減少或避免彎曲,本發明人 在不同於引線框連接引線的層處的塑膠中提供了額外的材 料層’以便平衡各個力。在—個實施例中,引線框材料的 一部分被彎曲到不同於用作引線框其餘部分的層,以便平 衡各個力。在另-個實施例中,引線指條被向下_曲再回 復向上,以便更好地平衡引線指條上的各個力。 如圖ia所示,引線框22的下置連杆2〇在塑膠包封劑 26内的f點24a和24b處被f曲到明顯低於引線框 22的引線指條32層面30的層28。層28被選擇來提供 雙材料弯曲力’此力使模組36的引線指條32和積體電 表纸張尺度適用中國國家揉準(CNS) A4規格(2i〇x297公I) 1231026 五、發明説明(5 J '------- =曰曰片3 4上的某些或全部的力得到平衡。此外,下置連 從鄰近封裝件一端的位置延伸到鄰近晶# 3 4邊沿 田:X便使下置連杆20的面積最大,並使下置效應 Γ 於是’、封裝件的彎曲被減少或消除。下置連杆20 “ =A孚开y形狀,以便在引線指條3 2所提供的空間 供最大的面積,並提供機械強度和硬度。通過在下置 = '内部提供幾個支撐杆2。,,也增加了穩定二 ^ 20被足向平行於模塑過程中液體塑膠化合物的流 β ’使當硬體塑膠化合物填充物體時’連杆不被突起。提 供二置連杆20的盡可能最大面積,就提供了最大的力來 肖更咼的引線指條32的力。下置連杆2〇最好與引線 十3 2平行,但在不同的平面上。彎點2 4 &、2 4 b通過 使用工具夾住鄰近連杆2()的引線框U,然後用彎曲操 作完成時以及下置連杆2〇被置於所希望的高度並平行於 引線指條32時提供足夠彎曲的工具,壓住連杆2〇而實 現。—下置連杆20被設計成使到鄰近料指條32的最小 s為3 2 m 11而到標稱尺寸和放置的晶片3 *邊沿的最 隔為2 3 m 11,以便避免模組3 6中的電短路或機械接 ^ °這些尺寸具有±lmil的公差。下置連杆2〇也能夠被 提供成在包封劑26内具有向下的斜坡。 所希望的是,通過鍵合金屬絲37連接到晶片34的鍵 合烊點35的引線指條2位於包封劑26中高處。模組36 和其所固定於其上的印刷電路板(未示出)之間的應力被 減少到?丨線指條32在模組36的包封劑26中被突起的程 -8 -
1231026
度因此,借助於把引線指條3 2提供成與其從包封劑 2 6出來時那樣高,就增強了到電路板的連接可靠性,同 時’借助於提供T置連杆20來平衡包封劑26/中的热應 力畎減少了模組3 6内高放置所導致的應力。 在用塑膠完成包封之後,引線指條32的連接端38 (圖1 b )被切斷,並把引線指條3 2彎曲到用以安裝到 印刷電路板的位置。延伸出包封劑26的下置連杆2〇的 連接端3 8,(圖1 b )被沿著包封劑2 6的邊沿2 6,切斷。 現在,下置連杆20就與引線框22的其餘部分和晶片34 完全分離。 下置連杆2 0的引入將薄小外形塑膠封裝件(T §〇p ) 的寶曲從3. 5 mil減少到了 2mil,即減小了 42%。這種 4〇mil厚的塑膠封裝件使用了 tCE約為13的模制包封 劑’具有丁 C E為3 · 5的矽晶片以及由τ C E約為4的合 金4 2製造的引線框。引線指條3 2約為5 m丨1厚,並位 於距包封劑2 6頂部表面約9 m i 1和距包封劑底部約 26mil的地方。晶片34約為I2mil厚,並且位於距包 封劑2 6頂部表面約1 7 m i 1處。引線指條3 2用厚約 3mil的條帶46a安裝在晶片34上(圖4)。下置連杆 2 0被下置在比包封劑2 6内的引線指條3 2低約1 5 m i 1 處’以便提供彎曲改善。借助於增加下置連杆2 〇的面積 或增加下置量,能夠獲得彎曲的進一步改善。下置連杆 2 0被設計成使到鄰近引線指條3 2的最小間隔為 3 2 m i 1,而到晶片3 4端的最小間隔為2 3 m i 1,以便避免 -9 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 1231026 A7
模組36内的電短路或機械接合。 部Π』::;在變通實施例中,引線指條323的各個 ’向下設置。在這種情況下,引線指條 U32aU 和恨,以便在比引線框22㈣^ :知…的層3〇更低的層28處提供下置區域32&,。 除了或不用下置連杆2〇,能夠提供引線指條仏的下置 邵分32a,。此外,具有下置區域33,的額外的指停” 可以被提供在各引線指们2a之間的通常未被佔用、的空 間内。 4圖3所717 ’在另一個變通實施例中,下置連杆2〇a 能夠被連接到一個或更多個引線指條3 2 b。在這種情況 下,彎點24a,和24b,在比引線框22a的引線指條… 的層30更低的層28處提供下置連杆2〇a。下置連杆 2〇a連接於其上的引線指條3 2b,最好被電連接到地。如 圖3所示,如果希望的話,下置連杆2〇a可以被分開。 如圖4a所示,在另一個變通實施例中,諸如類比半導 體晶片的物體4 4被提供在比引線指條3 2 a的層3 〇更低 的包封劑26中的層28處。物體44提供力來平衡引線指 條3 2 a所提供的力。物體4 4可以被放置在與積體電路晶 片3 4大致相同的層上。在這種情況下,物體* 4和晶片 3 4都被安裝在用來在裝配過程中固定物體4 4和晶片3 4 位置的帶條46a和46b上。另外,如圖4b和圖4c所 示,物體4 4 ’可以被放置在比晶片3 4低的位置。在這種 情況下,支柱5 0用帶條把物體4 4連接到引線指條 -10- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 1231026 五 發明説明 A7 B7 3 2 a ’利用支柱的高度可以控制力。支柱5 Q &夠與物體 44成一整體,並且能夠在模塑或衝壓操作中製造。除了 半導之外,物體4 4、4 4,能用諸如合金4 2、殷鋼、柯 伐鐵鎳鈷合金、或銅-殷鋼-銅之類的金屬來製造。也能夠 用诸如陶瓷或液晶聚合物之類的絕緣體來製造。如圖4 d _ 忖所示,物體44、44,可以有各種各樣的形狀4“、 4 4b 4 4 c。可以設計這些形狀來控制裝配過程中包封劑 的泥動,以便分裂大的平坦表面,從而將物體44、* 鎖定在包封劑内的位置上。提供局部延伸通過物體44、 44’的空、洞,使平坦表面破裂,從而增強了與包封劑的接 觸’並避免了溼氣引起的問題。 雖然此處詳細描述了並在附圖中闡述了本發明的幾種實 施例及其修正’但顯然,能夠在設計下置元件的過程中作 出多種進一步修正而不偏離本發明的範圍。在上述說明書 中’沒有比所附申請專利範圍更窄地限制本發明。給出的 例子只疋為了闡述而不是排他性的。 -11 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公爱)
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Claims (1)

  1. π h t 支 Μ 123Έζ9άζϊ%,7Μ) 六、申請專利範園 D8’, 1· 一種晶片封裝件,包含·· (a)具有接觸焊點的半導體晶片; 、、(J3) ?丨線框’具有-第-主要平面的引線指條, 琢罘一主要平面係從該晶片封裝的一端延伸至鄭近該 接觸ϋ的第-階層’㈣、線指條與該接觸焊點間隔 至少一第一距離; ()匕封β曰日片和部分該引線框的包封劑;以及 (d)、在該包封劑中且與該晶片間隔一第二距離的連 杆4連杆包含-彎曲部分,用以提供一與該第一主 要表面平行且與該第一主要平面相隔一段距離的連杆 、、要表面3連杆主要表面係藉由平衡該引線指條和 d G封Μ間的熱應力而提供一阻止該晶片彎曲的 "S? ° 2. 如申請專利範圍帛i項之晶片封裝件,其中該晶片 有明顯小於封裝件的面積。 3. 如申請專利_ !項之晶片封裝件,其中該晶片 有頂:表面和延伸在該頂部表面上的該引線指條, 中孩第一層由該頂部表面確定。 4·如申請專利㈣第丨項之晶片封裝件,其中該連杆是 引線框材料。 5’如申請專利範圍第4項之晶片封裝件’其中該連杆 含該引線框的彎曲部分,其中該彎曲部分在該包封 裝 力 具 具 其 瓠 包 劑 I 桃狀度適财關家辟(CNS) Μ驗 !231〇26 A BCD 、申請專利範圍 内。 力申清專利範圍第5項之該晶片封裝件,其中該連杆 從鄰近該包封劑的邊沿的位置延伸到鄰近該晶片邊沿 的位置。 如申凊專利範圍第5項之晶片封裝件,其中該連杆具 有A字形狀。 8.如申請專利範圍第5項之晶片封裝件,其中該連杆包 含疋向平行於模塑過程中液體塑膠化合物的流向的支 撐杆。 如申叫專利範圍第5項之晶片封裝件,其中該連杆包 士封裝元成時不電連接到引線指條的部分該引線框。 10·如申請專利範圍第9項之晶片封裝件,其中該連杆與 琢引線指條充分地分隔開,以避免到引線指條的短 路。 U·如申請專利範圍第4項之晶片封裝件,其中該連杆包 含被彎曲的部分引線指條。 12. 如申請專利範圍帛i項之晶片封裝件,其中該包封劑 具有第一 T C E,該引線框具有第二T c £,該晶片具有 第三TCE,而該連杆具有第四TCE,其中該第四 T c E明顯地小於該第一 T c E。 13. 如申請專利範圍第12項之晶片封裝件,其中該第四 TCE在該第二和該第三tce之間。 〇 1_ 本紙張尺度適用中國國家標準(CNS) A4規格Τϋ^797公董)------ 1231026 A8 B8 C8 ____ D8 六、申請專利範圍 14·如申请專利範圍第1 2項之晶片封裝件,其中該第四 T C Ε實質上相似於該第二T C Ε。 15. 如申請專利範圍第1項之晶片封裝件,其中該接觸烊 點被金屬絲連接到該引線,其中該連杆包含不用金屬 絲電連接到該引線的物體。 16. 如申请專利範圍第1 5項之晶片封裝件,還包含條帶, 其中該條帶連接該物體和該引線指條,用來在裝配過 程中固定該物體的位置。 Π·如申請專利範圍第1 6項之晶片封裝件,其中該物體還 包含支柱,其中該支柱被安裝到用來在裝配過程中固 定該物體位置的該條帶。 18. 如申請專利範圍第丨項之晶片封裝件,其中該引線指 條在該包封劑外面具有用來連接到襯底的區域,該引 線指條延伸出用來連接到襯底的該區域上的該第一層 上的該包封劑。 19. 一種製造晶片封裝件的方法,包含下列步驟: (a) 提供具有接觸焊點的半導體晶片; (b) 提供一引線框,具有一第一主要平面上的引線 才曰條,違弟一主要平面係從該晶片封裝的一端延伸至 鄰近4接觸干點的第一階層,該引線指條與該接觸焊 點間隔至少一第一距離; (c )包封該晶片和部分該引線框;以及 -3- 本紙張尺度適用中國國家標準(CNS) A4規格7^ϊ〇 X 297公釐) 1231026 申請專利範圍 (d )提供一在該包封劑中 齡^ ^ 、、 ΤΤ且與琢晶片間隔一第二距 、連杆,該連杆包含一彎曲 楚一、弓两邵分,用以提供一與該 罘一王要表面平行且與該第一 , 示王要千面相隔一段距離 勺連杆主要表面,該連杆 把王要表面係精由平衡該引線 才曰‘和孩包封劑間的埶岸 …4刀而棱供—阻止該晶片彎曲 的力量。 20.如申請專利範圍第 “万法,其中該晶片實質上小 於封裝件的面積。 孔如申請專利範圍第19項之方法,其中該晶片具有頂部 表面以及延伸在該頂部表面上的該引線,其中該第一 層由該頂部表面確定。 22. 如申請專利範圍第 ^ ,、足万法,其中該連杆是該引線 框的一個整體部分。 23. 如申請專利範圍第22項之方法,其中該提供步驟⑻ 包3鹜曲部分孩引線框以形成該步驟(d)的該連杆的步 驟’其中該彎曲部分在該包封劑内。 24. 如申請專利範圍第23項之方法,其中在該彎曲部分該 引線框的步驟包含第一彎點和第二彎點,這樣該部分 平仃於该引線框的其他部分,並位於該引線框的該其 他部分下面的特定距離處。 25·如申請專利範圍第24項之方法,其中該彎曲步驟 包含用工具夾住該引線框和壓住該部分以提供該第一 -4- 本紙張尺度適财酬家鮮(CNS) A4規格(21QX297公董)' 1231026 A8 B8 C8
    包封劑邊沿的位置延伸到鄰近該E 27.如申請專利範圍第2 3項之方法, 和第二彎點的步驟。 26.如中請專利範圍第2 3 形狀。 28.如中請專利範圍第2 3 ’其中該連杆從鄰近該 晶片邊沿的位置。 ,其中該連杆具有A字 元成時並不電連接到引線指條的部分該引線框。 项之方法, 項之方法,其中該連杆包含封裝 該提供步驟(b )包含 其中该連杆在該包封 29·如申請專利範圍第2 3項之方法, 彎曲部分引線指條的步驟。 30·如申請專利範圍第2 3項之方法, 劑内傾斜。 31.如申請專利範圍第19項之方法,其中該包封劑具有第 一 TCE,該引線框具有第二TCE,該晶片具有第三 TCE,而該連杆具有第四TCE,其中第四tce實質 上小於該第一 T C E。 32·如申請專利範圍第3 !項之方法,其中該第四τ c E在 奋亥弟一 TCE和該第三TCE之間。 33·如申請專利範圍第3 1項之方法,其中第四τ c E約等 於該第二T C E。 34·如申請專利範圍第1 9項之方法,其中該接觸焊點被金 屬絲連接到該引線,其中該提供步驟(d)包含提供不被 金屬絲電連接到該引線的物體。 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 1231026 A8 B8 C8 D8 申請專利範圍 5·如申请專利範圍第3 4項之方法,其中該物體包含條 帶’其中該條帶連接該物體和該引線指條,用來在裝 配過程中固定該物體的位置。 6·如申清專利範圍第3 5項之方法,其中該物體還包含支 柱’其中該支柱被安裝到用來在裝配過程中固定該物 體位置的該條帶。 37·如申清專利範圍第1 $項之方法,其中該引線指條在包 封劑外面具有用來連接到襯底的區域,該引線指條延 伸出用來連接到襯底的該區域上的該第一層上的謗包 封劑,其中該第二層在該第一層下面。 38·如申請專利範圍第1 9項之方法,其中該包封劑具有丁貝 部表面和底部表面,且其中該引線指條延伸出距謗項 部表面比該底部表面更近的包封劑。 -6- 本紙張尺度適用中國國家標準(CNS) Α4規格(210 X 297公釐)
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