TWI222752B - Method for manufacturing a thin film transistor - Google Patents
Method for manufacturing a thin film transistor Download PDFInfo
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- TWI222752B TWI222752B TW092105009A TW92105009A TWI222752B TW I222752 B TWI222752 B TW I222752B TW 092105009 A TW092105009 A TW 092105009A TW 92105009 A TW92105009 A TW 92105009A TW I222752 B TWI222752 B TW I222752B
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- film transistor
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- 238000000034 method Methods 0.000 title claims abstract description 51
- 239000010409 thin film Substances 0.000 title claims abstract description 45
- 238000004519 manufacturing process Methods 0.000 title abstract description 11
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 238000002425 crystallisation Methods 0.000 claims abstract description 9
- 230000008025 crystallization Effects 0.000 claims abstract description 9
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims abstract description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000001301 oxygen Substances 0.000 claims abstract description 7
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 7
- 229910021529 ammonia Inorganic materials 0.000 claims abstract description 3
- 230000008569 process Effects 0.000 claims description 29
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 12
- 239000001272 nitrous oxide Substances 0.000 claims description 5
- 239000010408 film Substances 0.000 abstract description 21
- 238000005468 ion implantation Methods 0.000 abstract description 3
- 229920005591 polysilicon Polymers 0.000 abstract description 3
- 238000009832 plasma treatment Methods 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 description 13
- 238000005516 engineering process Methods 0.000 description 10
- 238000009826 distribution Methods 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 239000002184 metal Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000004575 stone Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000001994 activation Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000005224 laser annealing Methods 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000006356 dehydrogenation reaction Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 230000008439 repair process Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- -1 phosphorus ions Chemical class 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000006068 polycondensation reaction Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- QHGVXILFMXYDRS-UHFFFAOYSA-N pyraclofos Chemical compound C1=C(OP(=O)(OCC)SCCC)C=NN1C1=CC=C(Cl)C=C1 QHGVXILFMXYDRS-UHFFFAOYSA-N 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 230000016776 visual perception Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78666—Amorphous silicon transistors with normal-type structure, e.g. with top gate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
- Recrystallisation Techniques (AREA)
Description
1222752 -921·05009,__年月 曰____ 絛正_ 五、發明說明（1) 發明所屬之技術領域 •本發明係關於一種薄膜電晶體液晶顯示器（th i η film transistor liquid cryStal display, TFTLCD)之 製程’尤指一種低溫多晶矽薄膜電晶體（丨〇w temperature polysilicon thin film transistor, LTPS TFT)液晶顯示器的製作方法，其特徵在於 行硼或磷等高能粒子的離子佈值製程，而是利用特定電 漿即可完成通道區摻雜，達到調整電晶體啟動電壓 ^ threshold volt age)之目的。此外，依據本發明方法之 最佳實施例，本發明的另一優點在於可使多晶矽層之晶 粒增大，提昇元件之效能。 先前技術 在現今的平面顯不器技術中，液晶顯示器可謂其中 最為熱門的一項技術，舉凡日常生活中常見的手機、數 =相機、攝影機、筆記型電腦以至於監視器均是利用此 工、技術所製造的商品。隨著人們對於顯示器視覺感受要 =的提高，加上新技術應用領域不斷的擴展，更高畫 =、高解析度、高亮度且具低價位的平面顯示器^ ^為 來顯示技術發展的趨勢，也造就了新的顯示技術發展 曰原動力。而平面顯不裔中的低溫複晶矽薄膜電晶體液 曰曰顯示器（LCD)除了具有符合主動式驅動（acUvely drlve)潮流的特性外，其技術也正是一個可以達到上述
1222752 _案號 92105009_年月日___ 五、發明說明（2) 目標的重要技術突破。 請參考圖一至圖八，圖一至圖八為習知製作一低溫 複晶石夕薄膜電晶體（low temperature polysilicon thin film transistor, LTPS TFT)1的方法示意圖。如圖一所 示，習知之低溫複晶矽薄膜電晶體1係製作於一絕緣基板 1 0之上，絕緣基板10由透光的（transparent)材質所構 成，通常為一玻璃基板、一石英（quartz)基板或是一塑 膠（p 1 a s t i c )基板。首先，於絕緣基板1 〇之表面上沈積一 緩衝層（buffer layer)12，其可以為一氮化矽膜、一氧 化矽膜，或氮化矽/氧化矽雙層膜。接著，於緩衝層1 2上 形成一非晶矽（amorphous· si 1 icon)膜14，並進行去氫製 程（dehydrogenation)。 如圖二所示，接著進行結晶製程，例如準分子雷射 退火（excimer laser annealing， ELA)或照光製程 (photo light)，使非晶矽膜 14再結晶（re — crystallize) 成為一複晶石夕層1 4 。如圖三所示，進行一黃光暨蚀刻製 程’以定義複晶石夕層1 4,成為複數個複晶矽島丨6主動區圖 案。如国四所示，隨後進行一離子佈值製程，利用硼或 磷離子植入複晶矽島1 6，藉此調整薄膜電晶體的啟動電 壓（threshold v〇Uage)。在習知有些製程中，調整薄膜 電晶體啟動電壓的離子佈值製程亦可以接在非晶矽膜1 4 沈積之後進行。 '
1222752
案號9gj卫5009 五、發明說明（3) 如圖五所示，接著以光阻1 8定義NMOS摻雜F 進行晒離子佈值形成關05的汲極與源極。如、^或，_並 接著沈積一閘極絕緣層2 2，並在閘極絕緣層2 $上、，所、示， 阻2 6定義PM0S摻雜區域，並進行p型離子佈值形=光 汲極與源極。 / π PM0S的 如圖七所示，在去除光阻2 6之後，隨後進行一活化 (activation)製程，使源極以及汲極内之摻質被高度活 化。活化的過程除了將離子移至正確的晶格位置外，亦 有將離子植入時所造成的晶格缺陷（1 a 11 i c e d e f e c t )予 以修補的作用。如圖八所示，接著進行一金屬濺鍍製 程，以及一金屬蝕刻製程，以於閘極絕緣層2.2上定義出 閘極2 8。 由上可知，上述習知技術皆需要進行離子佈值製程 來調整薄膜電晶體的啟動電壓，然而，離子佈值儀器設 備昂貴，增加面板生產成本。鑑於此，申請人乃根據此 等缺點及依據多年從事製造該類產品之相關經驗，悉心 觀察且研究之，而提出本發明可以取代習知昂貴需要進 行離子佈值製程來調整薄膜電晶體的啟動電壓之方法， 可降低生產成本，增加產能以及良率。 發明内容 本發明的主要目的在於提供一種薄膜電晶體的製作
第8頁 1222752 _案號92105009 ^-_月 日 修正_ 五、發明說明（4) 方法’利用特定電漿即可完成通道區摻雜，達到調整電 晶體啟動電壓之目的。 為達上述目的，本發明提供一種製作薄膜電晶體的 方法，包含有提供一基材；於該基材上沈積一非晶矽 層；利用一電漿接觸該非晶矽層，以調整該薄膜電晶體 的啟動電壓（threshold voltage);及進行一結晶製程， 使該非晶矽層轉換成一多晶矽層。若該薄膜電晶體為一 N 通道薄膜電晶體，且該電漿係為一含氧電漿，可將該N通 道薄膜電晶體之啟動電壓向負方向偏移調整。若該薄膜 電晶體為一 P通道薄膜電晶體，且該電漿係為一含氨氣電 漿，可將該P通道薄膜電晶體之啟動電壓向正方向偏移調 整。 依據本發明之一實施例，本發明提供一種製作低溫 多晶矽薄膜電晶體的方法，包含有提供一透光基材；於 該基材上沈積至少一緩衝層；於一化學氣相沈積 (chemical vapor deposition, CVD)反應室内進 4亍一化 學氣相沈積（CVD )製程，以於該缓衝層上沈積一非晶石夕— 層；於該CVD反應室内，利用一電漿接觸該非晶石夕層’， 以現場（in-situ)調整該薄膜電晶體的啟動電壓；及進打 一結晶製程，使該非晶矽層轉換成一多晶石夕層。 為了使貴審查委員能更近一步了解本發明之特徵 及技術内容，請參閱以下有關本發明之詳細說明與附
1222752
說明用 並非用來對本發 圖。然而所附圖式僅供參考與 明加以限制者。 實施方式 = = 圖九至圖十五為依據本發明 f ^曰石夕薄膜電晶體1〇1係製作於一絕此j低ς ，板1〇。，透光的材質所構成，通常為一玻璃基板、、、邑一 石央uuartz)基板或是一塑膠（plastic)基板。首先，於 絕緣基板100之表面上沈積一緩衝層（buf fer layer)、 11 2，其可以為一氮化矽膜、一氧化矽膜，或氮化矽/氧 化矽雙層膜。接著，於緩衝層丨i 2上形成一非晶矽 amorphous silicon)膜114。非晶矽膜114係在一電漿加 強氣相沈積（P E C V D )機台令進行，隨後，在同一機台中， 利用一氧化二氮（N 2〇)電漿接觸非晶矽膜1丨4表面，以調整 溥膜電晶體啟動電Μ。依據本發明之較佳實施例，一氧 化二氮（Ν2〇)電漿係在一氧化二氮氣體流量為1 0 0 0sccm， 380C之溫度下’無線電波功率（rf power )小於5 0 0瓦 (W)，較佳在100W左右，若換算成功率密度（p〇wer density)，以40公分X 32公分之面板尺寸為例，其功率密 度為 100W/(40cmx 32cm)=0.〇78W/cm2。對於 N型薄膜電晶 體而言，圖十六顯示在上述條件下所進行之啟動電壓調 整曲線，由1 0秒至5 0秒的不同製程時間，N型薄膜電晶體 的啟動電壓可由原先的2 · 5伏特（V)分別降至1. .4 V以及
第10頁 1222752 _案號 921050(^_年月日_修正—_ 五、發明說明（6) 0. 4 V。對於P型薄膜電晶體而言，圖十七顯示在上述條件 下所進行之啟動電壓調整曲線，由1 0秒至5 0秒的不同製 程時間，P型薄膜電晶體的啟動電壓可由原先的—2· 4伏特 (V)分別降至-4· 2V以及-5· 6V。隨後，可進行去氫製程 (dehydrogenation) 〇 雖然，一氧化二氮（N20)電漿乃為半導體製程上常用 之氣體電漿，然而，將其用在薄膜電晶體啟動電壓之調 整乃刖所未見之創新。如此，即可不用較昂貴的離子佈 值製程，而可改以現場（in —situ)進行啟動電壓的調整， 亦即，直接於沈積完非晶矽膜11 4之後，於同一 CVD反應 室中進行’十分節省成本並可提昇產能。對於N型薄膜電 晶體而言，若要提高啟動電壓值，依據本發明之較佳實 施例，係採用氨氣（NH 〇電漿。此外，申請人更意外地發 現除了一氧化二氮（N 2〇)電漿之外，利用氧氣電漿亦可^ 到同樣調整薄膜電晶體啟動電壓之目的。利用電漿調整 啟動電壓之另一優點在於電漿可以在非晶矽膜丨丨4表面上 开> 成厚度僅有十幾埃（angStrom)的氧化薄膜，可藉此在 後續結晶過程中，使非晶矽轉換成較大顆粒的多 構，提昇薄膜電晶體元件的效能。 的夕明石夕、^ 、如圖十所示，接著進行一結晶製程，例如準分子雷 射退火（excimer laser annealing, ELA)或照光製程， 使非晶石夕膜114再結晶（re-crystal 1 ize)成為一複晶石夕層 114。依據本發明之另一較佳實施例，上述利用電漿調
ΠΒ
第11頁 1222752 修正 案號 92105009 五、發明說明（7) 整薄膜電晶體啟動電壓之步驟，亦可在6 如雷射退火或照光）之後進行。如圖十在^ 所成結晶製程（= 光暨蝕刻製程，以定義複晶矽層丨丨4,成不，進仃一黃 島116主動區圖案。依據本發明之又另成為硬數個;复晶矽 述利用電聚調整薄膜電晶體啟動電壓之步驟'貫广 數個複晶矽島1 1 6定義完成之後進行。 了在複 计-隹ί Ϊ刑十Μ二示，接著以光阻118定義NM〇S摻雜區域， ^進订Ni離子佈值形成NMOS的汲極與源極。如圖十三所 示，接著沈積一閘極絕緣層122,並在閘極絕緣層12^ 上，以光阻126定義PMOS摻雜區域，並進行p型離子佈值 形成PMOS的汲極與源極。 如圖十四所示，在去除光阻1 2 6之後，隨後進行一活 化（act i vat ion)製程，使源極以及汲極内之摻質被高度 活化。活化的過程除了將離子移至正確的晶格位置外， 亦有將離子植入時所造成的晶格缺陷（lattice defect) 予以修補的作用。如圖十五所示，接著進行一金屬濺鍍 製程，以及一金屬蝕刻製程，以於閘極絕緣層1 2 2上定義 出閘極1 2 8。 相較於習知技藝，本發明藉由電漿處理方式，達到 調整啟動電壓之目的。利用N Η 3電漿處理可用以調整I - V曲 線往正·的的方向偏移，而利用Ν 2〇電漿處理可用以調整I 一 V 曲線往負的方向偏移。藉由調整RF功率以及電漿處理時
第12頁 1222752 _案號92105009_年月曰 修正_ 五、發明說明（8) 間可以決定啟動電壓的偏移量。以上種種優點均顯示本 發明已完全符合專利法所規定之產業利用性、新穎性及 進步性等法定要件，爰依專利法提出申請，敬請詳查並 賜准本案專利。 以上所述僅為本發明之較佳實施例，凡依本發明申 請專利範圍所做之均等變化與修飾，皆應屬本發明專利 之涵蓋範圍。
第13頁 1222752 _案號92105009_年月日_Hi_ 圖式簡單說明 圖式之簡單說明 圖一至圖八為習知製作一低溫複晶矽薄膜電晶體的 方法不意圖 圖九至圖十五為依據本發明一較佳實施例之剖面示 意圖。 圖十六為N型薄膜電晶體之啟動電壓調整曲線。 圖十七為P型薄膜電晶體之啟動電壓調整曲線。 圖式之符號說明
第14頁 1 絕 緣 基. 板 10 低 溫 複 晶石夕 薄膜電 晶體 12 緩 衝 層 14 非晶 矽 膜 14’ 複 晶 矽 層 16 複晶 矽 島 18 光 阻 22 閘極 絕 緣 層 26 光 阻 28 金屬 閘 極 100 絕 緣 基 板 101 低 溫 複 晶石夕 薄膜電 晶體 112 缓 衝 層 114 非晶 矽 膜 114’ 複 晶 矽 層 116 複晶 矽 島 118 光 阻 122 閘極 絕 緣 層 126 光 阻 128 金屬 閘 極
Claims (1)
1222752 _案號92105009_年月日__ 六、申請專利範圍 1. 一種製作薄膜電晶體的方法，包含有： 提供一基材； 於該基材上沈積一非晶矽層； 利用一含氧電漿接觸該非晶矽層，以調整該薄膜電 晶體的啟動電壓（threshold voltage)向負方向偏移調 整；及 進行一結晶製程，使該非晶矽層轉換成一多晶矽 層。 2. 如申請專利範圍第1項所述之方法，其中沈積該非晶 矽層之前，另包含有以下步驟： 於該基材上沈.積至少一缓衝層（buffer layer)。 3. 如申請專利範圍第2項所述之方法，其中該緩衝層包 含有一氮化碎層。 4. 如申請專利範圍第1項所述之方法，其中該含氧電漿 為一氧化二氮（N20)電漿。 5. 如申請專利範圍第1項所述之方法，其中該含氧電漿 為氧氣電漿。 6 .如申請專利範圍第1項所述之方法，其中該電漿係在一 預定無線電波功率下形成。
第15頁 1222752 _案號92105009_年月日__ 六、申請專利範圍 7. 如申請專利範圍第6項所述之方法，其中該預定無線電 波功率小於5 0 0瓦。 8. —種製作薄膜電晶體的方法，包含有： 提供一基材； 於該基材上沈積一非晶矽層； 利用一氨氣電漿接觸該非晶矽層，以調整該薄膜電晶體 的啟動電壓向正方向偏移調整；及 進行一結晶製程，使該非晶矽層轉換成一多晶矽層。 9. 如申請.專利範圍第8項所述之方法，其中沈積該非晶矽 層之前，另包含有以下步驟： 於該基材上沈積至少一緩衝層。 1 0 .如申請專利範圍第8項所述之方法，其中該缓衝層包 含有一氮化石夕層或一氧化石夕層。 11.如申請專利範圍第8項所述之方法，其中該電漿係在 一預定無線電波功率下形成。 1 2.如申請專利範圍第1 1項所述之方法，其中該預定無線 電波功率小於5 0 0瓦。
第16頁
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| TW092105009A TWI222752B (en) | 2003-03-07 | 2003-03-07 | Method for manufacturing a thin film transistor |
| US10/249,585 US20040175870A1 (en) | 2003-03-07 | 2003-04-22 | Method for manufacturing a thin film transistor |
| JP2003143449A JP4079364B2 (ja) | 2003-03-07 | 2003-05-21 | 薄膜トランジスタを製造する方法 |
| JP2007324732A JP4158055B2 (ja) | 2003-03-07 | 2007-12-17 | 薄膜トランジスタを製造する方法 |
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| TW092105009A TWI222752B (en) | 2003-03-07 | 2003-03-07 | Method for manufacturing a thin film transistor |
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| US7600999B2 (en) * | 2003-02-26 | 2009-10-13 | Align Technology, Inc. | Systems and methods for fabricating a dental template |
| TWI247432B (en) * | 2004-12-03 | 2006-01-11 | Chunghwa Picture Tubes Ltd | Manufacturing method of thin film transistor and poly-silicon layer |
| TWI311213B (en) * | 2004-12-24 | 2009-06-21 | Au Optronics Corp | Crystallizing method for forming poly-si films and thin film transistors using same |
| TW200924033A (en) * | 2007-11-16 | 2009-06-01 | Tpo Displays Corp | Method for forming a polysilicon thin film layer |
| WO2012081474A1 (ja) * | 2010-12-14 | 2012-06-21 | シャープ株式会社 | 結晶性半導体膜の形成方法 |
| CN102629558B (zh) * | 2012-01-09 | 2015-05-20 | 深超光电（深圳）有限公司 | 低温多晶硅薄膜晶体管制造方法 |
| KR101507381B1 (ko) * | 2014-02-26 | 2015-03-30 | 주식회사 유진테크 | 폴리실리콘 막의 성막 방법 |
| CN104037127A (zh) * | 2014-06-11 | 2014-09-10 | 京东方科技集团股份有限公司 | 一种多晶硅层及显示基板的制备方法、显示基板 |
| KR101927579B1 (ko) * | 2016-02-19 | 2018-12-10 | 경희대학교 산학협력단 | 전이금속 디칼코게나이드 박막 트랜지스터 및 그 제조방법 |
| CN108335969B (zh) * | 2018-02-05 | 2020-08-18 | 信利（惠州）智能显示有限公司 | 改善tft器件阈值电压的处理方法 |
| CN109616476A (zh) * | 2018-12-17 | 2019-04-12 | 惠科股份有限公司 | 主动开关及其制作方法、显示装置 |
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| JP4079364B2 (ja) | 2008-04-23 |
| JP2004274012A (ja) | 2004-09-30 |
| JP2008147680A (ja) | 2008-06-26 |
| TW200418190A (en) | 2004-09-16 |
| US20040175870A1 (en) | 2004-09-09 |
| JP4158055B2 (ja) | 2008-10-01 |
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