TW312029B - Manufacturing method of thin film transistor - Google Patents

Abstract

A method of forming transistor, which is used to semiconductor device process, comprises of at least the steps: (1) forming one conductive layer on one substrate; (2) forming one dielectric on the conductive layer and the substrate; (3) forming one first layer on the dielectric; (4) forming one second layer on the first layer; (5) patterning one photoresist on the second layer; (6) patterning multiple heavily doped regions on the first layer and the second layer; (7) heating the first layer and the second layer to execute annealing step, therefore the first layer and the second layer form one polycrystalline silicon layer; (8) etching partial polysilicon to form one channel region; (9) patterning drain and source region on the polysilicon layer; (10) forming one drain electrode and one source electrode of the semiconductor device; (11) forming one passivation on the drain electrode, the source electrode, the channel region and the dielectric.

Description

The Ministry of Economic Affairs of the People's Republic of China Zhongzhang Bureau of Industry and Commerce Cooperative Printing and Printing Co., Ltd. 312029 A7 B7 V. Description of the invention (I) 5.1 Field of the invention: The present invention relates to an inverted stacked polycrystalline thin-film transistor (inverted staggered ploy- Si thin-film transistor) low temperature (low temperature) process. In particular, it relates to a low-temperature process of reverse stacking polycrystalline silicon thin film transistors that uses laser annealing. 5_2 Background of the invention: As the technology of the semiconductor industry becomes more sophisticated, the density and quality of each pixel in an active matrix liquid crystal display (Active Matrix Liquid Crystal Display: AMLCD) also increase, so amorphous silicon hydrogen (hydrogenatedamorphoussilicon: a-Si: H), because of its low mobility, it is restricted in the application of thin film transistor (Thin Film Transistor: TFT), so the high mobility of poly crystalline silicon (poly crystalline silicon: poly-Si) It will be more attractive when manufacturing thin-film transistors in liquid crystal displays, and it is also easier to manufacture the peripheral driving circuits in the form of integrated circuits. The aforementioned technology can be referred to: "Cell Design Consideration for High-Aperture-Ratio Direct-View and Projection Polysilicon TFT-LCDs", 1995 Society For Imformation Display, Orlando, Florida, SID 1995, pp. 19-22, (199 5) Bu W. Wu ,. A cross-sectional view of a reverse stacked thin film transistor fabricated in a low temperature process is shown in the first figure. 2 The size of this paper is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 83. 3.10,000 (please read the precautions on the back before filling out this page) Binding-Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 312029 A7 _B7____ 5. Description of the invention (1) In the first picture, the substrate 100 is made of glass, and the gate, source and drain are represented by 103, 101 and 102 respectively. The polysilicon layer 104 is the channel layer of the thin film transistor. The dielectric layer 105 is an insulating substance, amorphous silicon hydride (a-SiO: H>), and the protective layer 106 is a layer deposited by Plasma Enhanced Chemical Vapor Deposition (LPCVD) Of amorphous silicon hydrogen nitride (a-

SiN: H) alloy. Amorphous silicon hydrogen alloy (hydrogenated amorphous silicon: a-Si: H) is often used in some semiconductor manufacturing processes. However, since the electrical characteristics of amorphous hydrogen are more than that of crystal, it can be replaced by polycrystalline silicon Amorphous silicon, especially the thin film transistors used in active matrix liquid crystal displays. Amorphous silicon hydrogen can be converted into polysilicon by heating, and there are many methods in the semiconductor process that can be used for heating. Because the gate metal layer of the reverse stacked thin film transistor is first formed, and the base of the thin film transistor is mostly glass, the process of the thin film transistor is preferably kept at a low temperature. In order to realize the low temperature process of thin film transistors, laser tempering (| aSerarmea | jng) is often used to convert amorphous stone into polysilicon. The tempering laser used as a polycrystalline silicon crystal is described in: "New Excimer-Laser-Crystallization Method for Producung Large-grained and Grain Boundary-

Location-Controlled Si Films for Thin Film Transistors ",

Appl. Phys. Lett., 68, pp. 1513-1515 (1996), HJ Kim and James S. 1m ,. 3 (Please read the precautions on the back before filling out this page) Binding · The size of the printed paper is for China Standard (CNS) A4 specification (210X297mm) 83. 3.10,000 312029 A7 A7 B7 5. Description of invention (B) In the process of thin film transistors used in liquid crystal displays, amorphous silicon is often used to convert into polycrystalline silicon, In order to make the transistor have better electrical properties, the theory of its conversion is described in: "A Thermal Description of the Melting of c- and a-SiIicon under Pulsed Excimer

Lasers ”, Applied Surface Science, 36, pp, 1-1 1, (1989), by De Unamuon and E Fogarassy. Especially in inverted stacked polycrystalline stone evening thin film transistors (inverted staggered .ploy-Si thin- In the process of film transistor, the laser annealing (| aser annealing) is used to convert the amorphous silicon on the upper insulating layer of the gate to polysilicon, and the polysilicon channel layer of the thin film transistor is formed to form the upper insulating layer on the gate For the polysilicon layer, the laser energy used for tempering must be carefully controlled. ≪ Because the electrical properties of the transistor are mainly determined by the polysilicon channel layer above the insulating layer on the gate, the tempering step affects the thin film transistor. If the energy of the tempering laser is too small, the amorphous silicon above the insulating layer on the gate cannot be completely converted into polysilicon, which is the main reason for the poor electrical properties of many thin film transistors. Central Ministry of Economic Affairs Printed by the Bureau of Standards and Staff Consumer Cooperative (please read the precautions on the back before filling in this page) In order to avoid the above situation, the ability to temper the laser must be strengthened In order to convert amorphous silicon to polysilicon. When the energy of the tempering laser is too large, part of the amorphous silicon above the insulating layer on the gate, or even the thin film transistor itself will be evaporated, resulting in Its surface roughness and unpredictable electrical curve θ and its impact are described in the following writing: “Surface 4 This paper scale is applicable to the Chinese National Standard (CNS) M specifications (21〇 < 297mm) Central Ministry of Economic Affairs Printed by the Bureau of Standards and Staff Consumer Cooperative 312029 A7 ________B7 V. Description of invention (+)

Roughness Effects in Laser Crystallized Polycrystalline Silcon ", Appl, Phys. Lett., 66, pp. 2060-2062, (1995), by D.J. Mcculloch and S. D.

Brotherton. In addition to the above shortcomings, if the laser energy is too large, it is possible to conduct heat from polysilicon or amorphous silicon to the insulating layer, resulting in damage to the insulating layer and increased leakage current of the gate. Excess heat may also cause the gate metal to diffuse into the insulating layer and even short-circuit the source and drain. As mentioned above, if the energy of the tempering laser is too large or too small, the electrical properties of the thin film transistor will be poor. Therefore, in the process of the thin film transistor, the tempering process is a key step. One problem is that when the thickness of the deposited amorphous stone is too thick, the amorphous silicon located deep cannot be converted into polycrystalline silicon by the laser tempering process. And in general, the thickness of amorphous silicon is not the same everywhere. For the same laser tempering energy, it may not be applicable to all positions of amorphous silicon. Therefore, the laser energy It is extremely difficult to convert amorphous silicon into polysilicon at all locations. E Because of the low temperature process used in the process of reverse stacked polycrystalline silicon thin film transistors, so in the process of reverse stacked polycrystalline silicon thin film transistors' The most frequently used process is laser tempering.9 According to the factors mentioned in the previous paragraphs, it is extremely difficult to control the energy of the tempering laser to the right. The polysilicon formed by the low-energy tempering laser is located at the gate. The 5 paper standards are applicable to the Chinese National Standard (CNS) Α4 specification (210Χ297 mm) (please read the precautions on the back before filling this page). ·,-· Β A7 printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (5) The structure near the edge of the butt joint is shown in Figure 2 as 9 is obvious, there is still a part of amorphous silicon 203 It remains on the junction between the channel layer 202 and the gate insulating layer 201. When the carrier passes, the carrier is easily scattered by some amorphous silicon 203. When these amorphous silicons are replaced by microcrystalline silicon (mJr. Crystal silicon: pC-Si) or polycrystalline silicon, the scattering will be reduced ’so the electrical properties of thin film transistors can be improved. 5_3Objective and summary of the invention: Rong In the background of the above invention, the low-temperature process in the traditional reverse stacked thin film transistor process' tempering laser energy is not easy to adjust to the right, and the process of forming the channel layer of the polysilicon film It is also very complicated. Therefore, the present invention provides a low-temperature process for a reverse stacked thin film transistor. In particular, it relates to a low-temperature process for a reverse stacked thin film transistor with laser tempering. First, a conductive layer is formed on the base layer (the conductive layer may be metal), and then a dielectric layer is formed on the conductive layer and the base layer to complete the structure of the bottom layer of the reverse stacked thin film transistor. Next, a microcrystalline silicon layer is formed on the aforementioned dielectric layer, and then an amorphous silicon hydrogen layer is formed on the microcrystalline silicon layer, and then a photoresist layer is formed on the amorphous silicon hydrogen layer and exposed to Form a patterned photoresist layer (p) and then define a plurality of heavily doped (heavily doped) areas on the micro-private paper scale to apply the Chinese National Standard (CNS) A4 specification (210X297 mm) (please read the notes on the back Please fill in this page for details) Binding * Order A7 _B7 printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (6) The crystalline silicon layer and the amorphous silicon hydrogen layer are heated by the laser to the microcrystalline silicon layer and amorphous The silicon-hydrogen layer performs an annealing step. Therefore, the microcrystalline silicon layer and the amorphous hydrogen layer form a polycrystalline silicon layer, and etch a portion of the polycrystalline silicon layer to form a channel region. Then, the drain and source regions are defined on the polysilicon layer, and then the drain electrode and the source electrode of the reverse stacked thin film transistor are formed, and then a passivation is formed on the stepless electrode and the source electrode , The channel area and the dielectric layer, this completes the manufacture of a thin film transistor with better electrical properties than traditional techniques. The performance of thin film transistors is explained in: "A High Performance Polysilicon Thin-Film transistor Using XeCI Excimer Laser Crystallization of Pre-Patterned Amorphuous S > i Films ", IEEE Trans, on ED, vol 4 3, no. 4, pp. 561 -567, (1996), by Min Cao, et.al. The main purpose of the present invention is to improve the inconvenience of controlling the energy of the tempering laser, so as to reduce the damage to the transistor structure caused by improper energy control. The present invention In addition to reducing the inconvenience of controlling the energy of the tempering laser, and the quality of the amorphous silicon into polycrystalline silicon and wood will be reduced, so it is a better thin film transistor thin film manufacturing process ^ The process is described in: "Α Fabrication of Homogenious Poly -Si TFT s Using Excimer Laser Annealing ", Extented Abstracts of the 1992 International Conference on Solid State Devices and Materials, Tsukuba, pp. 55-57, (1992), by Asia, N. Kato, et. Al. Applicable to the Chinese National Standard (CNS) A4 specification (210 > < 297mm) I ----: -------- f installed ------ order ------ 1. I (Please read the notes on the back first (Fill in this page) 312029 A7 B7___ 5. Description of the invention (f) (Please read the notes on the back before filling in this page) When the polysilicon film is formed in the process of the present invention, the microcrystalline silicon layer is formed in the same machine As for the amorphous silicon hydrogen layer, a polycrystalline silicon layer can be formed after one tempering, so there is no need to change the machine, which reduces the chance of defects, so it will not increase the complexity of the process and will not reduce the electrical properties of the thin film transistor. Its structure is described in: "Inverse Staggered Poly-Si and Amorphuous Si Double Structure TFTs for LCD panels with Peripheral Driver Circuit Integration", IEEE Trans on ED. Vol. 43, no. 5, pp 701-705, (1996), by Takashi Aoyama, et. al. Another object of the present invention is to use a traditional process plus a plasma-enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition: PECVD) deposited microcrystalline silicon layer as a gate The buffer layer between the insulating layer and amorphous silicon hydrogen can increase the energy range of the tempering laser that can be tolerated and reduce the defects of amorphous hair in small areas on the edge of the polysilicon and gate insulating layer. The resulting carrier scattering (trapping) and carrier trapping (trapping) effects and the resulting serious consequences, therefore, the characteristics of the reverse stacked thin film transistor are improved. Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. According to the above-mentioned purpose, in the low-temperature process of reverse stacked thin film transistors, the present invention provides a laser tempering process technology is not more complicated than the traditional technology ' The transistors produced have better electrical properties than traditional technologies' and all process temperatures can be controlled below 400 eC. The foregoing manufacturing process is described in the following article: "Fabrication of Low-Temperature Bottom Gate Poly-Si TFTs on 8 This paper standard is applicable to the Chinese National Standard (CNS) A4 specification (21〇X: 297 mm) Employees of the Central Bureau of Standards of the Ministry of Economic Affairs Printed by the consumer cooperative A7 B7 V. Description of invention (8) Large-Area Substrate by linear-Beam Exc.imer Laser Crystallization and Ion Doping Method ", 1995 International Electron Devices meeting, Washington, DC, IEDM 95, pp. 829-832 , (1995), by H. Hayashi. A brief description of the 5-4 diagram: All the features of the present invention described above will be described more clearly by the following description and reference drawings. Figure 1 is a cross-sectional view of the structure of an inverted staggered poly-Si thin-film transistor. -------- ^, installed-(please read the precautions on the back before filling in this page) Figure 2 is the channel (cha η ne 丨) layer of the reverse stacked polysilicon thin film transistor, located in Amorphous silicon (am 〇rph 〇uss M ic 〇m S i) is still a section between the insulating layer and the polysilicon layer, and its size is expressed by the size of the crystal. Figures 3A to 3F are schematic diagrams of a series of manufacturing processes in the first preferred embodiment for manufacturing a reverse stacked polysilicon thin film transistor. Figure 3A is a method according to the present invention for manufacturing a reverse stack A cross-sectional view of the first preferred embodiment of a diurnal polycrystalline silicon thin film transistor. The drawing includes the production of gate electrodes, dielectric layers, and micro-paper on a base layer from the applicable Zhongguanjia Standard (⑽) A4 (21 () × 297mm) 83. 3.10,000 Order 312029 Central Ministry of Economic Affairs A7 B7___ printed by the Staff Cooperative of the Bureau of Standards V. Description of the invention (?) A layer of microcrystalline silicon (μο-Si) and a layer of hydrogenated amorphous silicon (a-Si: H) ° 3B The picture shows the back exposure process used in the production of patterned photo resist in the process of reverse stacking polysilicon thin film transistors. Figure 3C is a cross-sectional view of the process of reverse stacking polysilicon thin film transistors to illustrate the use of phosphorus ion implantation to form a microcrystalline silicon layer and a heavily doped region in an amorphous silicon hydrogen layer. Figure 3D shows the process of laser annealing of the microcrystalline silicon layer and amorphous silicon hydrogen layer after removing the photoresist in the process of reverse stacking polysilicon thin film transistors Profile view. Figure 3E is a cross-sectional view of the patterned photoresist used to form the transistor channel layer in the polysilicon layer made by laser tempering in the process of reverse stacking polysilicon thin film transistors. Figure 3F is a cross-sectional view of the thin-film transistor after forming the gate electrode, source / drain region, source / drain electrode and protective layer in the thin-film transistor during the process of reverse stacking polysilicon thin film transistor . Figure 4 is the transfer curve of source-drain current (| DS) to gate-source voltage (VGS) (transfer cu rive), where the thin-film transistor is used in the invention (please read the notes on the back before filling in Page)

、 1T 10 The paper size is suitable for financial standards (CNS) A4 specification (21〇Χ297 公 楚) 312029

Fifth, the description of the invention ((0 completed by an embodiment. And the polysilicon layer has a variety of different thicknesses, and the energy of the tempering laser used to form the polycrystalline stone evening layer is 254mJ / cm2. --- ------ "'installation- (please read the precautions on the back before filling in this page) Figure 5 is a line graph of the mobility versus laser at different polysilicon film thickness. The polysilicon film Is the channel layer in the thin film transistor made in the first embodiment of the present invention. Figure 6 is a cross-sectional view of the channel in the reverse stacked polysilicon thin film transistor formed by the low temperature process, in which the insulation At the junction between the layer and the polycrystalline cut layer, the original amorphous hair has been replaced by a polycrystalline cut, and the size of its cross-sectional view is also expressed in terms of the size of the crystal. 5 · 5 Detailed description of the invention: Central Bureau of Standards, Ministry of Economic Affairs Employee's consumer cooperatives printed liquid B3 displays made with more and more low-temperature polycrystalline Shixi thin-film transistors. In the manufacture of low-temperature polycrystalline Shixi thin-film transistors as each pixel (pixel) Switch and peripheral drive circuit The temperature of the polycrystalline silicon thin film used to form polycrystalline silicon thin film transistors is decreasing, and the trend of this low temperature process is already a mainstream. Therefore, the plasma enhanced chemical vapor deposition method (Piasma Enhanced Chemical Vapor Deposition: PECVD) deposits thin films of various thicknesses, the process temperature of which is controlled below 400 ° C to test the electrical properties of thin films of various thicknesses. Basically, reverse stacked polycrystalline silicon thin film transistors In the manufacturing process, it is necessary to adjust the appropriate laser energy to transform amorphous silicon into polycrystalline paper. The standard is suitable for the national standard (CNS) M specifications (21GX297). The A7 is printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. ..___ B7 _ »——— _ * " 1-. V. Description of the invention (") A silicon 'and the polysilicon layer on the insulating layer have good electron transfer properties, which is very difficult. In the manufacturing process of stacked polysilicon thin film transistors, the present invention provides a method that can use laser annealing (laserannea 丨 ng) under low temperature conditions with only one In this way, the channel layer of the thin film transistor can be formed, and no amorphous silicon remains in the channel (polysilicon layer) of the thin film semiconductor, nor does it cause damage to the reverse stacked thin film transistor itself. The tempering process used to form the polysilicon film in the present invention uses only one laser tempering, and the polysilicon film can be formed only in the same machine, so its electrical properties are better than the process of deposition and tempering divided into two. Referring to FIG. 3A, a layer of metallic chromium (Cr) is sputtered on the glass substrate 310 to form a chromium layer 311, wherein the chromium layer 311 is used as a gate electrode of the thin film transistor. The thickness of the chromium layer 311 is 200 nm, and the size of the glass substrate 310 is 300x300 mm2. The next step is to deposit a layer of hydrogenated amorphous silicon oxide (a-SiO: H) on the glass substrate 310 by plasma enhanced chemical vapor deposition method to form a-SiO with a degree of 300nm : H layer 312, used as a dielectric layer. Then, a plasma-enhanced chemical vapor deposition method is used to deposit a layer of microcrystalline silicon (μ〇- $ Γι) on the oxidized amorphous silicon hydrogen layer 312 to form a layer of microcrystalline silicon with a degree of 3 nm 313, the lower layer of the channel is formed after laser annealing. With reference to the thin film transistor, the dielectric layer is used as the gate book. The paper standard is applicable to the Chinese National Standard (CNS) A4 (2lX297mm) (please read the precautions on the back and fill in this page). Set the Central Standard of the Ministry of Economic Affairs --_ A7 ~~~ ----- B7 5. Description of the invention (Try ———-— The insulating layer between the electrode and the channel. The PE c VD deposition used to form microcrystalline silicon The mixed gas used in the method is composed of hydrogen (H〇 and silicon methane (SiH4), wherein the proportion of hydrogen flow rate must be greater than 90% to form microcrystals. In the process of forming microcrystals in the present invention, the hydrogen rolling flow It is set at 195 sccm, and the flow rate of silane is set at 5 sccm. Then, in the same machine, a layer of amorphous hydrogen with a thickness of about 60 nm is deposited on the micro-ag layer 31 3 by PECVD deposition method. It is used as the amorphous silicon hydrogen layer 314. The mixed gas used in this amorphous silicon hydrogen manufacturing process is the same as the mixed gas used in the previous PECVD deposition method for manufacturing microcrystalline silicon, but the flow rate of hydrogen is 195 sccm, and The flow rate of Shi Xijia burning is 40sccm, so in The hydrogen gas flow rate is less than 90% of the mixed gas flow rate, and the process temperature of both PECVD processes is about 260 eC. Referring to Figure 3B, the next step is to lay a layer of photoresist on the amorphous silicon layer 314, Immediately following backside exposure, the chrome layer 311 is used as a photomask to expose the photoresist to obtain a patterned photoresist (patterned photo re si st> layer 315. The gate is the gate (chromium layer 311 ) It can be used as a photomask itself, so it can save a light army process step in the back exposure process. Figure 3B is a cross-sectional view of the wafer used in the back exposure process, and the light source is 31 7 Refer to Figure 3C, after obtaining the patterned photoresist layer 315, the channel layer I- n I n-IIIH it n ϋ IIIT (please read the precautions on the back before filling this page) 13 copies printed by the consumer cooperative The paper size is applicable to China National Standard (CNS) A4 specification (210X297mm) 312029 A7

V. Description of the invention ((3) The heavily doped area used for contacting the electrode and the source electrode in the printing of the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs can be obtained by plasma treatment, for example, with phosphorus ion implantation, and In Fig. 3C, the phosphorus ion implantation is represented by 3 to 8. Phosphorus ion implantation is performed by the plasma generated by the mixed gas of ph3 and & PHs, and the proportion of the mixed gas It is 1%, and the temperature is at room temperature (about 26.0). After ion implantation, the portion of the amorphous silicon hydrogen layer 314 exposed outside the photoresist, and the microcrystalline silicon layer 313 below it are transformed The heavily doped amorphous silicon hydrogen layers 319 and 321 and the heavily doped microcrystalline silicon layers 320 and 322. Referring to Figure 3D, after removing the photoresist, the wafer can be laser tempered. The substrate after completing the above process steps is placed in a nitrogen atmosphere, and is tempered in an environment of 400 t for two hours to remove hydrogen atoms embedded in the amorphous hydrogen-generating layer 9 However, the aforementioned process steps Not necessary 'because the amorphous silicon hydrogen layer is irradiated with a low-energy laser, it can also be obtained As a result of laser tempering the wafer, the amorphous silicon hydrogen layers 3 and 3 were transformed into polycrystalline hair layers 316, while the re-doped impurity regions 319, 320 and 321, 322 'were converted to heavy doping, respectively. Miscellaneous polysilicon regions: 323 and 324. If there are other traditional heating and tempering process steps, it can be used on the structure of this non-BH wind and microcrystalline hair, which can be converted into polycrystalline fragments. The warm tempering process can also be adopted by the present invention and has the same effect. Referring to FIG. 3E, after the photoresist is applied, it is exposed to form a patterned photoresist layer 325, and then the heavily doped polysilicon layer Do the etching to make the polycrystalline paper standard suitable for the Chinese coffee house standard (CNS) A4 specification (21GX297mm) (please read the precautions on the back before filling in this page) System A7 --_ B7 5. Description of the invention (丨 +) The silicon layer is formed as shown in 323a, 324a, and 316 in Figure 3F. The next step is to sputter the source and drain contact metals. The method of formation It is first sputtered with 50nm chromium, and then plated with a layer of 600nm aluminum, so that It forms chromium layer 325 and aluminum layer 326 in Figure 3E respectively. Then the entire wafer is treated with hydrogen plasma for one hour, and then a layer of amorphous silicon nitride with a thickness of 400 nm is deposited under PECVD at 260 ¾ Hydrogen (a_siNx: H) was chosen to be 3nm in order to form the protective layer 327p microcrystalline precious layer 31 3 because polycrystalline silicon thin film transistors of various thicknesses have been tested and their source-drain current (Ids) The graph of the electrical conversion characteristic of the gate-source voltage (VGS) is shown in Figure 4. The dotted line represents the source drain voltage (Vds) equal to 0. Volt (V), and the solid line represents the source The drain voltage (VDS) is equal to 5 volts. In this experiment, the polycrystalline evening layer was made by laser tempering with an energy density of 254mJ / cm2. Referring to FIG. 4, the lines 401 and 410 represent the conversion characteristic curve of the polycrystalline silicon thin film transistor without the microcrystalline silicon layer, and the lines 4 0 3 and 4 3 0 represent the polycrystalline silicon with a degree of 3 nm in the microcrystalline silicon layer The conversion characteristic curve of the thin film transistor. Lines 406 and 460 represent the conversion characteristic curve of the polycrystalline silicon thin film transistor with a degree of 6nm. The lines 4 0 9 and 4 9 0 represent the degree of the microcrystalline silicon layer is 9. The conversion characteristic curve of the polycrystalline silicon thin film transistor of nm. Lines 412 and 421 represent the conversion characteristic curve of the polycrystalline stone thin film transistor with the degree of the microcrystalline treasure layer of 12 nm. As shown in Figure 4, the size of the line paper is applicable to the Chinese National Standard (CNS) Α4 specification (21 〇X 297 mm) ---- ^ ---- 一 装 ------ 定- ---- We- (please read the notes on the back before filling this page) A7 ________B7 printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs V. Invention description ((ί) 403 and 430 are the best conversion characteristic curves, However, lines 41 and 410 are the worst conversion characteristic curves. In addition, the horizontal axis of Figure 4 represents the current between the source and the drain, and the vertical axis represents the voltage between the gate and the source. The unit of the horizontal axis is ampere (A), and the unit of the vertical axis is volts. The energy of the tempering laser can be adjusted, so XeCI lasers with different energy density can be used for thin films with different thicknesses of microcrystalline silicon. The crystal rice is tempered to form polycrystalline silicon thin film transistors. There are four kinds of laser energy density, which are 217, 229, 238 and 264mJ / cm2. And the mobility of each specific data is made up of 9 identical The average value of the movement rate of the components of the experiment is shown in Figure 5. Figure 5 shows the different tempering mines by the movement rate. The energy density is a graph of thin-film transistors with different microcrystalline silicon layer degrees, in which the microcrystalline silicon layer degrees are divided into four types of 3nm, 6nm, 9nm and I2nm. In the fifth figure, line 5 1, 502, 503, and 504 represent the curves of the microcrystalline silicon layers with 3nm, 6nm, 9nm, and 12nm respectively. Obviously, no matter how much the energy of the tempering laser is set, the mobility of all thin-film transistors is based on The transistor of the 3nm microcrystalline stone evening layer has the maximum mobility. The unit of the horizontal axis in Figure 5 is mJ / cm2, and the unit of the vertical axis is cm2 / vs. After the process described in the first embodiment above After the step process, the cross-sectional view of the channel layer of the transistor is shown in Figure 6. In this case, the polycrystalline stone is 602 and the insulating layer 601 is almost the same as in Figure 2 only ^ in Figure 2 Amorphous silicon is replaced by microcrystalline silicon 603 in figure 6, and the paper size is applicable to China National Standard (CNS) Α4 specification (210 \ 297 public) (please read the precautions on the back before filling this page) -Install_

1T A7 B7 5. Description of the invention (丨 6) The range of polysilicon is larger than that in Figure 2, which is why the thin-film transistors made by the present invention have better electrical properties. The development of the Ming Garden is only for the purpose of reciting the Shang Ming of the SFO, and the implementation of the decoration of the clam or the modification of the effect, etc., by the issuing of the copy. After the end of the circumstance, the Fanshenli Mastery should not be equal to its other limitations. It is used for demonstrating the purpose of revealing the non-exchange and expressly requesting the package »^ 1 (please read the precautions on the back before filling in This page) Pack-

、 1T Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 17 This paper standard is applicable to China National Standard (CNS) Α4 specification (210X297mm)

Claims (1)

A8 B8 C8 D8 printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs VI. Patent application range 1 ~ ^ Patent application park: 1. A method of forming transistors, which is used for the production of components. The method includes at least: forming A conductive layer on the base layer; forming a dielectric layer on the conductive layer and the base layer; forming a first layer on the dielectric layer; forming a second layer on the first layer; previous Patterning a photoresist layer on the second layer; defining a plurality of heavily doped regions on the first layer and the second layer; heating the first layer and the second layer to perform tempering (An nealing) step, so the first layer and the second layer form a polycrystalline silicon (polycrystalline silicon) layer; etching part of the polycrystalline silicon layer to form a channel region (channel region); this paper scale is applicable to Chinese national standards ( CNS) A4 specification (210X297mm) J (Binding "I (Please read the precautions on the back before filling out this page) The scope of the patent application defines the drain and source regions in the polysilicon layer; (please read the back first Please pay attention to this page and then fill in this page) forming a drain electrode and a source electrode of the semiconductor device; and forming a passivation layer on the drain electrode, the source electrode, the channel region and the dielectric layer上 9 2_ As in the method of applying for patent patent garden item 1, where the above-mentioned conductive layer contains at least a metal θ 3 · As in the method of applying for patent patent garden item 2, wherein the above-mentioned metal is chromium (Cr Bu 4. As applied The method of item 1 of the patent law circle, wherein the above dielectric layer contains at least amorphous silicon oxide (hydrogenated amorphous silicon oxide: a-SiOx: H>. 5) The method as claimed in item 4 of the patent scope, wherein the above The dielectric layer is formed by plasma enhanced chemical vapor deposition (PECVD). Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 6. Such as the method of applying for patent patent item 1, where the above The first layer contains at least microcrystalline sHicori (microcrystalline sHicori: μο-Si). The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 312029 A8 B8 C8 D8 6. Scope of patent application 7. As in the method of applying for patent garden item 6, the above-mentioned first layer is formed by the PECVD method. 8. As in the application of the patent patent garden item 6, where the above-mentioned item The thickness of one layer is about 3 ~ 6 nm. 9. The method as claimed in the second item of the patent scope, wherein the above-mentioned second layer contains at least amorphous hydrogen (a-Si: H) 〇1〇_ as the method of applying for the patent item No. 9 , Where the above-mentioned second layer is formed by the PECVD method. 11_ According to the method of patent application No.1, when the base layer is a light-transmissive substance, the above photoresist pattern layer may be formed by back exposure or front exposure. 12_The method of item ㈣㈣㈣ Item 'where the above-mentioned multiple heavily doped regions are formed by ion implantation e 1 3. The method of item 1 of the patent application garden, where ^ Xing Y is obsessed The annealing method for the first layer and the second layer is laser annealing. 1 4 _For example, the method of applying for the 13th item of the Patent Fan Garden, and the laser return of the fan in the middle m /, T is made by xeci laser with an energy of about 21 7 ~ 264mJ / cm2 ----- --- f outfit ------ order ------- M I (please read the notes on the back before filling this page) Printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 6. The scope of patent application 1 5. For example, the method of applying for the first item of the patent garden "where the source and the drain mentioned above contain metal Θ 16 · ~~ a method of forming polysilicon, which is used in the semiconductor device manufacturing process, the The method at least includes: forming a conductive layer on a base layer, the conductive layer at least including metal; forming a dielectric layer on the conductive layer and the base layer; forming a first layer on the dielectric layer, wherein the above The first layer includes at least microcrystalline silicon (microcrystalline silicon: μο-si); forming a second layer on the first layer, wherein the second layer includes at least amorphous silicon oxyhydrogen (hydrogenated amorphuous silicon: a- Si: H); the previous patterned photoresist layer is on this second layer; printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling in this page). Define multiple heavy doping (heavily doped) area on the first layer and the second layer; heating the first layer and the second layer to perform annealing (annealing) This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 %) 312029 A8 B8 C8 D8 々, the scope of patent application ~~ '~ steps, the first layer and the second layer form a polycrystalline silicon (polycrystalline silicon) layer; (please read the notes on the back before filling this page ) The rest of the polycrystalline hair layer to form a channel region (channel region); defining the drain and source regions on the polysilicon layer; forming a drain electrode and a source electrode of the semiconductor device; and A passivation is formed on the drain electrode, the source electrode, the channel region and the dielectric layer. 17. The square enamel of patent application No. 16 of the patent application, wherein the above dielectric layer contains at least amorphous silicon oxide (hydrogenated amorphous silicon oxide: a-Si〇x: H) 〇1 8. If the patent application The method of item 17, wherein the above-mentioned amorphous silicon oxide (a-SiOx: H) is formed by the PECVD method. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 19. The method as claimed in item 16, in which the above microcrystalline silicon (pc-Si) is produced by PECVD at a temperature of approximately 260 ~ 400 . 〇Formed under the environment of 9 20. The method as described in item 16 of the patent application scope, in which the above-mentioned amorphous stone evening hydrogen paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) Central Bureau of Standards of the Ministry of Economic Affairs Printed by staff consumer cooperatives A8 B8 C8 ---_____ D8 VI. Scope of patent application " 一 '~ (amorphoUSSiiicon: a_Si: H) is formed by pECVD method under the temperature of about 260 ~ 400 ° C of. 21. The method as claimed in item 16 of the patent application park, wherein the thickness of the aforementioned microcrystalline silicon hydrogen (Kc_Si) is approximately between 3 and 12 nm. 22. The method as claimed in item 20 of the patent application system, wherein The thickness of aSi: H is about 60nm. 23. According to the method of Patent Application No. 16, when the base layer is a light-transmissive substance (such as glass), the above photoresist pattern layer can be formed by back exposure or front exposure Form c 24. The method as claimed in item 16 of the patent application, wherein the above-mentioned multiple heavily doped regions are formed by ion implantation. 9 25. The method as claimed in item 16 of the patent application, where The annealing method of the first layer and the second layer of the fan is laser tempering. 26. The method of claim 25 of the patent application park, where the laser flashback is performed by XeCI laser with an energy of about 217 ~ 264mJ / cm2. 27. The method of claim 16 of the patent application , The source of the fan and the drain contain metal θ (please read the notes on the back before filling this page) 装 、 τ 23