TW587874U - Clock generating circuit, serial/parallel converting device, parallel/serial converting device and semiconductor device - Google Patents
Clock generating circuit, serial/parallel converting device, parallel/serial converting device and semiconductor deviceInfo
- Publication number
- TW587874U TW587874U TW091221351U TW91221351U TW587874U TW 587874 U TW587874 U TW 587874U TW 091221351 U TW091221351 U TW 091221351U TW 91221351 U TW91221351 U TW 91221351U TW 587874 U TW587874 U TW 587874U
- Authority
- TW
- Taiwan
- Prior art keywords
- serial
- parallel
- converting device
- generating circuit
- clock generating
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/06—Clock generators producing several clock signals
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M9/00—Parallel/series conversion or vice versa
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11964799 | 1999-04-27 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW587874U true TW587874U (en) | 2004-05-11 |
Family
ID=14766635
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW091221351U TW587874U (en) | 1999-04-27 | 2000-04-27 | Clock generating circuit, serial/parallel converting device, parallel/serial converting device and semiconductor device |
Country Status (6)
Country | Link |
---|---|
US (1) | US6414528B1 (zh) |
JP (1) | JP4029568B2 (zh) |
KR (1) | KR100510332B1 (zh) |
CN (1) | CN1156975C (zh) |
TW (1) | TW587874U (zh) |
WO (1) | WO2000065717A1 (zh) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7233638B2 (en) * | 2001-01-31 | 2007-06-19 | Rohm Co., Ltd. | Sampling clock generator circuit and data receiver using the same |
JP4663896B2 (ja) * | 2001-03-30 | 2011-04-06 | 株式会社日立製作所 | 液晶表示装置 |
US6657502B2 (en) * | 2001-10-01 | 2003-12-02 | Motorola, Inc. | Multiphase voltage controlled oscillator |
FR2841406A1 (fr) * | 2002-06-25 | 2003-12-26 | St Microelectronics Sa | Circuit dephaseur variable,interpolateur de phase l'incorporant, et synthetiseur de frequence numerique incorpoant un tel interpolateur |
AU2003246998A1 (en) * | 2002-07-31 | 2004-02-23 | Koninklijke Philips Electronics N.V. | Method and devic the for setting the slice level in a binary signal |
JP2005078523A (ja) * | 2003-09-02 | 2005-03-24 | Matsushita Electric Ind Co Ltd | シリアル転送装置 |
US7230495B2 (en) * | 2004-04-28 | 2007-06-12 | Micron Technology, Inc. | Phase-locked loop circuits with reduced lock time |
CN1797954B (zh) * | 2004-12-22 | 2010-09-08 | 瑞昱半导体股份有限公司 | 时钟信号产生装置及方法 |
KR100972494B1 (ko) * | 2005-04-28 | 2010-07-26 | 쟈인 에레쿠토로닉스 가부시키가이샤 | 위상 동기 루프 회로 |
JP2007096903A (ja) * | 2005-09-29 | 2007-04-12 | Rohm Co Ltd | パラレルシリアル変換回路およびそれを用いた電子機器 |
US9237000B2 (en) * | 2006-06-19 | 2016-01-12 | Intel Corporation | Transceiver clock architecture with transmit PLL and receive slave delay lines |
TWI348671B (en) * | 2006-08-16 | 2011-09-11 | Au Optronics Corp | A circuit for driving an lcd panel and a method thereof |
KR100886354B1 (ko) * | 2007-05-17 | 2009-03-03 | 삼성전자주식회사 | 다중 위상 클럭신호를 사용하는 통신 시스템 및 통신 방법 |
WO2010035309A1 (ja) * | 2008-09-24 | 2010-04-01 | 株式会社アドバンテスト | 遅延回路およびそれを用いたタイミング発生器および試験装置 |
CN102422610A (zh) * | 2009-05-13 | 2012-04-18 | 松下电器产业株式会社 | 混合型数据发送电路 |
JP2011160369A (ja) * | 2010-02-04 | 2011-08-18 | Sony Corp | 電子回路、電子機器、デジタル信号処理方法 |
CN102064927B (zh) * | 2010-09-21 | 2013-11-13 | 四川和芯微电子股份有限公司 | 时序纠错系统及方法 |
US9814106B2 (en) * | 2013-10-30 | 2017-11-07 | Apple Inc. | Backlight driver chip incorporating a phase lock loop (PLL) with programmable offset/delay and seamless operation |
KR101603093B1 (ko) * | 2014-02-03 | 2016-03-14 | 주식회사 파이칩스 | 스프레드 스펙트럼 클럭 생성기 |
KR101543704B1 (ko) * | 2014-12-10 | 2015-08-12 | 연세대학교 산학협력단 | 직렬 변환기 및 그를 포함한 데이터 송신 장치 |
CN110601698B (zh) * | 2018-06-13 | 2022-09-20 | 瑞昱半导体股份有限公司 | 串行器/解串器实体层电路 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4494021A (en) * | 1982-08-30 | 1985-01-15 | Xerox Corporation | Self-calibrated clock and timing signal generator for MOS/VLSI circuitry |
JPS60101799A (ja) * | 1983-11-08 | 1985-06-05 | Sony Corp | 2段階サンプルホ−ルド回路 |
US4922141A (en) | 1986-10-07 | 1990-05-01 | Western Digital Corporation | Phase-locked loop delay line |
JP3077815B2 (ja) * | 1990-07-13 | 2000-08-21 | ソニー株式会社 | パルス信号発生回路 |
JP3561792B2 (ja) | 1995-09-06 | 2004-09-02 | 株式会社ルネサステクノロジ | クロック発生回路 |
US5614868A (en) * | 1995-10-24 | 1997-03-25 | Vlsi Technology, Inc. | Phase locked loop having voltage controlled oscillator utilizing combinational logic |
US5786732A (en) * | 1995-10-24 | 1998-07-28 | Vlsi Technology, Inc. | Phase locked loop circuitry including a multiple frequency output voltage controlled oscillator circuit |
US6046994A (en) * | 1997-01-16 | 2000-04-04 | Rockwell International Corp. | Modular switching system |
JP3282792B2 (ja) * | 1997-08-27 | 2002-05-20 | 株式会社リコー | 電圧制御発振器及びこれを用いた半導体集積回路及び位相同期ループ回路及びこれを用いた中間周波数処理回路 |
US6198415B1 (en) * | 1998-08-04 | 2001-03-06 | Matsushita Electric Industrial Co., Ltd. | Serial-to-parallel converter |
-
2000
- 2000-04-27 CN CNB008007101A patent/CN1156975C/zh not_active Expired - Fee Related
- 2000-04-27 WO PCT/JP2000/002769 patent/WO2000065717A1/ja not_active Application Discontinuation
- 2000-04-27 TW TW091221351U patent/TW587874U/zh not_active IP Right Cessation
- 2000-04-27 KR KR10-2000-7014870A patent/KR100510332B1/ko not_active IP Right Cessation
- 2000-04-27 JP JP2000614557A patent/JP4029568B2/ja not_active Expired - Fee Related
- 2000-04-27 US US09/720,429 patent/US6414528B1/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
WO2000065717A1 (en) | 2000-11-02 |
US6414528B1 (en) | 2002-07-02 |
KR20010053231A (ko) | 2001-06-25 |
CN1156975C (zh) | 2004-07-07 |
CN1302477A (zh) | 2001-07-04 |
KR100510332B1 (ko) | 2005-08-25 |
JP4029568B2 (ja) | 2008-01-09 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4K | Annulment or lapse of a utility model due to non-payment of fees |