TW556273B - Method for establishing ultra-thin gate insulator using anneal in ammonia - Google Patents

Method for establishing ultra-thin gate insulator using anneal in ammonia Download PDF

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TW556273B
TW556273B TW089125288A TW89125288A TW556273B TW 556273 B TW556273 B TW 556273B TW 089125288 A TW089125288 A TW 089125288A TW 89125288 A TW89125288 A TW 89125288A TW 556273 B TW556273 B TW 556273B
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oxide
substrate
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thickness
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Effiong Ibok
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Advanced Micro Devices Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Description

556273 玖、發明說明： 此申凊案請求申請於】999年】2月7曰 60/〗69,540號之利益 緣體之方法” 美國臨時申請案第 標題為“使用於氨中退火而建立超薄間絕 [發明所屬之技術領域] 本發明係關於—種半導體裝置之製造，尤其在於建立場效電 晶體(FET)閘絕緣體。 [先前技術] 半導體晶片或晶圓應用於許多地方，包括積體電路，手持電 腦裝置之快閃記憶體’無線電話，以及數位相機。不論其應用為 何白』望方'使半導體晶片上單位面積所具有的電路及記憶體單 元越多越好。如此—來，利用半導體晶片之裝置，其尺寸，重量， 以及能量耗損均可有利地減至最小，同時可增進裝置之記憶體容 量及運算能力。 很谷易地可以察知將積體電路上之各種元件個別加以絕緣是 很重要的，以確保電路正常運作。例如於電晶體，閘極形成於半 導肢基板上’並用—非常薄之電介質層將其與基板絕緣。此層稱 為“閘氧化物”或“閘絕緣體，’。隨著半導體裝置尺寸的減小， 閘絕緣體層之厚度亦同樣減少。 如上述，當其尺寸很小時，閘絕緣體可能因太薄，使得基板 及鄰近多晶料結電極的次氧化物，微量的侵㈣閘絕緣層，而 減低閘、{緣層之絕緣能力。此造成嚴重問題，因於此情形下，即 91691 5 556273 使基板上非常微小的缺陷，也會造成經由閘絕緣體之電子洩漏途 徑，導致電晶體的嚴重故障。 為防止此問題發生，一些別於常見閘氧化物之材料，如高介 電常數電介質材料，包括可做成非常薄，但仍保留良好絕緣特性 的氮化物及氧氮化物，已被提出。遺憾地，這些材料被認為會降 低電晶體性能。尤其是氮化物被認為不合適，因其會促進不需要 的經閘絕緣層電子洩漏。 此外，當閘絕緣層變得非常薄時，例如於19埃（19 A )等級 時，裝置整合變的高度複雜。具體地說，必須蝕刻部分的多晶矽 電極向下至基板，但須停止於非常薄例如19埃（19A)的閘絕緣層， 而不蝕刻至底下的基板，是有困難的。因此，本發明體認需提供 一個可作成非常薄的閘絕緣層，以適合於非常小尺寸之電晶體。 但同時維持足夠的絕緣特性以適當地作為閘絕緣體，且須維持足 夠厚度以利裝置整合，且相對於氧化物絕緣體性能亦無降低。 [發明内容] 一種用於製造半導體裝置的方法，包括準備一個半導體基 板，於基板上建立一層氧化物基底薄層。接著將基板退火，理想 於溫度達攝氏1100度（l】〇(TC)之氨内，之後，場效電晶體（FET) 閘即形成於部份薄層上。較佳之基底薄層限定厚度不超過24埃（24 A )。然而，退火後基底薄層之電阻降至和常見氧化物薄層厚度 只有20埃（20 A )時相同。此薄層之電阻有利地減少，但其仍具 6 91691 556273 足夠厚度以防止不希望的穿隧效應，而能於相對較高之驅動電流 及電容下，具相對而言較低之備用電流。 本發明之其他特性將揭示於標題為“實施方式”的段落中。 [實施方式] 本發明之原理同樣適用於各種半導體及積體電路設計及製作 方法，包含，但並不限於非揮發性記憶體裝置之製造。所有此類 之實行均於本發明原理預期之内。 首先參照第1圖及第2圖，於第1圖之區塊10，準備一個半 導體基板12(第2圖）如矽，接著於區塊14中，依照此項技藝所 知之氧化物薄層形成原理，生成一層薄氧化物基底薄層16於基 板12上，並與基板12直接接觸。基底薄層16之厚度“t”不可 超過24埃（24 A)。 移至第1圖之區塊18，並參照第3圖，基板12及薄層16 在溫度達攝氏1100度（ll〇〇°C)之氨（NH3)中於原處退火，以建立 氮濃縮於基底薄層16。氮以點19表示。依照本原理，退火後基 底薄層]6之電阻降至和常見氧化物薄層厚度只有20埃（20 A )時 相同。薄層16之電阻有利地減少，但其仍具足夠厚度以防止不 希望的穿隧效應，而能於相對較高之驅動電流及電容下，具相對 而言較低之備用電流。 接著，於第2圖區塊20，並參照第4圖，以多晶矽為材料之 場效電晶體（FET)層疊28，依照此技藝所知的場效電晶體（FET)閘 7 91691修正本 556273 場效電晶體(FET)層疊28，依照此技藝所知的場效電晶體（FET)閘 層疊沉積及配線原理，形成於薄層16上。於形成及配線完場效 電晶體(FET)層疊28後，再使用常見原理形成場效電晶體(FET) 源極及汲極36，38，製程便完成。同時接點，交互連結頭，以及 場效電晶體(FET)和場效電晶體(FET)間的絕緣，亦依常見方式製 作。 經由上述之揭示可知，基底薄層之氨退火減少了基底薄層之 等量電厚度。換言之，對於一個具足夠厚度，符合上述結構考量 之薄層，例如，24埃（24 A)厚，退火後，有利地，薄層之電力 表現如同只有20埃（20 Λ )厚度之薄層。此舉有利地減低其後之 電子穿隧效應，使得高驅動電流及電容下，若和未於氨中退火的 薄層比較，有較低之備用電流。 本發明將具體地藉由某些較佳實施例之特色而加以表現及描 述。然而，顯而易見地，對於此項技藝之一般技術者而言，各種 於外形及細部之變動及修正均可實行，只要其不背離下列本發明 所提出之申請專利範圍的精神及範疇。尤其，使用交替層沉積或 製造方法；蝕刻技術；光罩方法；平版印刷方法；鈍化及氮化技 術；以及其餘半導體設計，或是於此揭示技術之應用於其餘電子 元件等，均屬於本發明原理預期之内。即使在沒有於此處無特別 揭示的構件情形下，此處所揭示之發明亦可實行。除非於申請專 利範圍裡特別聲明，申請專利範圍裡所使用之單數形式並不表示 8 91691： [固式之簡單說明] 第1圖為製造程序流程圖； 第2圖為在基板形成基底薄層後之裝置側面圖； 第3圖為基底薄層退火後之裝置側面圖；及 9] 691修正本 置側面圖。 [元件符號說明] 10 、 14 、 18 、 20 區塊 12 基板 16 氧化物基底薄層 19 氮 28 場效電晶體叠層 36 源極 38 汲極 9

Claims (1)

  1. 556273 拾、申請專利範圍·· 1. 一種用於製造半導體裝置之方法，該半導體裝置具有超薄絕 緣體用於防止穿隧效應，該方法包括下列步驟： 準備一個半導體基板； 於該基板上建立-層氧化物基底薄層，該氧化物基底薄 層具有—氧化物基底薄層厚度，其中建立該氧化物基底薄層 之邊步驟包括該氧化物基底薄層厚度係在不超過2 A)之範圍内； = 於氨(顺3)環境中於溫度上料咖t，將該基板上之 該氧化物基底薄層退火，由此形成—層氮化之氧化物薄層， 其中該退火步驟減少該氮化之氧化物薄層之等效電厚度 至20埃， X 该氮化之氧化物薄層具有相關於該氧化物基底薄層厚度 之氮化之氧化物薄層厚度，以促進防止該穿隨效應，由此對 於較高驅動電流及電容下獲得較低之備用電流，用於促進作 為閘絕緣體功能，和用於促進該裝置之積體化， 一讀化之氧化物薄層具有與較之該氧化物基底薄層厚度 為薄之氧化物薄層的電絕緣性相等的電絕綠性，以及 。亥超薄絕緣體包括該氮化之氧化物薄層；以及 ^於該氫化之氧化物薄層之至少—部分上形成至少一個以 多晶石夕為基底之場效電晶體（FE丁)間。 如申請專利範圍第】項之方法，其中該退火步驟降低其後之 9]69】 )0 2. 556273 電子穿随通過該氮化之氧化物薄層，由此使得·㈣_ 電流及電容下獲得較之該氧化物基㈣層為低之制電流。 3·-種用於製造半導體裝置之方法，該半導體裝置具有$超薄絕 緣體用於防止穿隧效應，該方法包括下列步驟·· 準備一個半導體基板； 於該基板上建立-層氧化物基底薄層，該氧化物基底薄 層具有一氧化物基底薄層厚度，· 於氨卿環境中於溫度增響C，將該基板上之 該氧化物基底薄層退火，由此形成-層氮化之氧化物薄層， 該氮化之氧化㈣層具有相詩該氧㈣基料層厚度 化之氧化物薄層厚度， ^ 一該氮化之氧化物薄層具有與較之該氧化物基底薄層厚度 為薄之氧化物薄層的電絕緣性相等的電絕緣性，以及 該超薄絕緣體包括該氮化之氧化物薄層；以及 個以 户曰於該氮化之氧化物薄層之至少一部分上形成至少 多晶石夕為基底之場效電晶體（FET)間， 其中建立氧化物基底薄層之該步驟包括該氧化物薄層厚 度係在不超過24埃（$24幻之範圍内， 度，其中該退火步驟減少該氮化之氧化物薄層之等效電厚 其 从火步称減少該氮化之氧化物薄層之等效電厚度 Π 91691* 556273 至20埃，以及 其中該退火步驟減少其後電子穿隧通過該氮化之氧化物 薄層，由此對於較高驅動電流及電容下獲得較該氧化物基底 薄層為低之備用電流。 12 91691
TW089125288A 1999-12-07 2000-11-29 Method for establishing ultra-thin gate insulator using anneal in ammonia TW556273B (en)

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CN1423832A (zh) 2003-06-11
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