US20010049186A1 - Method for establishing ultra-thin gate insulator using anneal in ammonia - Google Patents

Method for establishing ultra-thin gate insulator using anneal in ammonia Download PDF

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Publication number
US20010049186A1
US20010049186A1 US09479506 US47950600A US2001049186A1 US 20010049186 A1 US20010049186 A1 US 20010049186A1 US 09479506 US09479506 US 09479506 US 47950600 A US47950600 A US 47950600A US 2001049186 A1 US2001049186 A1 US 2001049186A1
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method
substrate
ammonia
base film
film
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US6444555B2 (en )
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Effiong Ibok
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GlobalFoundries Inc
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Advanced Micro Devices Inc
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/28273Making conductor-insulator-conductor-insulator-semiconductor electrodes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/518Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Abstract

A method for fabricating a semiconductor device including a silicon substrate includes forming a thin Oxide base film on a substrate, and then annealing the substrate in ammonia. FET gates are then conventionally formed over the gate insulator. The resultant gate insulator is electrically insulative without degrading performance with respect to a conventional gate oxide insulator.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application claims the benefit of U.S. Provisional Application No. 60/169,540, filed on Dec. 7, 1999 and entitled “METHOD FOR ESTABLISHING ULTRA-THIN GATE INSULATOR USING ANNEAL IN AMMONIA”.[0001]
  • TECHNICAL FIELD
  • The present invention relates to the fabrication of semiconductor devices, and more particularly to establishing field effect transistor (FET) gate insulators. [0002]
  • BACKGROUND OF THE INVENTION
  • Semiconductor chips or wafers are used in many applications, including as integrated circuits and as flash memory for hand held computing devices, wireless telephones, and digital cameras. Regardless of the application, it is desirable that a semiconductor chip hold as many circuits or memory cells as possible per unit area. In this way, the size, weight, and energy consumption of devices that use semiconductor chips advantageously is minimized, while nevertheless improving the memory capacity and computing power of the devices. [0003]
  • It can readily be appreciated that it is important to electrically isolate various components of an integrated circuit from each other, to ensure proper circuit operation. As one example, in a transistor, a gate is formed on a semiconductor substrate, with the gate being insulated from the substrate by a very thin dielectric layer, referred to as the “gate oxide” or “gate insulator”. As the scale of semiconductor devices decreases, the thickness of the gate insulator layer likewise decreases. [0004]
  • As recognized herein, at very small scales, the gate insulator can be become so thin that otherwise relatively small encroachments into the gate insulator layer by sub-oxides from the substrate and from adjacent polysilicon connector electrodes can reduce the insulating ability of the gate insulator layer. This poses severe problems because under these circumstances, even very minor defects in the substrate can create electron leakage paths through the gate insulator, leading to catastrophic failure of the transistor. [0005]
  • To circumvent this problem, alternatives to traditional gate oxide materials, such as high-k dielectric materials including nitrides and oxynitrides that can be made very thin and still retain good insulating properties, have been proposed. Unfortunately, it is thought that these materials can degrade the performance of the transistor. Nitride, in particular, has been considered undesirable because it promotes unwanted leakage of electrons through the gate insulator layer. [0006]
  • Furthermore, as the gate insulator layer becomes very thin, e.g., on the order of nineteen Angstroms (19 Å), device integration becomes highly complicated. Specifically, it is necessary to etch portions of the polysilicon electrodes down to the substrate, but stopping the etch on a very thin, e.g., 19 Å gate insulator layer without pitting the substrate underneath becomes problematic. Accordingly, the present invention recognizes that it is desirable to provide a gate insulator layer that can be made very thin as appropriate for very small-scale transistors while retaining sufficient electrical insulation properties to adequately function as a gate insulator, and while retaining sufficient physical thickness to facilitate device integration, without degrading performance vis-a-vis oxide insulators. [0007]
  • BRIEF SUMMARY OF THE INVENTION
  • A method for making a semiconductor device includes providing a semiconductor substrate, and establishing an oxide base film on the substrate. The substrate is annealed, preferably in ammonia at temperatures up to eleven hundred degrees Celsius (1100° C.), after which FET gates are formed on portions of the film. The preferred base film defines a thickness of no more than twenty four Angstroms (24 Å). However, after annealing the electrical resistance of the base film is reduced to that of a conventional oxide film having a thickness of only 20 Å, such that the electrical resistance of the film is advantageously reduced while the physical thickness remains sufficiently thick to inhibit undesired tunneling, resulting in a relatively lower standby current for a relatively higher drive current and capacitance. [0008]
  • Other features of the present invention are disclosed or apparent in the section entitled “DETAILED DESCRIPTION OF THE INVENTION”. [0009]
  • BRIEF DESCRIPTION OF DRAWINGS
  • For understanding of the present invention, reference is made to the accompanying drawing in the following DETAILED DESCRIPTION OF THE INVENTION. In the drawings: [0010]
  • FIG. 1 is a flow chart of the manufacturing process; [0011]
  • FIG. 2 is a side view of the device after forming the base film on the substrate; [0012]
  • FIG. 3 is a side view of the device after annealing the base film; and [0013]
  • FIG. 4 is a side view of the device after forming the FET gate stacks on the nitride film.[0014]
  • DETAILED DESCRIPTION OF THE INVENTION
  • The principles of the present invention are equally applicable to a wide range of semiconductor and integrated circuit design and manufacture regimens, including but not necessarily limited to the production of non-volatile memory devices. All such implementations are specifically contemplated by the principles of the present intention. [0015]
  • Referring initially to FIGS. 1 and 2, at block [0016] 10 in FIG. 1 a semiconductor substrate 12 (FIG. 2) such as Silicon is provided, and then at block 14 a thin Oxide base film 16 is grown on the substrate 12 in accordance with oxide film formation principles known in the art, in direct contact with the substrate 12. The thickness “t” of the base film 16 is no more than twenty four Angstroms (24 Å).
  • Moving to block [0017] 18 of FIG. 1 and referring to FIG. 3, the substrate 12 with film 16 is annealed in situ in ammonia (NH3) at a temperature of up to eleven hundred degrees Celsius (1100° C.) to establish a Nitrogen concentration in the base film 16. The Nitrogen is represented by the dots 19. In accordance with present principles, after annealing the electrical resistance of the base film 16 is reduced to that of a conventional oxide film having a thickness of only 20 Å, such that the electrical resistance of the film 16 advantageously is reduced while the physical thickness remains sufficiently thick to inhibit undesired tunneling, resulting in a relatively lower standby current for a relatively higher drive current and capacitance.
  • Next, at block [0018] 20 in FIG. 2 and referring now to FIG. 4, a polysilicon-based field effect transistor (FET) stack 28 is formed on the film 16 in accordance with FET gate stack deposition and patterning principles known in the art. After forming and patterning the FET stacks 28, the process is completed by forming FET sources and drains 36, 38 using conventional principles, and contacts, interconnects, and FET to FET insulation are likewise conventionally undertaken.
  • With the above disclosure in mind, the ammonia anneal of the base film reduces the equivalent electrical thickness of the base film. In other words, for a film that is sufficiently thick for the above-mentioned structural considerations, e.g., 24 Å thick, after annealing the film advantageously behaves electrically like a film that is only 20 Å thick. This in turn advantageously decreases subsequent electron tunneling resulting in a lower standby current for higher drive current and capacitance, compared to a film not annealed in ammonia. [0019]
  • The present invention has been particularly shown and described with respect to certain preferred embodiments of features thereof. However, it should be readily apparent to those of ordinary skill in the art that various changes and modifications in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims. In particular, the use of: alternate layer deposition or forming methodologies; etching technologies; masking methods; lithographic methods, passivation and nitridization techniques; as well as alternative semiconductor designs, as well as the application of the technology disclosed herein to alternate electronic components are all contemplated by the principles of the present invention. The invention disclosed herein may be practiced without any element which is not specifically disclosed herein. The use of the singular in the claims does not mean “only one”, but rather “one or more”, unless otherwise stated in the claims. [0020]

Claims (6)

    What is claimed is:
  1. 1. A method for making a semiconductor device, comprising:
    providing a semiconductor substrate;
    establishing an oxide base film on the substrate; then
    annealing the substrate in ammonia; then
    forming FET gates on portions of the film.
  2. 2. The method of
    claim 1
    , wherein the base film defines a thickness of no more than twenty four Angstroms (24 Å).
  3. 3. The method of
    claim 2
    , wherein the electrical resistance of the base film is reduced as a result of the annealing act.
  4. 4. The method of
    claim 1
    , wherein the annealing act reduces the electrical thickness of the oxide base film.
  5. 5. The method of
    claim 1
    , wherein the annealing act is undertaken at temperatures up to eleven hundred degrees Celsius (1100° C.).
  6. 6. The method of
    claim 4
    , wherein the annealing act decreases subsequent electron tunneling resulting in a lower standby current for higher drive current and capacitance, compared to a film not annealed in ammonia.
US09479506 1999-12-07 2000-01-07 Method for establishing ultra-thin gate insulator using anneal in ammonia Active 2020-03-08 US6444555B2 (en)

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US16954099 true 1999-12-07 1999-12-07
US09479506 US6444555B2 (en) 1999-12-07 2000-01-07 Method for establishing ultra-thin gate insulator using anneal in ammonia

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US09479506 US6444555B2 (en) 1999-12-07 2000-01-07 Method for establishing ultra-thin gate insulator using anneal in ammonia
TW89125288A TW556273B (en) 1999-12-07 2000-11-29 Method for establishing ultra-thin gate insulator using anneal in ammonia
CN 00816802 CN1423832A (en) 1999-12-07 2000-12-05 Method for establishing ultra-thin gate insulator using anneal in ammonia
EP20000983955 EP1236225A1 (en) 1999-12-07 2000-12-05 Method for establishing ultra-thin gate insulator using anneal in ammonia
PCT/US2000/033071 WO2001043177A1 (en) 1999-12-07 2000-12-05 Method for establishing ultra-thin gate insulator using anneal in ammonia
JP2001543768A JP2003516633A (en) 1999-12-07 2000-12-05 Method using the annealing in ammonia establishing the ultra-thin gate insulator

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US6444555B2 US6444555B2 (en) 2002-09-03

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Cited By (10)

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US20050130448A1 (en) * 2003-12-15 2005-06-16 Applied Materials, Inc. Method of forming a silicon oxynitride layer
US20060178018A1 (en) * 2003-03-07 2006-08-10 Applied Materials, Inc. Silicon oxynitride gate dielectric formation using multiple annealing steps
US20080230814A1 (en) * 2007-03-20 2008-09-25 Taiwan Semiconductor Manufacturing Co., Ltd. Methods for fabricating a semiconductor device
US20090035928A1 (en) * 2007-07-30 2009-02-05 Hegde Rama I Method of processing a high-k dielectric for cet scaling
US7645710B2 (en) 2006-03-09 2010-01-12 Applied Materials, Inc. Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system
US7678710B2 (en) 2006-03-09 2010-03-16 Applied Materials, Inc. Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system
US7837838B2 (en) 2006-03-09 2010-11-23 Applied Materials, Inc. Method of fabricating a high dielectric constant transistor gate using a low energy plasma apparatus
US7902018B2 (en) 2006-09-26 2011-03-08 Applied Materials, Inc. Fluorine plasma treatment of high-k gate stack for defect passivation
US7964514B2 (en) 2006-03-02 2011-06-21 Applied Materials, Inc. Multiple nitrogen plasma treatments for thin SiON dielectrics
US8119210B2 (en) 2004-05-21 2012-02-21 Applied Materials, Inc. Formation of a silicon oxynitride layer on a high-k dielectric material

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US6921691B1 (en) * 2004-03-18 2005-07-26 Infineon Technologies Ag Transistor with dopant-bearing metal in source and drain
US7592678B2 (en) * 2004-06-17 2009-09-22 Infineon Technologies Ag CMOS transistors with dual high-k gate dielectric and methods of manufacture thereof
US8178902B2 (en) 2004-06-17 2012-05-15 Infineon Technologies Ag CMOS transistor with dual high-k gate dielectric and method of manufacture thereof
US7344934B2 (en) * 2004-12-06 2008-03-18 Infineon Technologies Ag CMOS transistor and method of manufacture thereof
US7381608B2 (en) * 2004-12-07 2008-06-03 Intel Corporation Method for making a semiconductor device with a high-k gate dielectric and a metal gate electrode
US7253050B2 (en) * 2004-12-20 2007-08-07 Infineon Technologies Ag Transistor device and method of manufacture thereof
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US20070052036A1 (en) * 2005-09-02 2007-03-08 Hongfa Luan Transistors and methods of manufacture thereof
US20070052037A1 (en) * 2005-09-02 2007-03-08 Hongfa Luan Semiconductor devices and methods of manufacture thereof
US8188551B2 (en) * 2005-09-30 2012-05-29 Infineon Technologies Ag Semiconductor devices and methods of manufacture thereof
US7462538B2 (en) * 2005-11-15 2008-12-09 Infineon Technologies Ag Methods of manufacturing multiple gate CMOS transistors having different gate dielectric materials
US7495290B2 (en) * 2005-12-14 2009-02-24 Infineon Technologies Ag Semiconductor devices and methods of manufacture thereof
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US7429540B2 (en) 2003-03-07 2008-09-30 Applied Materials, Inc. Silicon oxynitride gate dielectric formation using multiple annealing steps
US20060178018A1 (en) * 2003-03-07 2006-08-10 Applied Materials, Inc. Silicon oxynitride gate dielectric formation using multiple annealing steps
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US7569502B2 (en) * 2003-12-15 2009-08-04 Applied Materials, Inc. Method of forming a silicon oxynitride layer
US20050130448A1 (en) * 2003-12-15 2005-06-16 Applied Materials, Inc. Method of forming a silicon oxynitride layer
US8119210B2 (en) 2004-05-21 2012-02-21 Applied Materials, Inc. Formation of a silicon oxynitride layer on a high-k dielectric material
US7964514B2 (en) 2006-03-02 2011-06-21 Applied Materials, Inc. Multiple nitrogen plasma treatments for thin SiON dielectrics
US7645710B2 (en) 2006-03-09 2010-01-12 Applied Materials, Inc. Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system
US7678710B2 (en) 2006-03-09 2010-03-16 Applied Materials, Inc. Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system
US7837838B2 (en) 2006-03-09 2010-11-23 Applied Materials, Inc. Method of fabricating a high dielectric constant transistor gate using a low energy plasma apparatus
US7902018B2 (en) 2006-09-26 2011-03-08 Applied Materials, Inc. Fluorine plasma treatment of high-k gate stack for defect passivation
US20080230814A1 (en) * 2007-03-20 2008-09-25 Taiwan Semiconductor Manufacturing Co., Ltd. Methods for fabricating a semiconductor device
US7638396B2 (en) 2007-03-20 2009-12-29 Taiwan Semiconductor Manufacturing Co., Ltd. Methods for fabricating a semiconductor device
US20090035928A1 (en) * 2007-07-30 2009-02-05 Hegde Rama I Method of processing a high-k dielectric for cet scaling

Also Published As

Publication number Publication date Type
EP1236225A1 (en) 2002-09-04 application
WO2001043177A1 (en) 2001-06-14 application
JP2003516633A (en) 2003-05-13 application
US6444555B2 (en) 2002-09-03 grant
CN1423832A (en) 2003-06-11 application

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