KR100586540B1 - Method of forming capacitor of semiconductor device - Google Patents

Method of forming capacitor of semiconductor device Download PDF

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KR100586540B1
KR100586540B1 KR1019990067035A KR19990067035A KR100586540B1 KR 100586540 B1 KR100586540 B1 KR 100586540B1 KR 1019990067035 A KR1019990067035 A KR 1019990067035A KR 19990067035 A KR19990067035 A KR 19990067035A KR 100586540 B1 KR100586540 B1 KR 100586540B1
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film
oxide
nitride film
semiconductor device
thin film
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KR1019990067035A
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KR20010059518A (en
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우상호
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment

Abstract

본 발명은 반도체장치의 커패시터 제조방법에 관한 것으로서, 특히 이 방법은 반도체기판에 도전체로 이루어진 하부전극을 형성하고 그 위에 질화막과 산화막이 적층된 유전체박막을 형성하되, 산화막은 질화막 표면을 400℃∼700℃의 온도에서 N2O 또는 NH3 가스 분위기에서 플라즈마로 열처리하여 형성하고, 상기 유전체박막 상부에 도전체로 이루어진 상부전극을 형성한다. 이에 따라, 본 발명은 질화막(N)/산화막(O) 구조의 유전체박막에서 산화막 제조 공정시 저온에서 플라즈마 열공정으로 질화막의 상부를 산화시킴으로써 고온 열산화 공정으로 인한 소자의 전기적 특성 저하를 방지할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device. In particular, the method includes forming a lower electrode made of a conductor on a semiconductor substrate, and forming a dielectric thin film having a nitride film and an oxide film stacked thereon, wherein the oxide film has a surface of the nitride film having a temperature of 400 ° C. It is formed by heat treatment with plasma in a N 2 O or NH 3 gas atmosphere at a temperature of 700 ℃, to form an upper electrode made of a conductor on the dielectric thin film. Accordingly, the present invention prevents the deterioration of the electrical characteristics of the device due to the high temperature thermal oxidation process by oxidizing the upper portion of the nitride film by the plasma thermal process at low temperature during the oxide film manufacturing process in the dielectric thin film of the nitride film (N) / oxide (O) structure. Can be.

Description

반도체장치의 커패시터 제조방법{Method of forming capacitor of semiconductor device} Method of manufacturing capacitor of semiconductor device {Method of forming capacitor of semiconductor device}             

도 1 내지 도 4는 본 발명에 따른 반도체장치의 커패시터 제조방법을 설명하기 위한 공정 순서도.1 to 4 are process flowcharts for explaining a capacitor manufacturing method of a semiconductor device according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

10: 반도체기판의 구조물10: structure of semiconductor substrate

20: 하부 전극20: lower electrode

30: N/O 유전체막30: N / O dielectric film

32: 질화막32: nitride film

34: 산화막34: oxide film

40: 상부전극40: upper electrode

본 발명은 반도체장치의 제조방법에 관한 것으로, 특히 전극들 사이에 내재되는 유전체 막질로서 질화막(nitride)과 실리콘막(silicon)의 복합층을 사용하여 고용량을 달성하는 반도체장치의 커패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a capacitor of a semiconductor device which achieves high capacity by using a composite layer of a nitride film and a silicon film as a dielectric film inherent between electrodes. will be.

현재 반도체장치의 고집적화를 달성하기 위하여 셀 면적의 감소 및 동작 전압의 저전압화에 관한 연구/개발이 활발하게 진행되고 있다. 더구나, 반도체장치의 고집적화가 이루어질수록 커패시터의 면적이 급격하게 감소되지만 기억소자의 동작에 필요한 전하 즉, 단위 면적에 확보되는 정전용량는 증가되어야만 한다. At present, in order to achieve high integration of semiconductor devices, research / development has been actively conducted on reduction of cell area and reduction of operating voltage. In addition, as the integration of semiconductor devices becomes higher, the area of the capacitor is drastically reduced, but the charge necessary for the operation of the memory device, that is, the capacitance secured in the unit area must be increased.

커패시터의 충분한 유전 용량을 확보하기 위해서는 유전막의 박막화, 유효 표면적의 증대 등의 구조적인 연구가 진행되고 있다. 또, 약 3-4 정도의 유전상수(ε)를 갖는 실리콘 산화막(SiO2) 대신에 고유전 물질로서 NO(Nitride-Oxide) 구조 또는 ONO(Oxide-Nitride-Oxide)구조라든지 Ta2O5 또는 BST(BaSrTiO3) 등으로 대체하려는 재료적인 연구도 진행되고 있다. 이러한 고유전체 막질은 커패시터 뿐만이 아니라 플래시 메모리내 게이트전극의 절연막에도 적용이 가능하다.In order to secure a sufficient dielectric capacity of a capacitor, structural studies such as thinning of a dielectric film and increasing an effective surface area have been conducted. In addition, instead of the silicon oxide film (SiO 2 ) having a dielectric constant (ε) of about 3-4, a high dielectric material NO (Nitride-Oxide) structure or ONO (Oxide-Nitride-Oxide) structure or Ta 2 O 5 or Material studies are also underway to replace BST (BaSrTiO 3 ). The high dielectric film quality can be applied not only to the capacitor but also to the insulating film of the gate electrode in the flash memory.

그 중에서도 N/O 구조의 유전체막은 제조 공정이 간단하면서도 고유전율을 확보할 수 있는 장점을 갖고 있어 전극간 절연체로 자주 사용되고 있다. 즉, N/O 구조의 유전체막을 사용하는 반도체소자(예컨대, 커패시터 또는 플래시 게이트전 극)에서는 하부전극에 질화막(SiN)을 증착하고 그 위에 산화막(SiO2)을 적층해서 복합 N/O 구조의 유전체막을 형성함으로써 원하는 반도체소자의 용량을 얻고 있다.Among them, N / O-structured dielectric films are frequently used as inter-electrode insulators because of their simple manufacturing process and high dielectric constant. That is, in a semiconductor device (eg, a capacitor or a flash gate electrode) that uses a dielectric film having an N / O structure, a nitride film (SiN) is deposited on a lower electrode, and an oxide film (SiO 2 ) is stacked thereon to form a composite N / O structure. By forming the dielectric film, the desired capacitance of the semiconductor device is obtained.

그러나, 소자의 속도를 증가시키기 위하여 금속 배선(예컨대, 워드라인 및 비트라인)을 갖는 반도체장치의 경우 N/O 구조의 유전체막 중에서 750℃ 이상의 고온의 산화 공정을 진행하면 높은 써멀 버젯(thermal budget)에 의해 배선의 전기적 특성이 저하되고 동시에 질화막의 산화정도가 증가되어 저유전체막을 형성함으로써 소자의 신뢰성 및 수율을 낮추는 문제가 있었다.However, in order to increase the speed of the device, a semiconductor device having metal wirings (eg, word lines and bit lines) has a high thermal budget when a high temperature oxidation process of 750 ° C. or higher is performed in a dielectric film having an N / O structure. By lowering the electrical characteristics of the wiring and at the same time the oxidation degree of the nitride film is increased to form a low dielectric film has a problem of lowering the reliability and yield of the device.

본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 NO 구조의 유전체막에서 산화막 제조 공정시 질화막 표면을 400℃∼700℃의 온도에서 N2O 또는 NH3 가스 분위기에서 플라즈마로 열처리하여 산화막을 형성함으로써 고온의 산화 공정으로 인한 써멀 버젯을 줄여 소자의 전기적 특성을 향상시키면서 고유전체막을 얻을 수 있는 반도체장치의 커패시터 제조방법을 제공하는데 있다.
An object of the present invention is to heat-treat the surface of the nitride film in a N 2 O or NH 3 gas atmosphere at a temperature of 400 ℃ to 700 ℃ in the oxide film manufacturing process in the NO structure dielectric film in order to solve the problems of the prior art as described above The present invention provides a method of manufacturing a capacitor of a semiconductor device capable of obtaining a high dielectric film while improving the electrical characteristics of a device by reducing the thermal budget caused by a high temperature oxidation process by forming an oxide film.

상기 목적을 달성하기 위하여 본 발명은 반도체장치의 커패시터 제조 방법에 있어서, 반도체기판에 도전체로 이루어진 하부전극을 형성하는 단계와, 하부전극 상부에 질화막과 산화막이 적층된 유전체박막을 형성하되, 질화막 표면을 400℃∼700℃의 온도에서 N2O 또는 NH3 가스 분위기에서 플라즈마로 열처리하여 산화막을 형성하는 단계와, 유전체박막 상부에 도전체로 이루어진 상부전극을 형성하는 단계를 포함하여 이루어진다.In order to achieve the above object, the present invention provides a method of manufacturing a capacitor of a semiconductor device, the method comprising: forming a lower electrode made of a conductor on a semiconductor substrate, and forming a dielectric thin film in which a nitride film and an oxide film are stacked on an upper surface of the lower electrode; Heat-treating a plasma in a N 2 O or NH 3 gas atmosphere at a temperature of 400 ° C. to 700 ° C. to form an oxide film, and forming an upper electrode made of a conductor on the dielectric thin film.

본 발명의 제조 방법에 있어서, 상기 유전체박막의 산화막 형성은 플라즈마 질화 공정시 전원을 10W∼1000W으로 하고 N2O 또는 NH3 가스를 10∼1000sccm 플로우하는 것이 바람직하다. 이때 산화막의 두께는 하부 질화막에서 1Å∼20Å정도를 산화시켜 형성하는 것이 바람직하다.In the production method of the present invention, in the formation of the oxide film of the dielectric thin film, it is preferable that the power is 10 W to 1000 W and the N 2 O or NH 3 gas is flowed 10 to 1000 sccm during the plasma nitridation process. At this time, the thickness of the oxide film is preferably formed by oxidizing about 1 GPa-20 GPa in the lower nitride film.

본 발명에 따르면, N/O 구조의 유전체박막에서 산화막 제조 공정시 저온에서 플라즈마 열공정으로 질화막의 상부를 산화시킴으로써 고온 열산화 공정으로 인한 소자의 전기적 특성 저하를 방지할 수 있다.According to the present invention, by oxidizing the upper portion of the nitride film by the plasma thermal process at a low temperature during the oxide film manufacturing process in the dielectric thin film of the N / O structure it is possible to prevent the electrical characteristics of the device due to the high temperature thermal oxidation process.

이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1 내지 도 4는 본 발명에 따른 반도체장치의 커패시터 제조방법을 설명하기 위한 공정 순서도로서, 이를 참조하여 본 발명의 실시예인 N/O 구조의 유전체막을 갖는 커패시터 제조 공정은 다음과 같다.1 to 4 are process flowcharts illustrating a method of manufacturing a capacitor of a semiconductor device according to the present invention. Referring to this, a process of manufacturing a capacitor having a dielectric film having an N / O structure according to an embodiment of the present invention is as follows.

우선, 도 1에 도시된 바와 같이, 반도체 소자(예컨대, 모스 트랜지스터)가 형성된 반도체 기판의 구조물(10)에 접합 영역과 연결되도록 도전층을 소정 두께로 증착시켜 하부전극(20)을 형성한다. First, as shown in FIG. 1, the lower electrode 20 is formed by depositing a conductive layer with a predetermined thickness so as to be connected to a junction region in a structure 10 of a semiconductor substrate on which a semiconductor device (eg, a MOS transistor) is formed.

여기서, 하부전극(20)의 도전층은 도프트 폴리실리콘(10) 및 언도프트 폴리실리콘이거나 또는 금속 물질일 수도 있다. 그리고, 하부전극(B)의 형태는 스택(stack), 트렌치(trench), 실린더(cylinder), 핀(fin), 스택 실린더(stack cylinder) 중에서 어느 하나를 채택한다. 또한, 하부전극의 평면적을 늘리기 위하여 HSG 공정을 실시할 수도 있다.Here, the conductive layer of the lower electrode 20 may be a doped polysilicon 10 and undoped polysilicon, or may be a metallic material. In addition, the shape of the lower electrode B may be any one of a stack, a trench, a cylinder, a fin, and a stack cylinder. In addition, the HSG process may be performed to increase the planar area of the lower electrode.

그 다음, 본 발명에 따른 N/O 구조의 유전체박막 제조 공정을 실시한다. 이에, 도 2 및 도 3에 도시된 바와 같이 하부전극 상부에 질화막(32)과 산화막(34)이 적층된 유전체박막(30)을 형성한다.Next, a dielectric thin film manufacturing process of the N / O structure according to the present invention is carried out. Accordingly, as shown in FIGS. 2 and 3, the dielectric thin film 30 having the nitride film 32 and the oxide film 34 stacked thereon is formed on the lower electrode.

여기서, 질화막(32) 증착은 디클로로사일렌(SiH2Cl2) 및 NH3 가스 (또는 사일렌(SiH4) 및 NH3 가스)를 사용한다. Here, the nitride film 32 is deposited using dichloroxylene (SiH 2 Cl 2 ) and NH 3 gas (or xylene (SiH 4 ) and NH 3 gas).

그리고, 산화막(34)은 400℃∼700℃의 온도에서 N2O 또는 NH3 가스 분위기에서 플라즈마(plasma)로 열처리하여 질화막(32)의 표면을 1Å∼20Å정도를 산화시켜 형성한다.The oxide film 34 is formed by heat-treating the plasma in an N 2 O or NH 3 gas atmosphere at a temperature of 400 ° C. to 700 ° C. to oxidize the surface of the nitride film 32 by about 1 GPa to 20 GPa.

그 다음, 도 4에 도시된 바와 같이, 상기 질화막(N)/산화막(O) 구조의 유전체막(30) 상부에 도전층으로서 불순물이 도핑된 폴리실리콘을 증착하고 식각공정으로 이를 패터닝하여 상부전극(40)을 형성한다. 이때, 상부전극(40)의 도프트 폴리실리콘과 유전체막(30) 사이에 유전체막(30)의 전도 장벽(conduction barrier) 역할을 하는 금속을 추가할 수 있다. 금속 재료로는 TiN 대신에 TaN, W, WN, WSi, Ru, RuO2, Ir, IrO2, Pt 중에서 어느 하나를 사용한다.Next, as shown in FIG. 4, polysilicon doped with an impurity as a conductive layer is deposited on the dielectric layer 30 having the nitride film N / oxide layer O and patterned by an etching process. 40 is formed. In this case, a metal serving as a conduction barrier of the dielectric film 30 may be added between the doped polysilicon of the upper electrode 40 and the dielectric film 30. Instead of TiN, any one of TaN, W, WN, WSi, Ru, RuO 2 , Ir, IrO 2 , and Pt is used as the metal material.

상술한 바와 같이, 본 발명은 N/O 구조의 유전체박막에서 산화막 제조 공정시 저온(400℃∼700℃)에서 N2O 또는 NH3 가스 분위기에서 플라즈마공정으로 질화막의 상부를 산화시킴으로써 종래 고온의 산화 공정으로 인한 써멀 버젯을 줄여 소자의 전기적 특성을 향상시킬 수 있다. 그리고, N/O 구조의 유전체박막의 산화막 두께를 얇게 조절할 수 있어 고유전율을 얻을 수 있고 결국, 반도체소자의 용량을 증가시킬 수 있는 이점이 있다.As described above, the present invention oxidizes the upper portion of the nitride film by a plasma process in a N 2 O or NH 3 gas atmosphere at low temperature (400 ℃ to 700 ℃) during the oxide film manufacturing process in the N / O dielectric thin film. The thermal budget due to the oxidation process can be reduced to improve the device's electrical characteristics. In addition, the thickness of the oxide film of the dielectric thin film of the N / O structure can be adjusted thinly, thereby obtaining a high dielectric constant, which in turn has the advantage of increasing the capacity of the semiconductor device.

본 발명은 상기 실시예에 한정되지 않으며, 전극간 N/O구조의 유전체물질을 갖는 소자, 예컨대 플래시 메모리의 게이트전극간 절연체 제조 공정에도 적용이 가능하다.
The present invention is not limited to the above embodiment, and is applicable to a device having a dielectric material of an inter-electrode N / O structure, for example, a process of manufacturing an insulator between gate electrodes of a flash memory.

Claims (3)

반도체장치의 커패시터 제조 방법에 있어서,In the capacitor manufacturing method of a semiconductor device, 반도체기판에 도전체로 이루어진 하부전극을 형성하는 단계;Forming a lower electrode made of a conductor on the semiconductor substrate; 상기 하부전극 상부에 질화막과 산화막이 적층된 유전체박막을 형성하되, 상기 질화막 표면을 400℃∼700℃의 온도에서 N2O 또는 NH3 가스 분위기에서 형성되는 상기 산화막의 두께가 1Å∼20Å가 되도록 플라즈마로 열처리하여 상기 산화막을 형성하는 단계; 및A dielectric thin film in which a nitride film and an oxide film are stacked is formed on the lower electrode, and the surface of the nitride film is formed in a N 2 O or NH 3 gas atmosphere at a temperature of 400 ° C. to 700 ° C. such that the thickness of the oxide film is 1 kPa to 20 kPa. Heat-treating the plasma to form the oxide film; And 상기 유전체박막 상부에 도전체로 이루어진 상부전극을 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체장치의 커패시터 제조방법.And forming an upper electrode made of a conductor on the dielectric thin film. 제 1항에 있어서, 상기 유전체박막의 산화막 형성은 플라즈마 질화 공정시 전원을 10W∼1000W으로 하고 N2O 또는 NH3 가스를 10∼1000sccm 플로우하는 것을 특징으로 하는 반도체장치의 커패시터 제조방법.The method of manufacturing a capacitor of claim 1, wherein the oxide thin film is formed to have a power supply of 10 W to 1000 W and a flow of N 2 O or NH 3 gas in the plasma nitriding process. 삭제delete
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US5696036A (en) * 1996-11-15 1997-12-09 Mosel, Vitelic Inc. DRAM no capacitor dielectric process
KR100189979B1 (en) * 1995-11-20 1999-06-01 윤종용 Method for manufacturing capacitor of semiconductor device
KR100207465B1 (en) * 1996-02-28 1999-07-15 윤종용 Capacitor fabrication method of semiconductor device
KR100224676B1 (en) * 1996-12-30 1999-10-15 윤종용 Manufacturing method for capacitor of semiconductor device

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KR100189979B1 (en) * 1995-11-20 1999-06-01 윤종용 Method for manufacturing capacitor of semiconductor device
KR100207465B1 (en) * 1996-02-28 1999-07-15 윤종용 Capacitor fabrication method of semiconductor device
US5696036A (en) * 1996-11-15 1997-12-09 Mosel, Vitelic Inc. DRAM no capacitor dielectric process
KR100224676B1 (en) * 1996-12-30 1999-10-15 윤종용 Manufacturing method for capacitor of semiconductor device

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