KR100351451B1 - Method for forming capacitor of memory device - Google Patents
Method for forming capacitor of memory device Download PDFInfo
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- KR100351451B1 KR100351451B1 KR1019990067267A KR19990067267A KR100351451B1 KR 100351451 B1 KR100351451 B1 KR 100351451B1 KR 1019990067267 A KR1019990067267 A KR 1019990067267A KR 19990067267 A KR19990067267 A KR 19990067267A KR 100351451 B1 KR100351451 B1 KR 100351451B1
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- South Korea
- Prior art keywords
- interlayer insulating
- forming
- insulating film
- diffusion barrier
- contact hole
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000003990 capacitor Substances 0.000 title claims abstract description 26
- 239000011229 interlayer Substances 0.000 claims abstract description 40
- 230000004888 barrier function Effects 0.000 claims abstract description 38
- 238000009792 diffusion process Methods 0.000 claims abstract description 36
- 239000010410 layer Substances 0.000 claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 claims abstract description 14
- 239000004020 conductor Substances 0.000 claims abstract description 12
- 238000003860 storage Methods 0.000 claims abstract description 11
- 238000007747 plating Methods 0.000 claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 7
- 150000002736 metal compounds Chemical class 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 238000009413 insulation Methods 0.000 claims abstract description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 229910052741 iridium Inorganic materials 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 abstract description 8
- 230000006866 deterioration Effects 0.000 abstract description 4
- 238000000059 patterning Methods 0.000 abstract description 4
- 239000010408 film Substances 0.000 description 43
- 239000000463 material Substances 0.000 description 7
- 239000005380 borophosphosilicate glass Substances 0.000 description 6
- 239000011810 insulating material Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910021339 platinum silicide Inorganic materials 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- -1 tungsten boro nitride Chemical class 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- HTXDPTMKBJXEOW-UHFFFAOYSA-N dioxoiridium Chemical compound O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 230000001546 nitrifying effect Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 반도체메모리장치의 커패시터 제조방법에 관한 것으로서, 특히 이 방법은 반도체 기판에 소정의 하부 구조, 예컨대 모스 트랜지스터를 형성하고, 이를 층간 절연하는 제 1층간 절연막을 형성한 후에, 제 1층간 절연막에 콘택홀을 형성하고 그 콘택홀내에 도전체를 매립하여 기판의 접합 영역과 이후 형성될 스토리지노드 전극을 서로 연결하는 콘택플러그를 형성하고, 제 1층간 절연막 상부에 제 2층간 절연막을 형성하고 제 2층간 절연막내에 콘택홀을 형성하고, 제 2층간 절연막의 콘택홀에 매립되도록 도금 방법으로 금속 또는 금속화합물을 증착하고 이를 평탄화해서 콘택플러그와 연결되는 확산 방지막을 형성한 후에, 확산 방지막이 형성된 구조물에 도전체로 된 스토리지노드 전극/ 강유전체막/도전체로 된 플레이트노드 전극을 순차 형성한다. 따라서, 본 발명은 층간 절연막의 콘택홀에 확산 방지막을 도금 방법에 의해 완전히 매립함으로써 이후 커패시터 패터닝 공정시 확산 방지막의 노출을 막아 후속 강유전체의 고온 열처리 공정으로 인한 확산 방지막의 열화를 막을 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor memory device. In particular, the method includes forming a predetermined substructure, for example, a MOS transistor, on a semiconductor substrate, and then forming a first interlayer insulating film for interlayer insulation. Forming a contact hole in the contact hole and forming a contact plug connecting the junction region of the substrate and the storage node electrode to be formed later by forming a conductor in the contact hole, and forming a second interlayer insulating film on the first interlayer insulating film. After forming a contact hole in the interlayer insulating film, depositing a metal or a metal compound by a plating method so as to be buried in the contact hole of the second interlayer insulating film and planarizing it to form a diffusion barrier film connected to the contact plug, the structure is formed with a diffusion barrier film Storage node electrode / ferroelectric film / conductor plate node electrode The. Therefore, in the present invention, the diffusion barrier layer is completely embedded in the contact hole of the interlayer insulating layer by the plating method, thereby preventing exposure of the diffusion barrier layer during the capacitor patterning process, thereby preventing deterioration of the diffusion barrier due to the high temperature heat treatment process of the ferroelectric.
Description
본 발명은 반도체메모리장치의 커패시터 제조 방법에 관한 것으로서, 특히 FeRAM소자의 커패시터 제조 공정시 커패시터와 콘택 플러그 사이에 형성되는 확산 방지막을 개선하여 반도체소자의 수율 및 신뢰성을 향상시킬 수 있는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor memory device, and more particularly, to improve a yield and reliability of a semiconductor device by improving a diffusion barrier formed between a capacitor and a contact plug during a capacitor manufacturing process of a FeRAM device.
현재, 반도체장치의 고집적화를 달성하기 위하여 셀 면적의 감소 및 동작 전압의 저전압화에 관한 연구/개발이 활발하게 진행되고 있다. 더구나, 반도체장치의 고집적화가 이루어질수록 커패시터의 면적이 급격하게 감소되더라도 기억소자의 동작에 필요한 충전 용량은 셀 면적 감소에도 불구하고 소프트 에러(soft error)의 발생과 리프레시(refresh) 시간의 단축을 방지하기 위해서, 25fF/cell 이상의 충분한 정전용량(capacitance)이 요구되고 있다.At present, in order to achieve high integration of semiconductor devices, research / development has been actively conducted on reducing the cell area and lowering the operating voltage. In addition, as the integration of semiconductor devices increases, the charge capacity required for the operation of the memory device, even though the area of the capacitor is drastically reduced, prevents the occurrence of soft errors and shortening of the refresh time despite the reduction of the cell area. In order to achieve this, a sufficient capacitance of 25 fF / cell or more is required.
현재 DRAM(Dynamic Random Access Memory)의 집적도가 256M bit 이상으로 증가함에 따라, 커패시터의 충분한 용량을 확보하기 위해서 통상의 실린더 구조 변경을 통해 커패시터 면적을 증가하거나 유전체막의 두께 감소를 통해 충분한 정전용량를 확보시키는 방법이 이루어지고 있으며, 기존 실리콘 산화막으로 사용하던 유전체막을 NO(Nitride-Oxide) 또는 ONO(Oxide-Nitride-Oxide) 구조라든지 Ta2O5등의 고유전체 물질로 대체하려는 재료적인 연구가 진행되고 있다.As the density of DRAM (Dynamic Random Access Memory) is increased to 256M bit or more, it is necessary to increase the capacitor area by changing the conventional cylinder structure to secure sufficient capacity of the capacitor, or to secure sufficient capacitance by reducing the thickness of the dielectric film. In this regard, a material research is being conducted to replace the dielectric film used as a silicon oxide film with a high dielectric material such as NO (Nitride-Oxide) or ONO (Oxide-Nitride-Oxide) structure or Ta 2 O 5 . .
기존의 ON(Oxide/Nitride)을 유전물질로 이용한 커패시터 구조는, 최소의 유효 정전용량의 확보를 위해 평면(planer) 구조에서 시작하여 트렌치(trench), 스택(stack) 셀 구조를 거쳐 실린더(cylinder), 핀(fin) 구조까지 개발되어 왔다.The conventional capacitor structure using ON (Oxide / Nitride) as a dielectric material starts from a planar structure, through a trench, stack cell structure, and cylinder to secure minimum effective capacitance. And fin structures have been developed.
그러나, 이와 같은 실리더 또는 핀 구조등의 커패시터 구조를 구현하기 위해서는 제조 공정이 매우 복잡하기 때문에 경제성 및 신뢰도의 측면에서 문제가 되고 있다.However, in order to implement such a capacitor structure, such as a cylinder or a pin structure, the manufacturing process is very complicated, which is a problem in terms of economics and reliability.
최근에는 커패시터 구조의 한계를 극복하고자 페롭스카이트(perovskite) 구조의 강유전체(ferroelectric) 물질, 예컨대 SrBi2Ta2O9, SrBi(Ta,Nb)2O9, SrBi2Nb2O9등의 계열 물질을 사용하기에 이르렀다. 강유전체를 갖는 반도체 메모리장치는 유전상수(ε)가 보통 수백에서 1,000 정도의 강유전체막의 분극 반전 특성 및 그 잔류 분극을 이용하여 고속으로 읽기(read)/쓰기(write) 동작이 가능한 장점을 가지고 있다.Recently, in order to overcome the limitations of the capacitor structure, ferroelectric materials of the perovskite structure, such as SrBi 2 Ta 2 O 9 , SrBi (Ta, Nb) 2 O 9 , SrBi 2 Nb 2 O 9, etc. The material has been used. A semiconductor memory device having a ferroelectric has an advantage that the read / write operation can be performed at high speed by using the polarization reversal characteristic of the ferroelectric film having a dielectric constant? Of about several hundred to 1,000 and the residual polarization thereof.
이러한 강유전체를 채택한 반도체 메모리장치의 경우에는, 강유전체를 수백Å의 후막(厚膜)으로 형성하여도 등가-산화막 두께(equivalent oxide thickness)를 10Å 이하로 박막화할 수 있는 이점이 있다.In the case of a semiconductor memory device employing such a ferroelectric, even when the ferroelectric is formed into a thick film of several hundreds of microns, there is an advantage that the equivalent oxide thickness can be reduced to 10 microns or less.
그러나, 현재 강유전체 박막을 커패시터의 유전체, 스토리지노드 전극 또는 플레이트노드 전극을 백금(Pt) 물질로 형성한 경우에는 500℃이상의 고온에서 콘택 플러그의 폴리실리콘과 반응하여 백금 실리사이드(Pt silicide)를 형성하게 된다. 이 백금 실리사이드는 부피 팽창에 의해 크랙(crack) 및 필링(peeling)의 원인으로 작용하므로 스토리지노드 전극과 콘택 플러그 사이에 확산 방지막을 추가 형성하고있다. 확산 방지막로서는 WBN(tungsten boro nitride), SiAlTiN(silicon aluminium titanium nitride), IrO2(iridium oxide), MoN(moli-nitride) 등의 다양한 물질이 제안, 연구되고 있다.However, in the case where the ferroelectric thin film is formed of a dielectric material of a capacitor, a storage node electrode, or a plate node electrode with platinum (Pt) material, it reacts with polysilicon of a contact plug at a high temperature of 500 ° C. or higher to form platinum silicide. do. Since the platinum silicide acts as a cause of cracking and peeling due to volume expansion, an additional diffusion barrier is formed between the storage node electrode and the contact plug. Various materials such as tungsten boro nitride (WBN), silicon aluminum titanium nitride (SiAlTiN), iridium oxide (IrO 2 ), and mol-nitride (MoN) have been proposed and studied.
도 1은 종래 기술에 의한 반도체 메모리장치의 커패시터 제조 방법을 설명하기 위한 단면도이다.1 is a cross-sectional view illustrating a capacitor manufacturing method of a semiconductor memory device according to the prior art.
도 1을 참조하면, 종래 확산 방지막이 추가된 스택형 커패시터 제조 공정은 다음과 같다. 즉, 반도체기판으로서 실리콘기판(10)에 필드 산화막(12)을 형성하고, 그 활성 영역 상부면에 게이트절연막(14), 게이트 전극(16) 및 소스/드레인 접합(18)을 갖는 트랜지스터를 형성한다. 그리고, 상기 기판 전면에 USG(Undoped Silicate Glass), BPSG(Boro Phospho Silicate Glass) 및 SiON 중에서 선택한 절연물질을 증착하고 화학적기계적연마(Chemical Mechanical Polishing) 공정을 실시하여 제 1층간 절연막(20)을 형성한다. 상기 제 1층간 절연막(20)에 콘택홀을 형성하고 도전체로서 도프트 폴리실리콘을 매립하고 이를 평탄화해서 콘택 플러그를 형성한다. 그리고, 배선 공정을 진행하여 소오스 또는 드레인접합 부위의 콘택 플러그에 연결되는 비트라인(22)을 형성한다. 다시 결과물 전면에 제 2층간절연막(24) 및 그 위에 절연 물질로된 보호 박막(25)을 형성한다. 계속해서, 제 2층간절연막(24)에 콘택홀을 형성하고 도전물질로서 도프트 폴리실리콘을 매립한 후에 이를 평탄화해서 콘택 플러그(26)를 형성한다. 그 다음, 상기 제 2층간절연막(24) 전면에 화학기상증착 또는 물리기상증착법에 의해 확산 방지막(30)을 형성한다. 그리고, 제 2층간 절연막(24)위에 스토리지노드용 도전체(32)를 증착하고 그 위에 강유전체막(34) 및 플레이트노드용 도전체(36)막을 순차 적층한다. 마지막으로 커패시터 마스크를 이용한 사진 및 식각 공정을 적층된 도전체막들(36,32)과 그 사이의 강유전체막(34)을 패터닝한 후에 하부의 확산 방지막(30)도 패터닝한다.Referring to FIG. 1, a stack capacitor manufacturing process to which a conventional diffusion barrier is added is as follows. That is, a field oxide film 12 is formed on the silicon substrate 10 as a semiconductor substrate, and a transistor having a gate insulating film 14, a gate electrode 16, and a source / drain junction 18 is formed on the upper surface of the active region. do. The first interlayer insulating film 20 is formed by depositing an insulating material selected from USG (Undoped Silicate Glass), BPSG (Boro Phospho Silicate Glass) and SiON on the entire surface of the substrate, and performing a chemical mechanical polishing process. do. A contact hole is formed in the first interlayer insulating film 20, and a doped polysilicon is embedded as a conductor and planarized to form a contact plug. Then, the wiring process is performed to form the bit line 22 connected to the contact plug of the source or drain junction portion. A second interlayer insulating film 24 and a protective thin film 25 made of an insulating material are formed on the entire surface of the resultant product. Subsequently, a contact hole is formed in the second interlayer insulating film 24 and the doped polysilicon is embedded as a conductive material, and then planarized to form the contact plug 26. Next, the diffusion barrier layer 30 is formed on the entire surface of the second interlayer insulating layer 24 by chemical vapor deposition or physical vapor deposition. Then, the storage node conductor 32 is deposited on the second interlayer insulating film 24, and the ferroelectric film 34 and the plate node conductor 36 film are sequentially stacked thereon. Finally, after patterning the conductive layers 36 and 32 and the ferroelectric layer 34 therebetween, the photolithography and etching processes using the capacitor mask are patterned, and the lower diffusion barrier layer 30 is also patterned.
하지만, 상기와 같은 커패시터 패터닝 공정시 확산 방지막(30)의 측벽이 노출되기 때문에 700℃ 이상의 고온 열처리를 필요로 하는 강유전체를 갖는 FeRAM소자의 열처리 공정에서 노출 부분이 산소의 통로가 되므로 확산 방지막의 원래 역할을 하지 못하게 되는 단점이 있다.However, since the sidewalls of the diffusion barrier layer 30 are exposed during the capacitor patterning process as described above, the exposed portion becomes the passage of oxygen in the heat treatment process of the FeRAM device having a ferroelectric material requiring a high temperature heat treatment of 700 ° C. or higher. There is a drawback to not playing a role.
본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 층간 절연막의 콘택홀에 확산 방지막을 도금 방법에 의해 매립함으로써 이후 커패시터 패터닝 공정시 확산 방지막의 노출을 막아 후속 강유전체의 고온 열처리 공정으로 인한 확산 방지막의 열화를 막을 수 있는 반도체메모리장치의 커패시터 제조방법을 제공하는데 있다.An object of the present invention is to fill the diffusion barrier film in the contact hole of the interlayer insulating film by the plating method in order to solve the problems of the prior art as described above to prevent the exposure of the diffusion barrier film in the capacitor patterning process to the subsequent high temperature heat treatment process of the ferroelectric The present invention provides a method of manufacturing a capacitor of a semiconductor memory device capable of preventing deterioration of a diffusion barrier.
도 1은 종래 기술에 의한 반도체 메모리장치의 커패시터 제조 방법을 설명하기 위한 단면도,1 is a cross-sectional view for explaining a capacitor manufacturing method of a semiconductor memory device according to the prior art;
도 2a 내지 도 2c는 본 발명에 따른 반도체메모리장치의 커패시터 제조방법을 설명하기 위한 단면도들.2A to 2C are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor memory device according to the present invention.
* 도면의 주요 부분에 대한 부호 설명 *Explanation of symbols on the main parts of the drawings
100: 실리콘기판 102: 필드 산화막100: silicon substrate 102: field oxide film
104: 게이트절연막 106: 게이트전극104: gate insulating film 106: gate electrode
108: 소오스/드레인 접합 110: 제 1층간 절연막108: source / drain junction 110: first interlayer insulating film
112: 콘택 플러그 114: 제 2층간 절연막112: contact plug 114: second interlayer insulating film
116: 보호박막 118: 콘택홀116: protective film 118: contact hole
120: 확산방지막 122: 하부전극120: diffusion barrier 122: lower electrode
124: 강유전체막 126: 상부전극124: ferroelectric film 126: upper electrode
이러한 목적을 달성하기 위하여 본 발명은 반도체 기판에 소정의 하부구조를 형성하고, 이를 층간 절연하는 제 1층간 절연막을 형성하는 단계와, 제 1층간 절연막에 콘택홀을 형성하고 그 콘택홀내에 도전체를 매립하여 기판의 접합 영역과 이후 형성될 스토리지노드 전극을 서로 연결하는 콘택플러그를 형성하는 단계와, 제 1층간 절연막 상부에 제 2층간 절연막을 형성하는 단계와, 제 2층간 절연막내에 콘택홀을 형성하는 단계와, 제 2층간 절연막의 콘택홀에 매립되도록 금속 또는 금속화합물을 증착하고 이를 평탄화해서 콘택플러그와 연결되는 확산 방지막을 형성하는 단계와, 확산 방지막이 형성된 구조물에 도전체로 된 스토리지노드 전극/ 강유전체막/도전체로 된 플레이트노드 전극을 순차 형성하는 단계에 있어서, 상기 확산방지막은 도금방법으로 콘택홀을 매립하여 형성하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method of forming a predetermined substructure on a semiconductor substrate, forming a first interlayer insulating film for interlayer insulation, forming a contact hole in the first interlayer insulating film, and forming a conductor in the contact hole. Forming a contact plug connecting the junction region of the substrate and the storage node electrode to be formed later, forming a second interlayer insulating film on the first interlayer insulating film, and forming a contact hole in the second interlayer insulating film. Forming a diffusion barrier layer formed by depositing a metal or a metal compound so as to be buried in the contact hole of the second interlayer insulating layer and planarizing the same; and forming a diffusion barrier layer connected to the contact plug; In the step of sequentially forming a plate node electrode of a ferroelectric film / conductor, the diffusion barrier film is a plating method As it characterized by forming a buried contact hole.
이하, 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명에 따른 반도체메모리장치의 커패시터 제조방법을 설명하기 위한 단면도들이다.2A to 2C are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor memory device according to the present invention.
우선, 도 2a에 도시된 바와 같이 반도체기판으로서 실리콘기판(100)에 필드 산화막(102)을 형성하고, 그 기판의 활성 영역 상부에 게이트절연막(104), 게이트 전극(106), 및 소스/드레인 접합(108)을 갖는 트랜지스터를 형성한다. 그리고, 그 기판 전면에 USG, BPSG 및 BPSG/TEOS-SiO2중에서 선택한 절연물질을 증착하고 화학적기계적연마(Chemical Mechanical Polishing) 공정으로 그 표면을 평탄화하여 제 1층간 절연막(110)을 형성한다.First, as shown in FIG. 2A, a field oxide film 102 is formed on a silicon substrate 100 as a semiconductor substrate, and a gate insulating film 104, a gate electrode 106, and a source / drain are disposed over an active region of the substrate. A transistor with junction 108 is formed. In addition, an insulating material selected from USG, BPSG, and BPSG / TEOS-SiO 2 is deposited on the entire surface of the substrate, and the first interlayer insulating film 110 is formed by planarizing the surface by a chemical mechanical polishing process.
그리고, 상기 제 1층간 절연막(110)에 콘택홀을 형성하고 그 콘택홀내에 도전체로서 도프트 폴리실리콘을 매립하고 이를 평탄화해서 기판의 접합 영역(108)과 이후 형성될 스토리지노드 전극을 서로 연결하기 위한 콘택플러그(112)를 형성한다. 그리고, 배선 공정을 진행하여 소오스 또는 드레인 접합(108) 부위의 콘택 플러그에 연결되는 비트라인(113)을 형성한다.In addition, a contact hole is formed in the first interlayer insulating layer 110, and the doped polysilicon is buried as a conductor in the contact hole and planarized to connect the junction region 108 of the substrate to the storage node electrode to be formed later. The contact plug 112 is formed. The wiring process is performed to form the bit line 113 connected to the contact plug of the source or drain junction 108.
다시 결과물 전면에, 제 1층간 절연막(110) 상부에 USG, BPSG 및 BPSG/TEOS-SiO2중에서 어느 하나를 사용하여 제 2층간 절연막(114)을 형성하고, 제 2층간 절연막(114)내에 콘택홀(118)을 형성한다. 여기서, 상기 제 2층간절연막(114) 위에 절연 물질로된 보호 박막(116)을 추가할 수도 있다.Again, on the entire surface of the resultant, a second interlayer insulating film 114 is formed on the first interlayer insulating film 110 by using any one of USG, BPSG, and BPSG / TEOS-SiO 2 , and a contact is made in the second interlayer insulating film 114. The hole 118 is formed. Here, a protective thin film 116 made of an insulating material may be added on the second interlayer insulating film 114.
그 다음, 도 2b에 도시된 바와 같이 제 2층간 절연막(114)의 콘택홀에 매립되도록 선택적 증착이 가능한 도금 방법(전해 또는 무전해 도금)으로 금속 또는 금속화합물을 증착하고 이를 평탄화해서 콘택플러그(112)와 연결되는 확산 방지막(120)을 형성한다. 여기서, 상기 확산 방지막(120)의 금속 또는 금속화합물은 Ir, W, SiTiN, WBN, SiAlTin, IrO2, MoN 중에서 어느 하나를 사용한다. 본 발명의 확산 방지막 제조 공정시 빠른 증착 속도와 높은 선택비를 갖는 도금방법을 이용하기 ??문에 콘택홀의 깊이에 따라 종래보다 확산 방지막의 두께를 증가시킬 수 있어 장벽 특성을 높일 수 있다.Next, as shown in FIG. 2B, a metal or metal compound is deposited by a plating method (electrolytic or electroless plating) capable of selective deposition so as to be buried in the contact hole of the second interlayer insulating film 114, and planarized to contact the plug. The diffusion barrier 120 is connected to the 112. Here, the metal or metal compound of the diffusion barrier 120 is any one of Ir, W, SiTiN, WBN, SiAlTin, IrO 2 , MoN. In the manufacturing process of the diffusion barrier film of the present invention, since the plating method having a high deposition rate and a high selectivity is used, the thickness of the diffusion barrier layer can be increased according to the depth of the contact hole, thereby increasing the barrier property.
이어서, 이후 스토리지노드 전극을 형성하기 전에 상기 확산 방지막(120)이 형성된 구조물에 열처리 또는 플라즈마를 이용한 후처리 공정을 추가 실시할 수 있다. 이때, 상기 후처리 공정시 O2, N2, 또는 N2O 분위기에서 실시한다. 이와 같이 후처리 공정을 실시하는 이유는 노출된 확산 방지막(120)의 표면을 산화 또는 질화(또는 질산화)처리하여 계면 특성을 양호하게 하기 위한 헤테로 구조(hetero structure)를 갖는 확산 방지막을 제작하기 위함이다.Subsequently, a post-treatment process using heat treatment or plasma may be additionally performed on the structure on which the diffusion barrier layer 120 is formed before the storage node electrode is formed. At this time, the post-treatment step is carried out in O 2 , N 2 , or N 2 O atmosphere. The reason for performing the post-treatment process as described above is to manufacture a diffusion barrier having a hetero structure for improving the interfacial properties by oxidizing or nitriding (or nitrifying) the surface of the exposed diffusion barrier 120. to be.
그 다음, 도 3c에 도시된 바와 같이 상기 확산 방지막(120)이 형성된 구조물에 도전체로 된 스토리지노드 전극(122)/ 강유전체막(124)/도전체로 된 플레이트노드 전극(126)을 순차 형성하여 본 발명에 따른 강유전체 커패시터 제조 공정을 완료한다. 여기서, 강유전체막(124)은 SrBi2Ta2O9, SrBi2Nb2O9등의 Y-1계열의 물질을 사용한다.Next, as shown in FIG. 3C, the storage node electrode 122, the ferroelectric layer 124, and the plate node electrode 126, which are conductive materials, are sequentially formed in the structure in which the diffusion barrier layer 120 is formed. Complete the ferroelectric capacitor manufacturing process according to the invention. Here, the ferroelectric film 124 uses Y-1 series materials such as SrBi 2 Ta 2 O 9 and SrBi 2 Nb 2 O 9 .
그러므로, 본 발명은 FeRAM 소자의 강유전체막의 특성을 확보하기 위해 700℃∼1000℃의 범위에서 열처리 공정을 실시하더라도 확산 방지막(120)이 층간 절연막(114)의 콘택홀에 매몰된 상태이므로 상기 열 공정에 의한 확산 방지막의 열화를 줄일 수 있다.Therefore, in the present invention, even if the heat treatment process is performed in the range of 700 ° C. to 1000 ° C. in order to secure the characteristics of the ferroelectric film of the FeRAM device, the diffusion barrier 120 is buried in the contact hole of the interlayer insulating film 114. Deterioration of the diffusion barrier due to this can be reduced.
상기한 바와 같이, 본 발명은 간단한 도금 방법으로 층간 절연막의 콘택홀에 하부 콘택 플러그와 연결되는 확산 방지막을 형성할 수 있으며 콘택홀의 깊이에 따라 확산 방지막의 두께를 증가시킬 수 있어 커패시터와 콘택 플러그 사이의 장벽 특성을 향상시킬 수 있다.As described above, the present invention can form a diffusion barrier layer that is connected to the lower contact plug in the contact hole of the interlayer insulating layer by a simple plating method, and the thickness of the diffusion barrier layer can be increased according to the depth of the contact hole, so that the capacitor and the contact plug are separated. Can improve the barrier properties.
또, 본 발명은 확산 방지막이 층간 절연막에 매립된 형태이기 때문에 700℃ 이상의 고온 열처리를 필요로 하는 강유전체를 갖는 FeRAM소자의 열처리 공정시 확산 방지막의 열화를 초래하지 않고 공정을 진행할 수 있다. 이에 따라, 고집적 반도체장치에서 고용량을 달성하기 위해 강유전체 박막을 사용함에 있어 고온 공정이 가능하며 우수한 특성을 가진 커패시터의 구현이 가능하다.In the present invention, since the diffusion barrier is embedded in the interlayer insulating film, the process can be performed without causing deterioration of the diffusion barrier during the heat treatment of the FeRAM element having the ferroelectric, which requires a high temperature heat treatment of 700 ° C. or higher. As a result, in using the ferroelectric thin film to achieve a high capacity in a high density semiconductor device, a high temperature process is possible and a capacitor having excellent characteristics can be realized.
Claims (7)
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| KR100755373B1 (en) * | 2006-09-15 | 2007-09-04 | 삼성전자주식회사 | Contact structure having conductive oxide, ferroelectric random access memory device employing the same and methods of fabricating the same |
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| KR100668348B1 (en) * | 2005-11-11 | 2007-01-12 | 삼성전자주식회사 | Nonvolatile memory device and fabrication method of the same |
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| US5478772A (en) * | 1993-04-02 | 1995-12-26 | Micron Technology, Inc. | Method for forming a storage cell capacitor compatible with high dielectric constant materials |
| US5506166A (en) * | 1993-04-02 | 1996-04-09 | Micron Technology, Inc. | Method for forming capacitor compatible with high dielectric constant materials having a low contact resistance layer |
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