KR100510526B1 - Capacitor of semiconductor device and method for fabricating the same - Google Patents

Abstract

The capacitor of the semiconductor device according to the present invention is composed of a cylindrical capacitor lower electrode, a dielectric film, and an upper electrode, and the upper electrode is made of a metal film and an n-type doped poly Si _1-x Ge _x film stacked thereon. Is characteristic. The n-type doped poly Si _1-x Ge _x film can be deposited at low temperatures below 500 ° C, or activated at temperatures below 500 ° C, and therefore compared to capacitor processes that must now proceed at high temperatures above 600 ° C. Therefore, the degradation of the leakage current characteristic of the capacitor can be remarkably improved.

Description

Capacitor of semiconductor device and method of manufacturing the same {Capacitor of semiconductor device and method for fabricating the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a DRAM cell capacitor and a method for manufacturing the same, which can be applied to a highly integrated device.

As the degree of integration of semiconductor devices increases, there is a need to secure sufficient cell capacitance in a limited area, especially for semiconductor devices such as DRAM. To this end, studies are being actively conducted to use a high dielectric film made of a material having a dielectric constant several times to several hundred times larger than that of an oxide film / nitride film / oxide film, which is conventionally used as a capacitor dielectric film.

However, the doped polysilicon electrode, which is used as a capacitor upper / lower electrode in the related art, reacts with the high dielectric film to deteriorate the electrical characteristics of the capacitor. In order to prevent this, a method of additionally applying a low dielectric film such as a SiON film between the doped polysilicon electrode and the high dielectric film has also been proposed, but there is a limit in that the substantial thickness of the dielectric film is increased.

As a further improved method, a method of using a metal film that is less reactive than a polysilicon film is proposed for only the upper electrode of the capacitor using the high dielectric film, or both the upper electrode and the lower electrode. The term "metal film" is used herein to include not only a film made of a metal material itself but also a film made of a conductive oxide or a conductive nitride thereof. In contrast to the SIS (Semiconductor-Insulator-Semiconductor) capacitors that use both the upper and lower electrodes as doped polysilicon electrodes, they are referred to as metal-insulator-semiconductor (MIS) capacitors and metal-insulator-metal (MIM) capacitors, respectively.

However, in the case of the upper electrode made of a metal film, problems such as wet etch, dry etch, stress, etc., occur in the integration process, and because the resistivity is small, the resistance layer for signal delay ( There is also a problem that can not play the role of resistor layer). For this reason, the double film which laminated | stacked the doped polysilicon film on the metal film is used as an upper electrode. Here, the doped polysilicon film is formed by depositing amorphous silicon by LPCVD (Low Pressure Chemical Vapor Deposition) method and then activating heat treatment. There is a problem that current characteristics deteriorate.

FIG. 1 shows how leakage current characteristics deteriorate due to activation heat treatment of a doped polysilicon film in a conventional MIS capacitor. In FIG. 1, (a) shows the leakage current characteristic of the MIS capacitor which does not need to be heat treated using only the TiN film as the upper electrode. (b) shows the leakage current characteristics of the MIS capacitor using a double film in which a TiN film and an n-type doped polysilicon film are stacked as an upper electrode. In the case of (b), the n-type doped polysilicon film was deposited by LPCVD at 530 ° C. and heat-treated at 600 ° C. for 30 minutes in a furnace of N ₂ atmosphere.

From (a) and (b) of FIG. 1, in the case of (b) subjected to the activation heat treatment, it can be seen that the leakage current is greatly increased and Tox is also thicker. Therefore, it is necessary to develop the heat treatment conditions (furnace process of 600 degreeC, 30 minutes, or 650 degreeC, 2 minutes) of the n-type doped polysilicon film currently used by the process with low thermal budget.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a capacitor of a semiconductor device capable of low temperature process and having improved leakage current characteristics.

Another object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor device at a low temperature.

In order to achieve the above technical problem, a capacitor of a semiconductor device according to the present invention includes a cylindrical capacitor lower electrode formed on a semiconductor substrate, a dielectric film formed on the lower electrode surface, and an upper electrode formed on the dielectric film. The upper electrode is made of a metal film in contact with the dielectric film and an n-type doped poly Si _1-x Ge _x film stacked thereon.

A capacitor of another semiconductor device according to the present invention includes a cylindrical capacitor lower electrode formed on a semiconductor substrate and made of a metal film, a dielectric film formed on the lower electrode surface, and an n-type doped poly Si ₁ formed on the dielectric film. _-x Ge _x includes an upper electrode.

In order to achieve the above technical problem, in the method of manufacturing a capacitor of a semiconductor device, a cylindrical capacitor lower electrode is formed on a semiconductor substrate, and then a dielectric film is formed on the lower electrode surface. A metal film and an n-type doped poly Si _1-x Ge _x film are sequentially stacked on the dielectric layer to form an upper electrode formed of the metal film and the n-type doped poly Si _1-x Ge _x film.

In another method of manufacturing a capacitor of a semiconductor device according to the present invention, a cylindrical capacitor lower electrode made of a metal film is formed on a semiconductor substrate, and then a dielectric film is formed on the lower electrode surface. An n-type doped poly Si _1-x Ge _x upper electrode is formed on the dielectric layer.

As such, the upper electrode of the capacitor of the present invention includes an n-type doped poly Si _1-x Ge _x film. The n-type doped poly Si _1-x Ge _x film may be deposited or activated at a low temperature of 500 ° C. or lower. Therefore, since the current n-type doped polysilicon film is used, the degradation of the leakage current characteristics of the capacitor can be remarkably improved as compared to the capacitor process that must proceed at a high temperature of 600 ° C or higher.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited to the embodiments described below. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. Accordingly, the shape and the like of the elements in the drawings are exaggerated to emphasize a more clear description, and the elements denoted by the same reference numerals in the drawings means the same elements. In addition, where a layer is described as being "on" another layer or semiconductor substrate, a layer may exist in direct contact with the other layer or semiconductor substrate, or a third layer therebetween. Can be done.

First embodiment

2 to 7 are cross-sectional views illustrating a capacitor and a method of manufacturing the same according to the first embodiment of the present invention. The capacitor according to the first embodiment is a MIS capacitor whose lower electrode is a doped polysilicon film and the upper electrode is made of a TiN film and an n-type doped poly Si _1-x Ge _x film.

First, referring to FIG. 2, a plurality of contact plugs are formed on the semiconductor substrate 100 and then contact the impurity regions 105 of the semiconductor substrate 100 through the lower insulating layer 110. 115). An etch stop layer 120 made of, for example, silicon nitride is formed on the contact plug 115 and the lower insulating layer 110, and then boron phosphorus silicate glass (BPSG), phosphorus silicate glass (PSG), and plasma (PE) are formed. The mold oxide film 130 is formed by depositing an enhanced (ETE) -Tetra Ethyl Ortho Silicate (TEOS) or a High Density Plasma (HDP) -oxide.

Next, as shown in FIG. 3, the mold oxide film 130 is etched until the top surface of the etch stop layer 120 is exposed to form a mold oxide film pattern 130a. In this case, the etch stop layer 120 protects the lower insulating layer 110 from being etched. Subsequently, the etching process is performed to remove only the exposed etch stop layer 120, thereby forming a hole 135 exposing the top surface of the contact plug 115 and the lower insulating layer 110 around the contact plug 115. The etch stop layer pattern 120a remains under the mold oxide layer pattern 130a.

Referring to FIG. 4, the doped polysilicon film 140 is formed to a thickness that does not completely fill the hole 135. The doped polysilicon layer 140 may be a lower electrode of the capacitor, and may be formed by CVD or atomic layer deposition (ALD) having excellent step coverage. For example, polysilicon is deposited by a conventional LPCVD method and then PH ₃ doped thereon to ensure a resistivity to become n-type doped polysilicon.

5, a capping film 145 such as a USG (Undoped Silicate Glass) film having good gap fill characteristics is deposited on the doped polysilicon film 140 to fill the inside of the hole 135. Next, the capping film 145 and the doped polysilicon film 140 are removed by etch back or chemical mechanical polishing (CMP) until the top surface of the mold oxide film pattern 130a is exposed. ). In this way, the cylindrical capacitor lower electrodes 140a are separated from each other.

Next, as shown in FIG. 6, the capping layer 145 and the mold oxide layer pattern 130a are removed by wet etching to expose the surface of the lower electrode 140a, and then the dielectric layer 150 is formed on the surface. . If necessary, plasma nitridation or thermal nitridation using NH ₃ gas may be performed on the surface of the lower electrode 140a before forming the dielectric film 150. By this treatment, a silicon nitride film having a thickness of about 10-20 Å may be formed on the surface of the lower electrode 140a, which prevents a reaction that may occur between the lower electrode 140a and the dielectric film 150.

As the dielectric film 150, for example, an HfO ₂ film, an Al ₂ O ₃ film, or an Al ₂ O ₃ / HfO ₂ composite film can be formed. In order to form the dielectric film 150 as described above, CVD or ALD having excellent step coatability can be used. Particularly in the case of ALD, the deposition temperature can be kept close to 300 ° C, which is advantageous in terms of process temperature. In order to improve the electrical characteristics of the dielectric layer 150, a separate process may be further performed after the deposition of the dielectric layer 150. For example, the resultant on which the dielectric layer 150 is formed may be heat treated in an ozone (O ₃ ) treatment, a plasma treatment in a gas atmosphere containing oxygen or nitrogen, or a gas atmosphere containing oxygen or nitrogen.

Next, as shown in FIG. 7, the upper electrode 160 is formed on the dielectric film 150. In this case, the upper electrode 160 is formed by sequentially stacking the TiN film 152 and the n-type doped poly Si _1-x Ge _x film 154.

First, the TiN film 152 may be formed by CVD, ALD, or MOCVD (Metal Organic CVD). Instead of the TiN film 152, a WN, TaN, Cu, Al, or W film may be formed. Also, it may be formed of a noble metal such as Pt, Ir, Ru, Rh, Os, Pd, or an oxide film of such a noble metal, or may be formed of a combination of various metal films such as TiN / W, TiN / TaN, WN / W You may also The deposition temperature of these films is more effective when less than 500 ° C.

Next, an n-type doped poly Si _1-x Ge _x film 154 is formed on the TiN film 152, which is formed by doping P or As in situ while depositing the poly Si _1-x Ge _x film. . For this purpose, a facility such as a furnace type facility, a sheet type facility, or a mini batch containing 25 wafers may be used to implement a conventional LPCVD method. Of course, instead of the in situ method, it may be formed in two steps of doping P or As after poly Si _1-x Ge _x film deposition.

First, when forming Si _1-x Ge _{x film, SiH 4, Si 2 H 6} , SiH 2 Cl 2 , such as four days-series gas and GeH _4, using a gas such as GeF ₄ as a source gas, a temperature not higher than 500 ℃, For example, at a temperature in the range 400-500 ° C., preferably around 430 ° C. It may be initially formed in an amorphous state and then polycrystalline at the time of activation heat treatment, or may be initially formed in a polycrystalline and activated state. In the case of amorphous formation, the deposition temperature can be lowered up to 400 ° C. or lower, for example, in the range of 350-400 ° C., and the subsequent activation heat treatment temperature to 500 ° C. or lower, for example in the range of 400-500 ° C. Can be lowered.

The composition ratio (ie, x) of Si and Ge can be adjusted by the gas flow rate ratio. Although this composition ratio is not specifically limited, It is preferable to design with impurity concentration so that it may become a work function value in which at least a depletion layer is not formed. For example, 0.05? X? 0.9. More preferably, it is adjusted to be 0.2≤x≤0.6.

Doping with P or As, which is an n-type impurity, is to ensure specific resistance, and the doping concentration is, for example, about 3 × 10 ²⁰ / cm ³ . If the deposition temperature is lower than 400 ℃ through a heat treatment process to activate the doping impurities. However, unlike the prior art, the heat treatment temperature does not have to exceed 500 ° C. As a result, the capacitor 190 including the lower electrode 140a, the dielectric layer 150, and the upper electrode 160 is manufactured at a relatively low temperature of 500 ° C. or less.

Since the melting point of Si _1-x Ge _x is lower than that of silicon, physical phenomena such as deposition, crystallization, grain growth, and impurity activation also occur at lower temperatures than silicon. In the present invention, the process temperature can be lowered to 500 ° C or lower by applying n-type doped poly Si _1-x Ge _x to the upper electrode instead of the conventional polysilicon, thereby reducing leakage current characteristics of the MIS capacitor. It can be greatly improved.

Second embodiment

8 is a cross-sectional view for describing a capacitor and a method of manufacturing the same according to the second embodiment of the present invention. In FIG. 8, the same elements as in the first embodiment are denoted by the same reference numerals as in FIGS. 1 to 7, and overlapping descriptions are omitted. The second embodiment explains that the n-type doped poly Si _1-x Ge _x top electrode of the present invention can also be applied to a MIM capacitor.

In the capacitor 290 illustrated in FIG. 8, the lower electrode 240a is a metal film, and the upper electrode 160 is formed of a TiN film 152 and an n-type doped poly Si _1-x Ge _x film 154. The lower electrode 240a may be formed by depositing and planarizing a TiN, WN, TaN, Cu, or W film by CVD, ALD, or MOCVD on the mold oxide film pattern as in the first embodiment. As the metal film that can be used for the lower electrode 240a, in addition to these films, precious metals such as Pt, Ir, Ru, Rh, Os, and Pd, oxides of such precious metals, or TiN / W, TiN / TaN, WN / W, etc. Metal multilayers, etc. in the form.

When the metal film is used as the lower electrode 240a, in addition to the HfO ₂ film, Al ₂ O ₃ film, Al ₂ O ₃ / HfO ₂ composite film, the HfO ₂ / Al ₂ O ₃ film, SrTiO ₃ film, or the like as the dielectric film 250, The (Ba, Sr) TiO ₃ film can be used.

In the case of the MIM capacitor 290 thus configured, as in the first embodiment, the n-type doped poly Si _1-x Ge _x film 154 is applied to the upper electrode instead of the conventional polysilicon. The temperature can be lowered below 500 ° C.

Third embodiment

9 is a cross-sectional view for describing a capacitor and a method of manufacturing the same according to a third embodiment of the present invention. In Fig. 9, the same elements as in the first and second embodiments are denoted by the same reference numerals as in Figs. 1 to 8, and overlapping descriptions are omitted.

As shown in FIG. 9, the upper electrode 360 is made of only a single film of an n-type doped poly Si _1-x Ge _x film. Here too, the range of x of the n-type doped poly Si _1-x Ge _x film is 0.05 ≦ x ≦ 0.9, or more preferably 0.2 ≦ x ≦ 0.6.

In this case, it is preferable to use a metal film as the lower electrode 240a of the capacitor 390. As described in the second embodiment, the metal film may be made of precious metals such as WN, TaN, Cu, Al, W or Pt, Ir, Ru, Rh, Os, Pd, oxides of such precious metals, and the like, in addition to TiN. Or a combination of such films, such as TiN / W, TiN / TaN, WN / W, and the like.

More detailed information about the present invention will be described through the following specific experimental examples, and details not described herein will be omitted because it can be inferred technically by those skilled in the art. In addition, the following experimental examples are not intended to limit the present invention.

Experimental Example 1

In order to use the upper electrode of the capacitor of the present invention, P doping was performed in situ while depositing a poly Si _1-x Ge _x film by using a sheet type facility at 500 ° C. and 275 torr. SiH ₄ and GeH ₄ were used as source gases, but poly Si _1-x Ge _x films were deposited for 4-5 minutes with different GeH ₄ flow rates. GeH ₄ was supplied by diluting with hydrogen or nitrogen at 10% (hereinafter referred to as 10% GeH ₄ ). The P doping concentration was about 3 × 10 ²⁰ / cm ³ , and no heat treatment was performed on the resulting n-type doped poly Si _1-x Ge _x film.

10 is a graph showing the resistivity characteristics of the in _- situ n-type doped poly Si _1-x Ge _x with increasing GeH ₄ flow rate. In FIG. 10, the horizontal axis represents the ratio of 10% GeH ₄ to SiH ₄ , and the vertical axis represents the specific resistance. As can be seen in FIG. 10, the resistivity of the n-type doped poly Si _1-x Ge _x decreases with GeH ₄ flow rate. From the resistivity of FIG. 10, the deposition conditions at 500 ° C. and 275 torr were confirmed to result in in situ n-type doped poly Si _1-x Ge _x activated simultaneously with deposition.

Accordingly, when the SiH ₄ and GeH ₄ are used at 500 ° C. and 275torr deposition conditions using the source gas, the post-activation subsequent heat treatment may be omitted unlike the existing process. It has been reported that the temperature of the transition from amorphous to polycrystalline during silicon deposition decreases with the decrease in pressure, which is more likely when using mini batches (approximately 4 Torr) or furnace type LPCVD equipment (approximately 1 Torr or less), which have lower pressure than single-sheet equipment. It is expected that deposition of in situ n-type doped poly Si _1-x Ge _x at low temperatures will be possible.

Experimental Example 2

The ALD method was used to form a cylindrical lower electrode shape with a polysilicon film, and then a doping polysilicon was formed by performing PH ₃ doping thereon. Plasma nitride treatment using NH ₃ gas was performed on the surface of the doped polysilicon lower electrode, and the silicon nitride film having a thickness of about 16 kHz was formed by performing about 20 seconds at an RF power of 300 W at 790 ° C. An HfO ₂ film was formed thereon at about 45 kHz as a dielectric film. As the source gas, [Hf (NEtMe) ₄ ] and O ₃ called TEMAH were used, and the ALD method using Ar bubbling at 300 ° C was used.

Next, a TiN film was formed on the HfO ₂ film at 450 ° C. by the ALD method. TiCl ₄ and NH ₃ were used as the source gas, and the deposition temperature did not exceed 500 ° C. On top of that, an in-situ n-type doped poly Si _1-x Ge _x film was laminated with the conditions given below to form an upper electrode composed of a TiN film and an in-situ n-type doped poly Si _1-x Ge _x film. It was.

P doping at a concentration of about 3 × 10 ²⁰ / cm ³ was performed in situ while depositing a poly Si _1-x Ge _x film using a sheet type facility at 470 ° C. and 275torr. SiH ₄ and GeH ₄ were used as the source gas and the deposition was carried out in two stages: seeding and main deposition.

The seeding step without GeH ₄ to SiH ₄ It was supplied for about 50 seconds at a flow rate of 50 sccm. At this time, 6 sccm of 1% diluted PH ₃ (hereinafter designated as 1% PH ₃ ) as a P doping source was supplied. The flow rate of N _{2 which} is a carrier gas was about 9000 sccm. In the main deposition step, the flow rate of SiH ₄ was increased to 80 sccm and 10% GeH _{4 was} also supplied at 240 sccm. The flow rates of 1% PH ₃ and N ₂ were kept the same as the seeding step. The main deposition step time was around 110 seconds. This gives an x value of about 0.2. Hydrogen or nitrogen was used to dilute PH ₃ and GeH ₄ . The resulting n-type doped poly Si _1-x Ge _x film was not subjected to a separate heat treatment.

11 is a graph measuring leakage current of the capacitor thus manufactured. Leakage current is very low than in the case of (b) in Figure 1, it can be confirmed that almost similar to the case of (a), Tox was also measured as 20.5 Å similar to (a). Accordingly, it can be seen that an n-type doped poly Si _1-x Ge _x film having characteristics as an upper electrode can be obtained without additional heat treatment.

This excellent result was also obtained by depositing an in _- situ doped poly Si _1-x Ge _x film for about 65 minutes using an LPCVD furnace at 470 ° C. and 0.45 torr.

Experimental Example 3

A capacitor was prepared under similar conditions as in Experimental Example 2. However, various Tox results were obtained by varying only the conditions under which the HfO ₂ film was deposited. In order to compare with the results of the present invention, as shown in (b) of FIG. 1, a capacitor using a double film of a TiN film and an n-type doped polysilicon film heat-treated at 600 ° C. for 30 minutes was manufactured.

FIG. 12 is a graph showing the leakage current with respect to Tox at 1.2V in the capacitors thus manufactured. In FIG. 12, the dotted line indicates the result of the capacitor according to the present invention, and the solid line indicates the result of the conventional capacitor as shown in FIG.

As can be seen in Figure 12, even under the same Tox condition, the leakage current is smaller in the case of the present invention. Also, in the case of the same leakage current condition, Tox is smaller in the case of the present invention. Therefore, in the case of the present invention, it can be seen that the leakage current and the Tox are both smaller than the conventional ones, so that a capacitor having excellent characteristics is manufactured.

As mentioned above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical idea of the present invention. It is obvious.

According to the present invention described above, an upper electrode is formed by stacking a metal film such as a TiN film and an n-type doped poly Si _1-x Ge _x film, or a lower electrode made of a metal film and an n-type doped poly Si _1. Capacitors are fabricated by forming a top electrode made of _-x Ge _x film. The n-type doped poly Si _1-x Ge _x film can be deposited at a low temperature below 500 ° C, or activated at a temperature below 500 ° C. In comparison, the degradation of the leakage current characteristic of the capacitor can be remarkably improved.

1 is a graph showing a problem of leakage current characteristics deteriorated due to activation heat treatment of an n-type doped polysilicon film in a conventional metal-insulator-semiconductor (MIS) capacitor.

2 to 7 are cross-sectional views illustrating a MIS capacitor and a method of manufacturing the same according to a first embodiment of the present invention.

8 is a cross-sectional view for describing a metal-insulator-metal (MIM) capacitor and a method of manufacturing the same according to a second embodiment of the present invention.

9 is a cross-sectional view for describing a MIM capacitor and a method of manufacturing the same according to a third embodiment of the present invention.

10 is a graph showing the resistivity characteristics of the in _- situ n-type doped poly Si _1-x Ge _x with increasing GeH ₄ flow rate.

11 is a graph showing the cell leakage current measured for the MIS capacitor manufactured according to the present invention.

12 is a graph showing a cell leakage current measured with respect to Tox for the conventional MIS capacitor and the MIS capacitor manufactured according to the present invention.

* Description of the symbols for the main parts of the drawings

100 ... semiconductor substrate 140 ... doped polysilicon film

140a, 240a ... lower electrode 150, 250 ... dielectric film

152 ... TiN film 154 ... n-type doped poly Si _1-x Ge _x film

160, 360 ... upper electrode 190 ... MIS capacitor

290, 390 ... MIM Capacitors

Claims (36)

delete A cylindrical capacitor lower electrode formed on the semiconductor substrate and made of a doped polysilicon film; A dielectric film formed on the surface of the lower electrode; And An upper electrode formed on the dielectric layer, And the upper electrode is formed of a metal film in contact with the dielectric film and an n-type doped poly Si _1-x Ge _x film stacked thereon. 3. The capacitor of claim 2, wherein the dielectric film is an HfO ₂ film, an Al ₂ O ₃ film, or an Al ₂ O ₃ / HfO ₂ composite film. A cylindrical capacitor lower electrode formed on the semiconductor substrate and formed of a metal film; A dielectric film formed on the surface of the lower electrode; And An upper electrode formed on the dielectric layer, And the upper electrode is formed of a metal film in contact with the dielectric film and an n-type doped poly Si _1-x Ge _x film stacked thereon. 5. The dielectric film of claim 4, wherein the dielectric film comprises an HfO ₂ film, an Al ₂ O ₃ film, an Al ₂ O ₃ / HfO ₂ composite film, an HfO ₂ / Al ₂ O ₃ film, an SrTiO ₃ film, and a (Ba, Sr) TiO ₃ film. Capacitor of a semiconductor device, characterized in that any one selected from the group. 5. The capacitor of claim 2 or 4, wherein the n-type doped poly Si _1-x Ge _x film is doped with P or As. The capacitor of claim 2 or 4, wherein 0.05≤x≤0.9. The semiconductor device capacitor according to claim 2 or 4, wherein 0.2≤x≤0.6. 5. The capacitor of claim 2 or 4, wherein the metal film in the upper electrode is TiN. The semiconductor according to claim 2 or 4, wherein the metal film of the upper electrode is any one selected from the group consisting of TiN, WN, TaN, Cu, W, Al, precious metals, precious metal oxides, and combinations thereof. Capacitors in the device. delete delete delete delete delete delete Forming a cylindrical capacitor lower electrode formed of a doped polysilicon film or a metal film on the semiconductor substrate; Forming a dielectric film on the lower electrode surface; And The metal film and the n- type doping agent poly Si _1-x Ge _x sequentially laminated film on the dielectric layer and forming a top electrode made of a metal film and an n- type doped poly-bit _1-x Ge _x film Si Capacitor manufacturing method of a semiconductor device, characterized in that. 18. The method of claim 17, wherein the n-type doped poly Si _1-x Ge _x film is formed by doping a poly Si _1-x Ge _x film with P or As. 18. The method of claim 17, wherein the n-type doped poly Si _1-x Ge _x film is formed by doping P or As in-situ while depositing a poly Si _1-x Ge _x film. Method for manufacturing a capacitor of a semiconductor device. 18. The method of claim 17, wherein the n-type doped poly Si _1-x Ge _x film is formed to be activated simultaneously with deposition. 21. The method of claim 20, wherein the temperature when depositing the n-type doped poly Si _1-x Ge _x film is 350-500 ° C. 18. The method of claim 17, wherein the n-type doped poly Si _1-x Ge _x film is formed by activation heat treatment after deposition. 23. The method of claim 22, wherein the temperature during activation heat treatment of the n-type doped poly Si _1-x Ge _x film is 400-500 ° C. 18. The method of claim 17, wherein the metal film of the upper electrode is formed of TiN. 18. The capacitor of claim 17, wherein the metal layer of the upper electrode is formed of any one selected from the group consisting of TiN, WN, TaN, Cu, W, Al, precious metals, precious metal oxides, and combinations thereof. Manufacturing method. 18. The method of claim 17, wherein the doped poly Si _1-x Ge _x film is a low pressure chemical vapor deposition (LPCVD) method using a furnace type facility, a sheetfed facility, or a mini batch facility containing 25 wafers. A capacitor manufacturing method of a semiconductor device, characterized in that formed by. Forming a cylindrical capacitor lower electrode formed of a metal film on the semiconductor substrate; Forming a dielectric film on the lower electrode surface; And And forming an n-type doped poly Si _1-x Ge _x upper electrode at 350-500 ° C. on the dielectric layer. 28. The method of claim 27, wherein the n-type doped poly Si _1-x Ge _x film is formed by doping a poly Si _1-x Ge _x film with P or As. 28. The capacitor fabrication of claim 27, wherein the n-type doped poly Si _1-x Ge _x film is formed by doping P or As in-situ while depositing a poly Si _1-x Ge _x film. Way. 28. The method of claim 27, wherein the n-type doped poly Si _1-x Ge _x film is formed to be activated simultaneously with deposition. delete 28. The method of claim 27, wherein the n-type doped poly Si _1-x Ge _x film is formed by activation heat treatment after deposition. 33. The method of claim 32, wherein the activation heat treatment of the n-type doped poly Si _1-x Ge _x film is performed at 400-500 ° C. 28. The method of claim 27, wherein the metal film of the upper electrode is formed of TiN. 28. The capacitor of claim 27, wherein the metal film of the upper electrode is formed of any one selected from the group consisting of TiN, WN, TaN, Cu, W, Al, precious metals, precious metal oxides, and combinations thereof. Manufacturing method. 28. The method of claim 27, wherein the doped poly Si _1-x Ge _x film is a low pressure chemical vapor deposition (LPCVD) method using a furnace type facility, a sheetfed facility, or a mini batch facility containing 25 wafers. A capacitor manufacturing method of a semiconductor device, characterized in that formed by.