KR20010008412A - Method for manufacturing capacitor of semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a capacitor is provided to prevent a storage electrode from being oxidized in a thermal oxide process of a Ta2O5 thin film while increasing a surface area of the storage electrode, by using a tungsten silicide layer as a layer for the storage electrode. CONSTITUTION: A plug(121) connected to a semiconductor device or predetermined region of the semiconductor device through a contact hole of an interlayer dielectric(110) for isolation between devices is formed on a semiconductor substrate(100) having the semiconductor device. A storage electrode composed of a conductive layer including a tungsten silicide layer(122) is formed, contacting the plug. A Ta2O4 thin film as a dielectric material between electrodes is formed on an upper surface of the storage electrode. A plate electrode composed of a conductive layer including a metal layer is formed on the Ta2O4 thin film.

Description

Capacitor Manufacturing Method of Semiconductor Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor manufacturing method of a semiconductor device, and more particularly, to a capacitor manufacturing method of a semiconductor device capable of improving electrical characteristics of a capacitor of a highly integrated semiconductor device.

At present, in order to achieve high integration of semiconductor devices, research / development has been actively conducted on reduction of cell area and reduction of operating voltage. In addition, as the integration of semiconductor devices increases, the area of the capacitor is rapidly decreasing, and thus, the charge required for the operation of the memory device, that is, the capacitance secured in the unit area, must be further increased.

Meanwhile, the basic structure of a capacitor used in a memory cell is composed of a lower electrode for a storage node, a dielectric film, and an upper electrode that is a plate node. Capacitors having such a structure have a first thin dielectric film thickness to increase the high capacitance in a small area, increase the effective area through the structure of a three-dimensional capacitor, or use a dielectric material having a high dielectric constant. Several conditions must be met, such as forming a film.

Capacitors in semiconductor devices generally obtain better dielectric films with less leakage current and larger breakdown voltages at a given dielectric film thickness, but Fowler-Nordheim when the dielectric film becomes thinner than 100 Å. ) The leakage current increases due to tunneling, which lowers the reliability. In addition, when the cross-sectional area of the lower electrode is increased by using a three-dimensional structure to increase the effective area of the capacitor, the manufacturing process becomes difficult due to the complicated structure resulting from the high integration of the semiconductor device. For this reason, the capacitor used in the memory cell mainly uses a method having a high dielectric constant as a dielectric film of the capacitor so that a high capacitance can be secured even in a small area. ₂ , Ta ₂ O ₅ and the like, among these, the method for producing a capacitor having Ta ₂ O ₅ is as follows.

FIG. 1 is a vertical cross-sectional view illustrating a structure of a metal / insulator / silicon (MIS) capacitor having a Ta ₂ O ₅ thin film having a high dielectric constant. In general, a capacitor 30 formed in a semiconductor memory device is manufactured according to a conventional manufacturing process. A lower electrode 32 made of polysilicon doped with impurities and contacting the active region of the semiconductor substrate 10 through the contact hole of the interlayer insulating film 20, and a Ta ₂ O ₅ thin film 34 stacked thereon as a high dielectric material. And an upper electrode 38 on which a thin titanium nitride film TiN and a doped polysilicon layer are stacked.

The capacitor has a silicon nitride film (Si ₃ N ₄ ) to a silicon nitride oxide film (SiO x N y) 33 because the capacitor is nitrided to increase the surface oxidation stability of the lower electrode 32.

Meanwhile, the deposition process of the Ta ₂ O ₅ thin film 34 is performed by Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), Ultra Violet (UV)-photo-CVD, and Radio Frequence (RF) magnetic sputtering ( magnetic sputtering, etc. Recently, PECVD is used to improve the quality of Ta ₂ O ₅ thin film or LPCVD method which is relatively low in quality but excellent in step coverage. .

However, regardless of which method is used, since the Ta ₂ O ₅ thin film 34 itself has an unstable stoichiometry, substitutional Ta atoms due to differences in the composition ratios of Ta and O are produced. It is present in the thin film. And carbon atoms, carbon compounds (C, CH _4, etc.) and water (H) that are impurities due to the reaction of the organic material of Ta (OC ₂ H ₅ ) ₅ , which is a raw material source of Ta ₂ O ₅ , with O ₂ (or N ₂ O) gas. ₂ 0) will also be present. Therefore, the leakage current of the capacitor increases due to carbon atoms, ions, and radicals present as impurities in the Ta ₂ O ₅ thin film 34, and dielectric characteristics This has a problem of deterioration.

In order to improve such electrical characteristics, a high temperature annealing process is further performed in an O ₂ , N ₂ O or UV-O ₃ atmosphere after Ta2O ₅ thin film deposition, but when the capacitor 30 structure is MIS, the lower electrode Since polysilicon is contained, a natural oxide film (SiO ₂ ) having a low dielectric constant is formed between the silicon of the lower electrode 32 and the interface of the Ta ₂ O ₅ thin film 34 by this process. Then, although the dielectric constant? Of the Ta 2 O ₅ thin film 34 is 20 to 25, about 15 to 20 mA is oxidized at the interface of the lower electrode 32, the capacitance is greatly reduced.

Furthermore, when the surface area of the lower electrode 32 is increased to increase the capacitance, low P concentration amorphous silicon must be used to form HSG (HemiSpherial Grain) of low P (hosphorous) concentration to have an uneven structure on the surface of the lower electrode. In this case, the difference in the number of main carrier atoms from the titanium nitride film (TiN) 36, which is the upper electrode used as the metal diffusion barrier layer, is significantly different.

Then, as shown in the graph of FIG. 2 showing a correlation in which the capacitance of the conventional MIS capacitor changes according to the voltage magnitude, it can be seen that the capacitance ΔC decreases in the MIS capacitor at the negative voltage due to the difference in the main carriers. .

In order to overcome this problem, a capacitor having a high dielectric constant Ta2O ₅ thin film should be changed to a metal / insulator / metal (MIM) structure in which the lower electrode is also made of metal. However, in general, tungsten (W), tungsten nitride (WN), and tantalum nitride film In the case of (TaN), there is a limit in achieving the high capacitance required in the semiconductor memory device because it cannot be formed as an uneven surface for increasing the surface area of the lower electrode.

An object of the present invention is to be deposited in an amorphous state in order to solve the problems of the prior art as described above, and the surface can be formed into an uneven shape because the phase transition is possible through a subsequent thermal process such as amorphous silicon in a subsequent heat treatment process. By using tungsten silicide (WSix) as the film of the lower electrode, to provide a method of manufacturing a capacitor of a semiconductor device that can increase the surface area of the lower electrode while preventing the oxidation of the lower electrode generated during the thermal oxidation process of the Ta2O ₅ thin film. .

1 is a vertical cross-sectional view for explaining the structure of a MIS capacitor having a high dielectric constant Ta2O ₅ thin film,

2 is a graph showing a correlation in which the capacitance of a conventional MIS capacitor is changed according to a voltage magnitude;

3A to 3F are vertical cross-sectional views sequentially illustrating a MIM capacitor manufacturing process of a semiconductor device according to the present invention;

* Description of symbols on the main parts of the drawings *

100: silicon substrate 110: interlayer insulating film

121: plug 122: tungsten silicide film

122 ': tungsten silicide pattern 124: uneven structure of the lower electrode

126: Ta2O ₅ thin film 128: titanium nitride film

129: doped polysilicon film

b: lower electrode u: upper electrode

In order to achieve the above object, the present invention provides a semiconductor substrate including a semiconductor device in manufacturing a capacitor of a semiconductor device comprising a lower electrode for charge storage, an upper electrode thereon, and a high-k dielectric Ta2O ₅ thin film embedded in the electrodes. Forming a plug connected to any region of the semiconductor device or the semiconductor device through a contact hole of an interlayer insulating film for insulating between devices, and forming a lower electrode made of a conductive layer including tungsten silicide in contact with the plug And forming a Ta2O ₅ thin film as an inter-electrode dielectric on the upper surface of the lower electrode, and forming an upper electrode including a conductive layer including a metal film on the upper surface of the Ta2O ₅ thin film.

In the manufacturing method of the present invention, the plug forming step is to bury the doped polysilicon or tungsten silicide in the contact hole of the interlayer insulating film, and then polish the surface by the planarization step, and the forming of the lower electrode deposits tungsten silicide and After patterning this to form a pattern of the lower electrode, characterized in that the annealing in a reaction chamber temperature of more than 600 ℃ and N ₂ , Ar or He gas atmosphere.

In the manufacturing method of the present invention, after forming the lower electrode, 20 sccm (standard cubic centimeter per minute) of SiH ₄ / Si ₂ H ₆ gas is used in a reaction chamber of 10 ^-6 Torr and a wafer temperature of 500 to 600 ° C. The method may further include forming a surface of the lower electrode in a concave-convex structure by making the seed on the surface of the lower electrode to be less than and performing an annealing process at the same temperature.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A to 3F are vertical cross-sectional views sequentially illustrating a MIM capacitor manufacturing process of a semiconductor device according to the present invention.

First, as a semiconductor substrate, a semiconductor device (not shown) having a gate electrode and a source / drain is formed on an upper surface of an active region of a silicon substrate, and USG (Undoped Silicate Glass) and BPSG (Boro Phospho Silicate Glass) are formed on the entire surface of the substrate. And depositing a material selected from SiON and performing a chemical mechanical polishing process to form a planarized interlayer insulating film, so as to secure a cross-sectional area of the capacitor in contact with the active region of the substrate, that is, the drain region of the device. And selectively etching the interlayer insulating layer through an etching process to form a contact hole (not shown).

Next, as shown in FIG. 3A, a plug 121 for depositing amorphous and impurity doped silicon is sufficiently filled with the contact hole of the interlayer insulating film 110 and performing a chemical mechanical polishing process to fill the contact hole. To form. Next, a tungsten silicide film (WSix) 122 is deposited on the entire interlayer insulating film 110.

Instead of the plug polysilicon plug process as described above, the plug is deposited by 0.5 to 1 μm so that the tungsten silicide layer 122 is buried in the contact hole of the interlayer dielectric layer 110 in the SiH ₄ + WF ₆ atmosphere by LPCVD. May be formed. In this process, SiH ₄ gas is flowed into the reaction chamber with 300 to 500 sccm and WF ₆ gas is about 1 to ₅ sccm, and a reaction chamber pressure of 1 Torr or less and a wafer of 300 to 500 ° C. are used to cause a chemical phase reaction. Deposit in an amorphous state at temperature. However, the reaction gases may be increased or decreased depending on the chamber size.

Subsequently, as shown in FIG. 3B, a photoresist pattern 123 is coated on the tungsten silicide layer 122 to form a lower electrode having a simple stacked structure, and an etching process is performed on the pattern 123. The film 122 is then patterned to form a tungsten silicide pattern 122 '.

After removing the photoresist pattern 123, as shown in FIG. 3c, the resultant is washed using a dilute chemical solution containing HF solution.

Next, as shown in FIG. 3D, the amorphous tungsten silicide pattern 122 ′ is annealed at a reaction chamber temperature of 600 ° C. or higher and N ₂ / Ar / He gas atmosphere. Then, the tungsten silicide film is tetragonal in an amorphous state, and seeds are generated by excess silicon atoms (Si) in the film, so that the surface of the pattern 122 'is uneven (124). Will have As a result, a lower electrode b having an HSG structure having a larger surface area is formed.

In addition, the process for forming the lower electrode (b) of the HSG structure as described above is a gas for forming a seed instead of the annealing process by flowing SiH ₄ to Si ₂ H ₆ 20 sccm or less into the reaction chamber into the chemical phase reaction To achieve this, the seeding process was performed under a pressure of 10 ⁻⁶ Torr or less and a wafer temperature of 500 to 700 ° C., and the annealing process was performed in the same reaction chamber where only gas was blocked. Can be achieved.

3E, a Ta ₂ O ₅ film 126, which is an inter-electrode dielectric, is formed on the lower electrode b by LPCVD using Ta (OC ₂ H ₅ ) ₅ and O ₂ gas. Then, post-treatment is performed to enhance the film quality of the Ta ₂ O ₅ film 126 and to remove impurities in the oxygen space and the carbon atom series in the film 126. At this time, the post-treatment process is performed by selecting any one or two or more of low temperature O ₂ to N ₂ O plasma treatment, high temperature O ₂ to N ₂ O heat treatment, UV-O ₃ .

Thereafter, as illustrated in FIG. 3F, a thermal oxidation process is performed on the resultant, and a titanium nitride layer (TiN) is formed on the Ta ₂ O ₅ thin film 126 by chemical vapor deposition (CVD) using TiCl ₄ . It is deposited by about ~ 1000Å to form a single layer of the upper electrode.

However, in the present embodiment, in order to reduce internal stress caused by oxidation and phase transition of the titanium nitride film TiN, which may occur during a high temperature process, the upper electrode u is doped with a titanium nitride film 128 and an impurity doped polysilicon layer 129. ) Is a laminated structure. Thus, TiCl ₄ was deposited on the amorphous Ta ₂ O ₅ thin film 126 by the chemical vapor deposition method at about 100 to 500 mW, and the impurity-doped polysilicon layer 129 was deposited thereon at about 500 mW to 1000 mW. The upper electrode u is completed.

Therefore, in the capacitor manufacturing method of the present invention, when the annealing process is performed after depositing the amorphous tungsten silicide film 122 'with the material of the lower electrode b, the tungsten silicide film 122' is the same as the silicon in the amorphous state. Since phase transition is possible, the surface of the tungsten silicide film 122 'has an uneven shape. After forming the uneven lower electrode b, a capacitor is formed by depositing a Ta ₂ O ₅ thin film 126 as a dielectric and an upper electrode u having a titanium nitride film 128 to a titanium nitride film and a polysilicon layer stacked thereon. When the process is performed, a capacitor having a MIM structure having a Ta ₂ O ₅ thin film capable of securing a high capacitance while simultaneously increasing the surface area of the lower electrode b can be realized.

When a Ta ₂ O ₅ capacitor having a MIS structure according to the prior art deposits a Ta ₂ O ₅ thin film, a natural oxide film having a low dielectric constant (ε = 4 to 5) is formed at an interface of polysilicon of the lower electrode to about 10 to 20 kV. Therefore, although the dielectric Ta ₂ O ₅ thin film has a high dielectric constant (ε = 20 to 25), the capacitance was improved by about 1.5 times that of the capacitor having the dielectric of the nitride / oxide film. However, when the capacitor manufacturing method having the Ta ₂ O ₅ of the MIM structure according to the present invention is used as described above, the tungsten silicide film is deposited since the tungsten silicide film is deposited in an amorphous state when the lower electrode is formed and the subsequent heat treatment process is performed. The surface becomes irregular and eventually increases the surface area of the lower electrode. As a result, the capacitor of the present invention can secure the capacitance at least twice as large as that of the capacitor of the conventional MIS structure.

In addition, tungsten silicide used as the lower electrode of the present invention is widely used as a word line and a bit line in a general device, and annealing or seed gas (Si ₂ H ₆ / SiH ₄ ) after deposition in an amorphous state such as polysilicon. After passing through the annealing, the HSG lower electrode can be easily obtained, so even if the capacitor is a simple stacked type, it is possible to secure the capacitance of 25 fF / cell or more required for a DRAM of 256 M or more. In addition, in the present invention, since the lower electrode uses the same metal as the metal material of the upper electrode, even if a negative voltage is applied to the semiconductor device, the difference in the main carrier is not large, so that the capacitance is not reduced, and the high capacitance is ensured. In order to form a three-dimensional (Cylinder Crown) capacitor, the semiconductor device can be directly connected directly.

In addition, since the tungsten silicide used as the lower electrode in the present invention is more stable in terms of oxidation resistance than the polysilicon used as the lower electrode in the prior art, the lower electrode is oxidized due to a subsequent thermal oxidation process after forming a Ta ₂ O ₅ thin film. There is no need to perform a separate nitriding process such as Rapid Thermal Nitridation (RTN) to prevent the damage, thereby reducing the number of related unit processes such as a pretreatment cleaning process.

Claims (6)

In manufacturing a capacitor of a semiconductor device comprising a lower electrode for charge storage, an upper electrode thereon, and a high-k dielectric Ta2O ₅ thin film embedded in the electrodes, Forming a plug connected to any one region of the semiconductor device to the semiconductor device through a contact hole of an interlayer insulating film for inter-device insulation between the semiconductor substrates having the semiconductor device; Forming a lower electrode in contact with the plug and including a conductive layer including tungsten silicide; Forming a Ta ₂ O ₅ thin film as an inter-electrode dielectric on an upper surface of the lower electrode; And And forming an upper electrode formed of a conductive layer including a metal film on an upper surface of the Ta ₂ O ₅ thin film. The method of claim 1, wherein the plug forming step, And embedding doped polysilicon or tungsten silicide in the contact hole of the interlayer insulating film, and then polishing the surface thereof by a planarization process. The method of claim 1, wherein the forming of the lower electrode, After depositing and patterning the tungsten silicide to form a pattern of the lower electrode, the method of manufacturing a capacitor of a semiconductor device, characterized in that the annealing in a reaction chamber temperature of 600 ℃ or more and N ₂ , Ar or He gas atmosphere. The method of claim 3, wherein the tungsten silicide deposition process, A method of manufacturing a capacitor of a semiconductor device, characterized in that it is carried out by any one of PECVD, LPCVD, UV-photo-CVD, RF magnetic sputtering. The method of claim 1, wherein after forming the lower electrode, SiH ₄ / Si ₂ H ₆ gas is less than 20 sccm in the reaction chamber at 10 ^-6 Torr and the wafer temperature is 500 ~ 600 ℃, and the bottom electrode surface is annealed at the same temperature. Capacitor manufacturing method of a semiconductor device characterized in that it further comprises the step of forming a concave-convex structure. The method of claim 1, wherein the conductive layer constituting the upper electrode, A method of manufacturing a capacitor of a semiconductor device, wherein a single metal film, a thin titanium nitride film, and a polysilicon film doped with impurities are sequentially formed.