KR100342868B1 - Method of forming capacitor - Google Patents
Method of forming capacitor Download PDFInfo
- Publication number
- KR100342868B1 KR100342868B1 KR1019990064618A KR19990064618A KR100342868B1 KR 100342868 B1 KR100342868 B1 KR 100342868B1 KR 1019990064618 A KR1019990064618 A KR 1019990064618A KR 19990064618 A KR19990064618 A KR 19990064618A KR 100342868 B1 KR100342868 B1 KR 100342868B1
- Authority
- KR
- South Korea
- Prior art keywords
- nitride film
- lower electrode
- film
- capacitor
- forming
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000003990 capacitor Substances 0.000 title claims abstract description 17
- 150000004767 nitrides Chemical class 0.000 claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 claims abstract description 20
- 238000004140 cleaning Methods 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 238000009832 plasma treatment Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 239000007789 gas Substances 0.000 claims description 7
- 239000007769 metal material Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000011065 in-situ storage Methods 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 239000012495 reaction gas Substances 0.000 claims description 2
- 238000004381 surface treatment Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 45
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000004020 conductor Substances 0.000 description 3
- 238000005121 nitriding Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 125000004437 phosphorous atom Chemical group 0.000 description 2
- 229910015801 BaSrTiO Inorganic materials 0.000 description 1
- 229910002651 NO3 Inorganic materials 0.000 description 1
- NHNBFGGVMKEFGY-UHFFFAOYSA-N Nitrate Chemical compound [O-][N+]([O-])=O NHNBFGGVMKEFGY-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- High Energy & Nuclear Physics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Toxicology (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Health & Medical Sciences (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
본 발명은 N/O 구조의 유전막을 갖는 커패시터 제조방법에 관한 것으로서, 특히 이 방법은 반도체기판에 하부전극을 형성하며, 하부전극 표면에 P를 축적시키고 동일한 챔버에서 NH3가스를 이용한 플라즈마 트리트먼트 공정을 실시하여 축적된 P를 질화시켜 제 1질화막을 형성하며, 제 1질화막 상부에 제 2질화막을 형성하며, 제 2질화막 상부에 산화막을 형성한 후에 상부전극을 형성한다. 이에 따라, 본 발명은 유전막 제조 공정 이전에 습식 세정 공정을 생략할 수 있어 세정 공정으로 인한 하부전극의 도핑 상태의 캐리어 손실을 방지할 수 있고 MPS 그레인의 성장도에 따라 취약해진 좁은 통로 부위의 그레인의 파단을 미연에 방지할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor having a dielectric film having an N / O structure. In particular, the method includes forming a lower electrode on a semiconductor substrate, accumulating P on the lower electrode surface, and plasma treatment using NH 3 gas in the same chamber. The deposited P is nitrided to form a first nitride film, a second nitride film is formed over the first nitride film, and an upper electrode is formed after the oxide film is formed over the second nitride film. Accordingly, the present invention can omit the wet cleaning process prior to the dielectric film manufacturing process, thereby preventing carrier loss in the doped state of the lower electrode due to the cleaning process, and grains of narrow passage portions weakened by the growth of MPS grains. It is possible to prevent the breakage of in advance.
Description
본 발명은 반도체장치의 커패시터 제조방법에 관한 것으로, 특히 하부/상부전극들 사이에 내재되는 유전체 막질로서 질화막(nitride)과 실리콘막(silicon)의 복합층을 사용하여 고용량을 달성하는 커패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of manufacturing a capacitor using a composite layer of a nitride film and a silicon film as a dielectric film inherent between lower and upper electrodes. It is about.
현재 반도체장치의 고집적화를 달성하기 위하여 셀 면적의 감소 및 동작 전압의 저전압화에 관한 연구/개발이 활발하게 진행되고 있다. 더구나, 반도체장치의 고집적화가 이루어질수록 커패시터의 면적이 급격하게 감소되지만 기억소자의 동작에 필요한 전하 즉, 단위 면적에 확보되는 정전용량는 증가되어야만 한다.At present, in order to achieve high integration of semiconductor devices, research / development has been actively conducted on reduction of cell area and reduction of operating voltage. In addition, as the integration of semiconductor devices becomes higher, the area of the capacitor is drastically reduced, but the charge necessary for the operation of the memory device, that is, the capacitance secured in the unit area must be increased.
커패시터의 충분한 유전 용량을 확보하기 위해서는 유전막의 박막화, 유효 표면적의 증대 등의 구조적인 연구가 진행되고 있다. 또, 약 3-4 정도의 유전상수(ε)를 갖는 실리콘 산화막(SiO2) 대신에 고유전 물질로서 NO(Nitride-Oxide) 구조 또는 ONO(Oxide-Nitride-Oxide)구조라든지 Ta2O5또는 BST(BaSrTiO3) 등으로 대체하려는 재료적인 연구도 진행되고 있다.In order to secure a sufficient dielectric capacity of the capacitor, structural studies such as thinning of the dielectric film and increasing the effective surface area have been conducted. In addition, instead of the silicon oxide film (SiO 2 ) having a dielectric constant (ε) of about 3-4, a high dielectric material NO (Nitride-Oxide) structure or ONO (Oxide-Nitride-Oxide) structure or Ta 2 O 5 or Material studies are also underway to replace BST (BaSrTiO 3 ).
그 중에서도 NO 구조의 유전막은 제조 공정이 간단하면서도 고유전율을 확보할 수 있는 장점을 갖고 있다. 즉, NO 구조의 유전막을 사용하는 커패시터에서는 하부전극에 질화막(SiN)을 증착하고 그 위에 산화막(SiO2)을 적층해서 복합 NO 구조의 유전막을 형성함으로써 원하는 반도체소자의 용량을 얻고 있다.In particular, the dielectric film of the NO structure has the advantage of ensuring a high dielectric constant while a simple manufacturing process. In other words, in a capacitor using a dielectric film having a NO structure, a desired semiconductor device capacity is obtained by depositing a nitride film (SiN) on a lower electrode and then stacking an oxide film (SiO 2 ) thereon to form a dielectric film having a complex NO structure.
한편, 최근에는 커패시터의 고용량을 달성하기 위하여 선택적인 MPS(Metastable PolySilicon) 구조로 실리콘을 성장시켜서 표면이 요철 형태, 즉 단면적이 증가된 하부전극을 형성하고 있다.On the other hand, in recent years, silicon is grown in a selective MPS (Metastable PolySilicon) structure in order to achieve a high capacity of the capacitor to form a lower electrode having a concave-convex shape, that is, an increased cross-sectional area.
그러나, 이와 같은 선택적 MPS 공정을 진행한 후에 N/O 유전막 제조 공정시 대체로 유전막질을 양호하게 하기 위한 세정 공정을 진행하는데, 이때, 자연 산화막을 제거하기 위하여 희석된 HF 용액을 사용하기 때문에 MPS 그레인의 성장도에 따라 취약해진 좁은 통로(neck) 부위가 파단되는 경우가 있다. 즉, MPS 그레인 성장은 실리콘막 표면에서 실리콘 원자들의 이동에 의해 이루어지기 때문에 매트릭스내 그레인이 성장된 경계부분은 그 두께가 아주 얇아지게 된다. 그러므로, 이러한 부분에 형성된 자연산화막을 제거하는 세정 공정을 진행하게 되면 그레인이 파단되어 잔류하는 폴리계 잔여물로 인해 소자의 불량을 야기시킨다.However, after the selective MPS process, the N / O dielectric film manufacturing process generally proceeds with a cleaning process to improve the quality of the dielectric film. In this case, MPS grain is used because diluted HF solution is used to remove the native oxide film. Depending on the growth rate, the narrow neck area may be broken. That is, since MPS grain growth is caused by the movement of silicon atoms on the surface of the silicon film, the boundary where grains are grown in the matrix becomes very thin. Therefore, when the cleaning process is performed to remove the natural oxide film formed on such a portion, the grain breaks and causes a defect of the device due to the remaining poly-based residue.
그리고, 이와 같은 세정 공정을 생략하게 되면 하부전극과 유전막 사이에 존재하게 되는 자연산화막에 의해 Tox의 증가로 전체 커패시턴스가 낮아지는 문제점이 있었다.If the cleaning process is omitted, the total capacitance decreases due to the increase in Tox due to the natural oxide film existing between the lower electrode and the dielectric film.
또한, 하부전극에 P 도핑시 상당 부분의 P원자들은 하부전극의 표면 아래에 몰려 있고 이들중 일부는 전극의 표면에 흡착되어 있는 상태이기 때문에 상술한 세정 공정시 상당부분이 소실되어 하부전극의 캐리어 수가 감소하게 되는 문제점이 있었다.In addition, since a large portion of the P atoms are concentrated under the surface of the lower electrode and some of them are adsorbed on the surface of the electrode when P is doped to the lower electrode, a substantial portion of the P atoms is lost during the above-described cleaning process. There was a problem that the number is reduced.
본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 하부전극의 P 도핑을 실시하되, 그 표면에 P를 일정 두께로 축적시킨 다음, NH3가스를이용한 플라즈마 트리트먼트 공정을 실시하여 축적된 P를 질화시킴으로써 유전막 제조 공정 이전의 세정 공정을 생략할 수 있어 세정 공정으로 인한 하부전극의 도핑 상태의 캐리어 손실을 방지할 수 있고 MPS 그레인의 성장도에 따라 취약해진 좁은 통로(neck) 부위의 그레인의 파단을 미연에 방지할 수 있는 커패시터 제조방법을 제공하는데 있다.An object of the present invention is to perform the P doping of the lower electrode in order to solve the problems of the prior art as described above, by accumulating P on the surface of a predetermined thickness, and then by performing a plasma treatment process using NH 3 gas By nitriding the P, the cleaning process prior to the dielectric film manufacturing process can be omitted, thereby preventing carrier loss in the doped state of the lower electrode due to the cleaning process, and narrowing the neck area that is vulnerable due to the growth of MPS grains. It is to provide a capacitor manufacturing method that can prevent the fracture of the grain in advance.
도 1 내지 도 5는 본 발명에 따른 커패시터 제조방법을 설명하기 위한 공정 순서도.1 to 5 is a process flow chart for explaining a capacitor manufacturing method according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
10: 반도체기판의 구조물10: structure of semiconductor substrate
12: 하부 전극12: lower electrode
14: P 축적막14: P accumulation film
14': 제 1질화막14 ': first nitride film
16: 제 2질화막16: second nitride film
18: 산화막18: oxide film
20: 상부전극20: upper electrode
상기 목적을 달성하기 위하여 본 발명은 반도체장치의 커패시터 제조 방법에 있어서, 반도체기판에 하부전극을 형성하는 단계와, 하부전극 표면에 P를 축적시키고 동일한 챔버에서 NH3가스를 이용한 플라즈마 트리트먼트 공정을 실시하여 축적된 P를 질화시켜 제 1질화막을 형성하는 단계와, 제 1질화막 상부에 제 2질화막을 형성하는 단계와, 제 2질화막 표면을 산화처리하여 산화막을 형성하는 단계와, 산화막 상부에 상부전극을 형성하는 단계를 포함하여 이루어진다.In order to achieve the above object, the present invention provides a method of manufacturing a capacitor of a semiconductor device, the method comprising: forming a lower electrode on a semiconductor substrate, and accumulating P on the lower electrode surface and performing a plasma treatment process using NH 3 gas in the same chamber; Forming a first nitride film by nitriding the accumulated P, forming a second nitride film on the first nitride film, oxidizing the surface of the second nitride film to form an oxide film, and forming an upper portion on the oxide film. Forming an electrode.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 5는 본 발명에 따른 커패시터 제조방법을 설명하기 위한 공정 순서도로서, 이를 참조하여 본 발명의 실시예인 N/O 구조의 유전막을 갖는 커패시터 제조 공정을 설명하면 다음과 같다.1 to 5 are flowcharts illustrating a method for manufacturing a capacitor according to the present invention. Referring to this, a capacitor manufacturing process having a dielectric film having an N / O structure according to an embodiment of the present invention will be described below.
우선, 도 1에 도시된 바와 같이, 반도체 소자(예컨대, 모스 트랜지스터)가 형성된 반도체 기판의 구조물(10)에 도전체로서 도프트 폴리실리콘 및 언도프트 폴리실리콘을 증착하고 선택적 MPS 공정을 실시하여 요철 표면을 갖는 하부전극(12)을 형성한다.First, as shown in FIG. 1, doped polysilicon and undoped polysilicon are deposited as a conductor on the structure 10 of a semiconductor substrate on which a semiconductor element (eg, a MOS transistor) is formed, and a selective MPS process is performed to unevenness. A lower electrode 12 having a surface is formed.
여기서, 상기 하부전극(12)의 형태는 스택(stack), 트렌치(trench), 실린더(cylinder), 핀(fin), 스택 실린더(stack cylinder) 중에서 어느 하나로 한다.The lower electrode 12 may be formed of any one of a stack, a trench, a cylinder, a fin, and a stack cylinder.
그리고, 선택적 MPS 공정시 실리콘 원자(Si)의 이동에 의해 형성된 요철 표면을 갖는 하부전극(12)은 P가 부족하여 커패시턴스의 고갈 원인이 되기에 충분한 P를 공급하기 위하여 PH3처리를 실시해준다.In addition, the lower electrode 12 having the uneven surface formed by the movement of silicon atoms (Si) during the selective MPS process is subjected to PH 3 treatment to supply P sufficient to cause P depletion due to insufficient P.
이때, 하부전극(12)의 PH3처리시 플라즈마 도핑 공정을 이용하고 10W∼1000W의 전원하에서 PH3를 10sccm∼1000sccm로 공급하고 그 공정 시간을 조정하여 도프트 폴리실리콘에 도핑을 실시함과 동시에 도 2에 도시된 바와 같이 그 표면에 P를 축적(14)시킨다.At this time, a plasma doping process is used for the PH 3 treatment of the lower electrode 12, and PH 3 is supplied at 10 sccm to 1000 sccm under a power supply of 10 W to 1000 W, and the process time is adjusted to dope the doped polysilicon. As shown in Fig. 2, P is accumulated 14 on its surface.
그 다음, 도 3 및 도 4에 도시된 바와 같이 본 발명에 따른 N/O 구조의 유전체박막 제조 공정을 실시한다.Next, as illustrated in FIGS. 3 and 4, a process of manufacturing a dielectric thin film having an N / O structure according to the present invention is performed.
이에, 인시튜(in-situ)로 동일한 챔버에서 NH3가스를 이용한 플라즈마 트리트먼트 공정을 실시하여 축적된 P(14)를 질화시켜 제 1질화막(14')을 형성한다.이때, 제 1질화막(14')의 형성은 200℃∼600℃에서 진행하되, 반응 가스로서 O2또는 N2O를 추가할 수 있고, 제 1질화막(14')의 두께는 1Å∼20Å로 한다.Accordingly, in-situ, a plasma treatment process using NH 3 gas is performed in the same chamber to nitrate the accumulated P 14 to form the first nitride film 14 ′. 14 'formed of, but is held in 200 ℃ ~600 ℃, as the reaction gas it is possible to add O 2 or N 2 O, the first nitride film (14', the thickness of) will be 1Å~20Å.
그리고, 제 1질화막(14') 상부에 제 2질화막(16)을 형성한다. 이때, 제 2질화막(16)의 형성은, 통상의 세정 공정을 생략하고 제 1질화막(14')을 형성한 후에 연속해서 SiH2Cl2및 NH3또는 SiH4및 NH3를 이용하여 질화막을 형성하되, 소자에서 요구되는 Tox를 만족시키도록 제 2질화막(16) 두께를 정한다.A second nitride film 16 is formed on the first nitride film 14 '. At this time, the formation of the second nitride film 16 skips the usual cleaning process and forms the first nitride film 14 'and subsequently forms the nitride film using SiH 2 Cl 2 and NH 3 or SiH 4 and NH 3 . The thickness of the second nitride film 16 is determined so as to satisfy the Tox required in the device.
이어서, 제 2질화막(16) 상부 표면을 산화시켜 산화막(18)을 형성하여 본 발명에 따른 N/O 구조의 유전막 제조 공정을 완료한다.Subsequently, the upper surface of the second nitride film 16 is oxidized to form an oxide film 18 to complete the N / O dielectric film manufacturing process according to the present invention.
그 다음, 도 5에 도시된 바와 같이, N/O 구조의 유전막 상부에 도전체를 증착하여 상부전극(20)을 형성한다. 이때, 상부전극(20)의 도전체는 도프트 폴리실리콘 및 금속물질 중에서 어느 하나를 단독으로 형성하거나 이들을 조합해서 형성한다. 상기 금속 재료로는 TiN, TaN, W, WN, WSi, Ru, RuO2, Ir, IrO2, Pt 중에서 어느 하나를 사용한다.Next, as shown in FIG. 5, the upper electrode 20 is formed by depositing a conductor on the dielectric film having an N / O structure. In this case, the conductor of the upper electrode 20 is formed of any one of doped polysilicon and a metal material alone or a combination thereof. As the metal material, any one of TiN, TaN, W, WN, WSi, Ru, RuO 2 , Ir, IrO 2 , and Pt is used.
이에, 본 실시예에서는 상부전극(20) 제조 공정시 불순물이 도핑된 폴리실리콘을 증착하고, 도프트 폴리실리콘과 유전막 사이에 유전막의 전도 장벽(conduction barrier) 역할을 하는 금속을 추가하도록 한다.Thus, in the present embodiment, during the manufacturing process of the upper electrode 20, polysilicon doped with impurities is deposited, and a metal serving as a conduction barrier of the dielectric film is added between the doped polysilicon and the dielectric film.
상술한 바와 같이, 본 발명은 하부전극의 P 도핑을 실시하되 그 표면에도 P를 일정 두께로 축적시킨 다음, NH3가스를 이용한 플라즈마 트리트먼트 공정으로 축적된 P를 질화시킴으로써 N/O 구조의 유전막 제조 공정 이전에 HF 용액을 사용한 습식 세정 공정을 생략할 수 있어 통상의 세정 공정으로 인한 하부전극의 도핑 상태의 캐리어 손실을 방지할 수 있고 MPS 그레인의 성장도에 따라 취약해진 좁은 통로(neck) 부위의 그레인의 파단을 미연에 방지할 수 있다.As described above, in the present invention, a P / doping of the lower electrode is performed, but P is accumulated on the surface thereof to a certain thickness, and then the P deposited by a plasma treatment process using NH 3 gas is nitrided to form an N / O dielectric film. The wet cleaning process using HF solution can be omitted prior to the manufacturing process, thereby preventing carrier loss in the doped state of the lower electrode due to the conventional cleaning process, and narrow neck area weakened by the growth of MPS grain. The fracture of grain can be prevented beforehand.
또한, 본 발명은 하부 전극 표면에 축적된 P를 질화시킴으로써 하부전극과 유전막 사이의 계면 특성을 향상시킬 수 있는 이점이 있다.In addition, the present invention has the advantage of improving the interface characteristics between the lower electrode and the dielectric film by nitriding P accumulated on the lower electrode surface.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990064618A KR100342868B1 (en) | 1999-12-29 | 1999-12-29 | Method of forming capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990064618A KR100342868B1 (en) | 1999-12-29 | 1999-12-29 | Method of forming capacitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20010064422A KR20010064422A (en) | 2001-07-09 |
| KR100342868B1 true KR100342868B1 (en) | 2002-07-02 |
Family
ID=19631889
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990064618A KR100342868B1 (en) | 1999-12-29 | 1999-12-29 | Method of forming capacitor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100342868B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100518235B1 (en) * | 2003-12-19 | 2005-10-04 | 주식회사 하이닉스반도체 | Method for fabricating capacitor of semiconductor device |
| KR100564433B1 (en) | 2004-12-02 | 2006-03-28 | 주식회사 하이닉스반도체 | Method for forming capacitor of the semiconductor device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100479237B1 (en) * | 2002-05-24 | 2005-03-30 | 주성엔지니어링(주) | Method for fabricating lower electrode of capacitor used in semiconductor device |
-
1999
- 1999-12-29 KR KR1019990064618A patent/KR100342868B1/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100518235B1 (en) * | 2003-12-19 | 2005-10-04 | 주식회사 하이닉스반도체 | Method for fabricating capacitor of semiconductor device |
| KR100564433B1 (en) | 2004-12-02 | 2006-03-28 | 주식회사 하이닉스반도체 | Method for forming capacitor of the semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010064422A (en) | 2001-07-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6624069B2 (en) | Methods of forming integrated circuit capacitors having doped HSG electrodes | |
| CN100355085C (en) | Semiconductor element with tungsten oxide layer and method for its production | |
| KR100640631B1 (en) | Capacitor of semiconductor device and method for fabricating the same | |
| US6673668B2 (en) | Method of forming capacitor of a semiconductor memory device | |
| US7750385B2 (en) | Semiconductor interconnection structures and capacitors including poly-SiGe layers and metal contact plugs | |
| KR100618869B1 (en) | Semiconductor device including capacitor and method for fabricating the same | |
| KR20010059655A (en) | Method of forming capacitor with TaON dielectic layer | |
| JP2004320022A (en) | Semiconductor device capacitor and method for manufacturing the same | |
| US7300852B2 (en) | Method for manufacturing capacitor of semiconductor element | |
| US6448166B2 (en) | Method for forming a gate for semiconductor devices | |
| KR100342868B1 (en) | Method of forming capacitor | |
| KR100519514B1 (en) | Method of forming capacitor provied with TaON dielectric layer | |
| US6635524B2 (en) | Method for fabricating capacitor of semiconductor memory device | |
| US20050059206A1 (en) | Integrated circuit devices having barrier layers between upper electrodes and dielectric layers and methods of fabricating the same | |
| KR100327587B1 (en) | Method of forming capacitor provided with TaON dielectric layer | |
| US6323098B1 (en) | Manufacturing method of a semiconductor device | |
| KR100586540B1 (en) | Method of forming capacitor of semiconductor device | |
| US20040126964A1 (en) | Method for fabricating capacitor in semiconductor device | |
| KR100504434B1 (en) | Method of forming capacitor | |
| KR100510526B1 (en) | Capacitor of semiconductor device and method for fabricating the same | |
| KR20050064671A (en) | Method of manufacturing a flash memory device | |
| KR100842953B1 (en) | Method for forming capacitor of semiconductor device | |
| KR100532428B1 (en) | Capacitor of semiconductor device and method for fabricating the same | |
| KR100865545B1 (en) | Method for forming capacitor of semiconductor device | |
| KR20060011604A (en) | Method for manufacturing flash memory device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20100524 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |