KR100541799B1 - Capacitor Manufacturing Method for Semiconductor Devices - Google Patents

Abstract

A capacitor manufacturing method of a semiconductor device according to the present invention includes the steps of forming a gate electrode on a semiconductor substrate; Forming a source / drain region in the substrate on both edges of the gate electrode; Forming a first interlayer insulating film provided with DC on a front surface of the substrate including the gate electrode to expose a portion of the source / drain region on one side of the gate electrode; Forming a bit line on a predetermined portion on the first interlayer insulating film including the DC; Forming a second interlayer insulating film on the first interlayer insulating film including the bit line; Forming a BC by selectively etching the second interlayer insulating layer, the bit line, and the first interlayer insulating layer such that a surface of the source / drain region on the other side of the gate electrode is partially exposed; Forming a storage node electrode on a predetermined portion on the second interlayer insulating layer including the BC; Forming a dielectric film on a surface of the storage node electrode within a temperature range of 650 ° C. to 750 ° C .; Forming a plate electrode on the second interlayer insulating film including the dielectric film; And furnace anneal and RTP anneal to prevent degradation of the silicide film or degradation of the logic-side transistors caused during MDL fabrication, without degrading the DRAM cell caused when the capacitor is manufactured using a low temperature process. do.

Description

Capacitor Manufacturing Method for Semiconductor Devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and is particularly caused by a high temperature process in manufacturing a capacitor of a highly integrated DRAM or merged DRAM and logic (MDL) in which a DRAM and logic are merged The present invention relates to a method of manufacturing a capacitor of a semiconductor device capable of preventing performance degradation of a semiconductor device (particularly, a logic transistor).

As the degree of integration of semiconductor devices increases, complex chips (eg, memory) (such as DRAM) and logic are merged into one chip as a preliminary step in a system on chip product to meet various consumer demands. , MDL).

This MDL composite chip combines separate memory and logic products into a single chip, enabling smaller, lower power, higher speeds, and lower electro magnetic interferance (EMI) noise. Due to the need for high temperature heat treatment, logic transistors are subject to thermal stress (or heat burdget), which is still an unsolved task.

A high temperature heat treatment process which is most problematic in the MDL manufacturing process may include a capacitor forming process of a DRAM cell, which will be described with reference to the drawings illustrated in FIGS. 1 and 2. 1 is a cross-sectional view illustrating a conventional DRAM cell structure, and FIG. 2 is a process block diagram illustrating a DRAM cell manufacturing method of FIG. 1.

Referring to FIG. 1, in a conventional DRAM cell, a field oxide film 12 for defining an active region is formed in a device isolation region on a semiconductor substrate 10, and a predetermined portion of the active region and the field oxide film 12 is formed. A transfer transistor and a pass gate electrode 16a, which are composed of a source / drain region 22 and a cell gate electrode 16 and serve as a switching function, are formed on one side of the gate electrode 16. The bit line 26 is formed to be connected to the transfer transistor through a direct contact (DC) formed in the second portion 24, and the second interlayer insulating layer 28 and the bit line 26 are formed on the other side of the gate electrode 16. A capacitor composed of the storage electrode 30, the dielectric film 34, and the plate electrode 36 is connected to the transfer transistor through a buried contact formed in the first interlayer insulating film 24. It can be seen that the composed of the structure. Here, reference numerals 14, 18, 20, and 32 denote gate insulating films, silicide films, spacers, and hemi spherical grains (HSG), respectively.

Therefore, the DRAM cell of the above structure is manufactured through the ninth step as shown in FIG.

In a first step 100, a field oxide layer 12 is formed in an isolation region on a semiconductor substrate 10 to define an active region in which an active element is to be formed, and then a gate insulating layer 14 is formed in an active region on the substrate 10. ). Next, a polysilicon conductive film is formed on the gate insulating film 14 including the field oxide film 12, the conductive film and the gate insulating film 14 are selectively etched to pass through the gate electrode 16 and the pass gate of the transfer transistor. After forming the electrode 16a, a low concentration of impurities are implanted onto the substrate 10. Thereafter, spacers 20 made of an insulating material are formed on both sidewalls of the gate electrodes 16 and 16a, and a high concentration of impurities are ion implanted onto the substrate to form the inside of the substrate 10 at both edges of the gate electrode 16. A source / drain region 22 having a lightly doped drain (LDD) structure is formed in the gate, and then the silicide layer 18 is selectively formed only on the gate electrodes 16 and 16a. As a result, a transfer transistor including a source / drain region 22 and a gate electrode 16 is formed in the active region on the substrate 10, and a pass gate electrode 16a is formed on the field oxide film 12.

In a second step 102, a first interlayer insulating film 24 is formed on the entire surface of the resultant material, and the first insulating interlayer 24 is selectively etched to expose a portion of the source / drain region 22 on one side of the gate electrode 16. 24) to form a DC.

As a third step 104, a bit line 26 of a conductive film material is formed in a predetermined portion on the first interlayer insulating film 24 including the DC.

As a fourth step 106, a second interlayer insulating film 28 is formed on the first interlayer insulating film 24 including the bit line 26.

As a fifth step 108, the second interlayer insulating layer 28, the bit line 26, and the first interlayer insulating layer 24 are exposed to a predetermined portion of the surface of the source / drain region 22 on the other side of the gate electrode 16. Selective etching to form BC.

As a sixth step 110, a polysilicon storage electrode 30 doped with a high concentration of impurities is formed in a predetermined portion on the second interlayer insulating film 28 including BC, and then the storage electrode 30 is formed. The HSG 32 is formed on the surface of the storage electrode 30 to increase the contact area between the dielectric films to be formed.

As a seventh step 112, a dielectric film 34 having a NO structure is formed on a surface of the storage electrode 30 provided with the HSG 32. In this case, the dielectric film is manufactured by a CVD method to form a nitride film, and then proceed with a thermal oxidation process at 30 ± 5 minutes at a temperature around 830 ℃, in this way the thermal oxidation process at a temperature around 830 ℃ The reason is that the doped high concentration dopant in the storage electrode 30 is evenly diffused into the BC to sufficiently activate the storage electrode.

As an eighth step 114, a polysilicon plate electrode 36 doped with a high concentration of impurities is formed in a predetermined portion on the second interlayer insulating film 28 including the dielectric film 34. To complete.

However, when the capacitor of the DRAM cell is formed by applying the above-mentioned process, two problems arise in manufacturing the MDL.

First, in the process of forming the dielectric film 34 during capacitor manufacturing, a high-temperature thermal oxidation process of around 830 ° C. is generally required, which causes a phenomenon in which the transistor of the logic formation part receives thermal stress. When the logic transistor is subjected to thermal stress as described above, the threshold voltage of the channel region decreases as well as the junction depth of the high concentration source / drain region 22 is decreased due to the change in the concentration profile of the impurities. This lowering phenomenon and punch-through occur, causing a problem of degrading the performance of the logic transistor.

Second, since the silicide film formed in the gate electrode and the active region (source / drain region) of the logic transistor is agglomerated due to the high temperature thermal oxidation process, the silicide film is deteriorated, so that the resistance of the gate electrode constituting the transistor increases. Done. Since the deterioration of the silicide film is similarly shown in the DRAM cell forming portion in addition to the logic forming portion, there is an urgent need for improvement.

Accordingly, an object of the present invention is to make a dielectric film forming the capacitor through a low temperature process when manufacturing a highly integrated DRAM or MDL capacitor, a separate furnace anneal for activation of the storage electrode and the plate electrode after the plate electrode is formed By changing the process to add more RTP (rapid thermal process) and annealing processes, it is possible to prevent degradation of the transistor of the logic side or deterioration of the silicide layer without reducing the capacitance of the capacitor or increasing the BC resistance. A method of manufacturing a capacitor of a semiconductor device is provided.

In order to achieve the above object, in the present invention, forming a gate electrode on a semiconductor substrate; Forming a source / drain region in the substrate on both edges of the gate electrode; Forming a first interlayer insulating film provided with DC on a front surface of the substrate including the gate electrode to expose a portion of the source / drain region on one side of the gate electrode; Forming a bit line on a predetermined portion on the first interlayer insulating film including the DC; Forming a second interlayer insulating film on the first interlayer insulating film including the bit line; Forming a BC by selectively etching the second interlayer insulating layer, the bit line and the first interlayer insulating layer such that a surface of the source / drain region on the other side of the gate electrode is partially exposed; Forming a storage node electrode on a predetermined portion on the second interlayer insulating film including the BC; Forming a dielectric film on a surface of the storage node electrode within a temperature range of 650 to 750 ° C .; Forming a plate electrode on the second interlayer insulating film including the dielectric film; And performing a furnace anneal and an RTP anneal.

At this time, the furnace annealing is preferably carried out for 10 minutes to 3 hours in the temperature range of 650 ~ 800 ℃, the RTP annealing is preferably carried out for 10 seconds to 5 minutes within the temperature range of 800 ~ 975 ℃. Do.

When the capacitor is manufactured as described above, even if the dielectric film of the capacitor is formed at a low temperature of 650 ~ 750 ℃, it is possible to sufficiently activate the storage electrode and the plate electrode by using the furnace annealing process and the RTP annealing process, which is a subsequent process, It is possible to prevent the transistor's performance degradation or the silicide film from deteriorating without a decrease in capacitance or an increase in BC resistance that may occur during the process.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

According to the present invention, the capacitor of the DRAM is formed using a low temperature process, not a high temperature process, and after the capacitor is formed, a DRAM cell manufacturing process is performed by performing a separate furnace annealing and RTP annealing. A technology that focuses on preventing the degradation of the transistor and the degradation of the silicide film caused during the capacitor manufacturing without degrading the performance of the DRAM cell caused during manufacturing. This will be described with reference to FIG. 3.

3 is a flowchart illustrating a process for manufacturing a DRAM cell proposed in the present invention, and for convenience, the manufacturing method will be described by dividing the manufacturing method into ninth steps.

In a first step 200, a field oxide layer 12 is formed in an isolation region on a semiconductor substrate 10 to define an active region in which an active element is to be formed, and then a gate insulating layer 14 is formed in an active region on the substrate 10. ). Next, a polysilicon conductive film is formed on the gate insulating film 14 including the field oxide film 12, the conductive film and the gate insulating film 14 are selectively etched to pass through the gate electrode 16 and the pass gate of the transfer transistor. After forming the electrode 16a, a low concentration of impurities are implanted onto the substrate 10. Thereafter, spacers 20 made of an insulating material are formed on both sidewalls of the gate electrodes 16 and 16a, and a high concentration of impurities are ion implanted onto the substrate to form the inside of the substrate 10 at both edges of the gate electrode 16. A source / drain region 22 having a lightly doped drain (LDD) structure is formed in the gate, and then the silicide layer 18 is selectively formed only on the gate electrodes 16 and 16a. As a result, a transfer transistor including a source / drain region 22 and a gate electrode 16 is formed in the active region on the substrate 10, and a pass gate electrode 16a is formed on the field oxide film 12.

In a second step 202, a first interlayer insulating film 24 is formed on the entire surface of the resultant material, and the first insulating interlayer 24 is selectively etched to expose a portion of the source / drain region 22 on one side of the gate electrode 16. 24) to form a DC.

In a third step 204, a bit line 26 of a conductive film material is formed on a predetermined portion on the first interlayer insulating film 24 including the DC.

As a fourth step 206, a second interlayer insulating film 28 is formed on the first interlayer insulating film 24 including the bit line 26.

In a fifth step 208, the second interlayer insulating layer 28, the bit line 26, and the first interlayer insulating layer 24 are exposed to a predetermined portion of the surface of the source / drain region 22 on the other side of the gate electrode 16. Selective etching to form BC.

In a sixth step 210, a polysilicon storage electrode 30 doped with a high concentration of impurities is formed in a predetermined portion on the second interlayer insulating layer 28 including BC, and then the storage electrode 30 is formed. The HSG 32 is formed on the surface of the storage electrode 30 to increase the contact area between the dielectric films to be formed.

As a seventh step 212, a dielectric film 34 having a NO structure is formed on a surface of the storage electrode 30 having the HSG 32. In this case, the dielectric film is formed by forming a nitride film by CVD, and then performing a thermal oxidation process for 30 ± 5 minutes at a low temperature of 650 to 750 ° C.

As an eighth step 214, a polysilicon plate electrode 36 doped with a high concentration of impurities is formed in a predetermined portion on the second interlayer insulating layer 28 including the dielectric layer 34.

In a ninth step 216, an insulating film 38 of a CVD oxide film (eg, PEOX) is formed on the plate electrode 36, and then the conductivity of the plate electrode 36 and the storage electrode 30 is enhanced. Furnace annealing process for 10 minutes to 3 hours in the temperature range of 650 ~ 800 ℃ for the purpose of Joule, followed by RTP annealing process for 10 seconds to 5 minutes in the temperature range of 800 ~ 975 ℃ in succession 36) and the storage electrode 30 are sufficiently activated to complete the present process. In this case, the process of forming the insulating layer 38 may be skipped.

The furnace annealing process and the RTP annealing process are performed after the plate electrode 36 is formed in the same manner as in the case of forming the dielectric film 34 using a high temperature thermal oxidation process as in the related art. Although the dielectric film 34 is formed at a low temperature of 650 to 750 ° C., which is a temperature at which the silicide film does not deteriorate, as in the present invention, a high concentration of impurities doped in the storage electrode 30 to the inside of BC. Since it is impossible to diffuse enough, a lot of depletion occurs, and if the process is continued without furnace annealing or RTP annealing in this state, the capacitance of the capacitor and the BC resistance become large. This is to prevent the problem because the performance of the DRAM cell is raised.

According to an exemplary embodiment, when the capacitor of the DRAM is manufactured under the process conditions, even if the dielectric film 34 is formed at a low temperature, the storage electrode 30 may have good activation characteristics through the RTP annealing process, and thus the storage electrode 30 It is confirmed that the capacitor can maintain a stable capacitance regardless of the voltage change because the capacitance can be maintained even on the negative voltage, which is a region where) is activated.

In the process as described above, since the transistor of the DRAM is formed through a low temperature process, the transistor of the logic side does not undergo thermal stress during MDL manufacturing, and thus the threshold voltage is lowered due to the change in the concentration profile of the impurity during device manufacturing. The punch-through phenomenon can be eliminated to prevent the degradation of the logic transistor. In this case, a phenomenon in which the silicide layer 18 formed on the gate electrode, the active region (source / drain region) of the logic transistor, and the gate electrodes 16 and 16a of the DRAM cell forming portion of the logic transistor is deteriorated due to the low temperature process is also caused. Since it can be removed, it is possible to prevent the resistance of the gate electrode from increasing in the manufacturing of the capacitor.

As described above, according to the present invention, after the capacitor is formed through a low temperature process in the manufacture of highly integrated DRAM or MDL, the process is performed in a manner of further performing a separate annealing process (for example, furnace annealing and RTP annealing). By changing the structure, it is possible to prevent the degradation of the silicide film and the degradation of the silicide film caused by the MDL fabrication without degrading the DRAM cell caused by the capacitor manufacturing using the low temperature process. It can be implemented.

1 is a cross-sectional view showing a conventional general DRAM cell structure,

FIG. 2 is a process block diagram showing a DRAM cell manufacturing method shown in FIG.

3 is a process flowchart showing a DRAM cell manufacturing method shown in FIG. 1 according to the present invention.

Claims (5)

Forming a gate electrode on the semiconductor substrate; Forming a source / drain region in the substrate on both edges of the gate electrode; Forming a first interlayer insulating film provided with DC on a front surface of the substrate including the gate electrode to expose a portion of the source / drain region on one side of the gate electrode; Forming a bit line on a predetermined portion on the first interlayer insulating film including the DC; Forming a second interlayer insulating film on the first interlayer insulating film including the bit line; Forming a BC by selectively etching the second interlayer insulating layer, the bit line and the first interlayer insulating layer such that a surface of the source / drain region on the other side of the gate electrode is partially exposed; Forming a storage node electrode on a predetermined portion on the second interlayer insulating film including the BC; Forming a dielectric film on a surface of the storage electrode and performing a thermal oxidation process within a temperature range of 650 to 750 ° C; Forming a plate electrode on the second interlayer insulating film including the dielectric film; And After the furnace annealing was performed for 10 minutes to 3 hours in the temperature range of 650 ~ 800 ℃ to the resultant plate electrode formed, RTP annealing for 10 seconds to 5 minutes in the temperature range of 800 ~ 975 ℃ Capacitor manufacturing method of a semiconductor device, characterized in that consisting of. The method of claim 1, wherein the storage electrode and the plate electrode are formed of polysilicon doped with a high concentration of impurities. The method of claim 1, wherein the dielectric layer has a NO structure. The method of claim 1, further comprising forming an HSG on a surface of the storage electrode after forming the storage electrode. The method of claim 1, further comprising forming an insulating film thereon after the plate electrode is formed.